Learning Maps

Cadence Training Services learning maps provide a comprehensive visual overview of the
learning opportunities for Cadence customers. They provide recommended course flows as well
as tool experience and knowledge levels to guide students through a complete learning plan.
Learning Maps cover all Cadence® technologies and reference courses available worldwide.
For course names, descriptions, and schedules, please select the Browse Catalog button at
https://www.cadence.com/training.
Contents
• PCB Design and Analysis • System Design and Analysis • Computational Fluid Dynamics • Onboarding
• Custom IC, Analog, and RF Design • IC Package Design and Analysis • Safety and Reliability Platform
• Digital Design and Signoff • Mixed Signal Modeling and Verification • Tensilica® Processor IP
 Learning Mapand
PCB Design Digital Design
Analysis and Signoff
Learning Map
Logic Design PCB Design SI/PI Analysis Library Development

Beginner
Beginner

Allegro® X Design OrCAD® X Capture OrCAD X Presto Basic Essential High-Speed PCB DE-HDL Library Development
Entry HDL Front-to- Techniques Design for Signal Integrity using DE-HDL
Back Flow
Allegro X PCB Editor Basic
Techniques PCB Design at RF – Multi- DE-HDL Library Development
Allegro X Design OrCAD CIS
Gigabit Transmission, EMI using Allegro X System Capture
Entry HDL
Control, and PCB Materials
Basics
OrCAD X Capture Allegro X PCB Editor
Allegro X System Constraint Manager PCB Intermediate Techniques
Sigrity Aurora Allegro X EDM PCB Librarian
Capture Basics Flow

Allegro EDM Design Allegro X PCB Router Basics

Allegro X System Entry HDL Front-to- Sigrity PowerDC™ and
Capture Back Flow OptimizePI™
Allegro X PCB Editor
Analog Simulation Advanced Methodologies
Allegro Design Reuse with PSpice® SystemSI for Parallel Bus and
Serial Link Analysis
Analog Simulation
Allegro X High-Speed Constraint
Analog Simulation with PSpice ® using Allegro Design Entry HDL SKILL®
Management
with PSpice ® using System Capture Model Generation and Analysis Programming Language
Design Entry HDL Allegro DesignTrue DFM using PowerSI and Broadband
SPICE

Allegro X Update Training Clarity 3D Solver Allegro X PCB Editor SKILL

Programming Language
Advanced

Advanced
Advanced Design Verification Celsius Thermal Solver
with the RAVEL Programming
Language

New Course Number of days for instructor-led course Accelerated Learning Path Course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning Design
IC Package Map Digital Design and
and Analysis SignoffMap
Learning

Beginner
Beginner

IC Package Design SI/PI Analysis

Allegro® X Advanced Package Designer Sigrity Aurora

Allegro Sigrity Package Assessment and Model Extraction Sigrity PowerDC™ and OptimizePI™

OrbitIO™ System Planner SystemSI for Parallel Bus and Serial Link Analysis

Advanced Design Verification with the RAVEL Programming Model Generation and Analysis using PowerSI and Broadband SPICE
Language

Designing with Integrity 3D-IC Clarity 3D Solver

Celsius Thermal Solver

Advanced

Advanced
New Course Number of days for instructor-led course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 CustomLearning Map
IC/Analog Digital
Design andDesign and Signoff
Simulation Learning Map 1 of 3 – see next page

Design Verification

Beginner
Beginner

Circuit Schematic and Design Creation Spectre Simulations

Virtuoso Schematic Editor Spectre ® Simulator Virtuoso® ADE Verifier Series

Fundamentals Series S1 Setup, Run, & View Verifier Results
S1 Spectre Basics
S2 Reference Flow and Analog Coverage Using
Virtuoso® ADE Explorer & Assembler Series S2 Large-Signal Analyses the Setup Library Assistant
S1 ADE Explorer & Single Test Corner Analysis
S3 Small-Signal Analyses
S2 ADE Assembler & Multi Test Corner Analysis
S4 Spectre MDL
S3 Sweeping Variables and Simulating Corners

S4 Monte Carlo, Real-Time Tuning & Run Plans Design Checks and Asserts

Reliability Analysis
High-Performance Spectre
Simulation (APS, Spectre X)
Virtuoso Visualization and Analysis
Reliability Analysis in Virtuoso Studio
Spectre FX Simulator

Spectre FMC in Virtuoso ADE

Virtuoso ® Spectre ® Pro Series

S1 DC Algorithm
Advanced

Advanced
Virtuoso Spectre Transient Noise
S2 Transient Algorithm

Accelerated Learning Path Course

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning Map
RF/Microwave andDigital
System Design and
Design Signoff Map
Learning 2 of 3 – see next page

System Design AWR Microwave Design

Beginner
Beginner

RF Design and Simulations

Virtuoso Schematic Editor 5G mmWave Handset System Design – Microwave & RF Design (AWR ®)
S1 Simulation and Verification of the RFIC Microwave Office for RF Designers
(Transceiver)
Virtuoso® ADE Explorer & Assembler Series
S1 ADE Explorer & Single Test Corner Analysis
Planar EM Analysis in AWR Microwave Office

S2 ADE Assembler & Multi Test Corner Analysis

Spectre ® Simulator Fundamentals Series

S1 Spectre Basics

S2 Large-Signal Analyses

Spectre ® RF Series
RF Analysis Using Shooting Newton

RF Analysis Using Harmonic Balance

Advanced

Advanced
New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning
Custom IC/Analog Map
Physical Digital
Design andDesign and Signoff
Verification Learning Map 3 of 3 – see the start

IC CAD Physical Design and Advanced Nodes Physical Verification

Beginner
Beginner

SKILL® Language Virtuoso® Layout Design Basics Virtuoso® Layout Pro Series Pegasus Quantus™
Programming T1: Env. and Basic Commands Verification Extraction
Introduction
System Solution
T2: Create and Edit Commands Transistor-Level
SKILL Language Virtuoso Connectivity-Driven Series
Programming Layout Transition T3: Basic Commands
Physical T1: Overview
E
Verification and Technology
T4: Advanced Commands
System Setup
SKILL Development
of Parameterized Virtuoso Abstract Generator T5: Interactive Routing
Cells
T2: Parasitic
T6: Constraint-Driven Flow
Extraction
Virtuoso Floorplanner and Power Routing
Advanced SKILL Physical
T7: Module Generator Verification
Language
and Floorplanner Language T3: Extracted
Programming
Rules-Writer View Flows
T8: Concurrent Layout Editing
Virtuoso® Advanced-Node – ICADVM E
and
Advanced
Virtuoso Layout for Advanced T9: Virtuoso Design Planner E
Features
Nodes

T1: Place and Route

T2: Electromigration
Advanced

Advanced
Virtuoso Layout for Advanced
Nodes and Methodology
Platform E
Accelerated Learning Path Course

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning
Mixed-Signal Modeling, Map Digital
Simulation andDesign and Signoff
Verification Learning Map
Mixed-Signal Verification

Beginner
Beginner

Circuit Modeling Mixed-Signal Simulations

(GUI and Command-Line)
SystemVerilog for Design and Verification
AMS/Real Number Modeling
Virtuoso Schematic Editor
Analog Modeling with Verilog-A

Virtuoso® ADE Explorer & Assembler Series SystemVerilog Real Number Modeling (SV-
Behavioral Modeling with Verilog AMS RNM) Based Advanced Verification
S1 ADE Explorer & Single Test Corner Analysis

Real Modeling with Verilog-AMS S2 ADE Assembler & Multi Test Corner Analysis
Mixed-Signal Verification with UVM

Real Modeling with SystemVerilog

Mixed-Signal Design and Simulation
Mixed-Signal Simulations using Spectre AMS
Designer (GUI)

Command-Line Based Mixed-Signal Simulations

w/ Xcelium Use Model

SimVision for Debugging Mixed-Signal

Simulations
Advanced

Advanced
New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning Map Digital
Digital Design Design
and Signoff and Signoff
Learning Map
Synthesis and Test Implementation Silicon Signoff Equivalence Checking

Beginner
Beginner

Semiconductor 101
Digital IC Design Fundamentals
Cadence® RTL-to-GDSII Flow

Fundamentals of IEEE 1801 Low- Design For Test

Power Specification Fundamentals
Format
Genus™ Synthesis Solution with Innovus™ Block Implementation Basic Static Timing Analysis
Stylus Common UI with Stylus Common UI Conformal® Equivalence
Genus Low-Power Synthesis Checking
Innovus Hierarchical Tempus™ Signoff Timing
Flow with IEEE 1801
Implementation with Stylus Analysis and Closure with Stylus Conformal Low-Power
Low-Power Synthesis Flow Common UI Common UI Verification with CPF
with Genus Stylus Common UI
Innovus Low-Power Flow with Voltus™ Power Grid Analysis Conformal Low-Power
Genus Physical Synthesis Stylus Common UI and Signoff with Stylus Common Verification Using IEEE1801
Flow UI
Test Synthesis with Genus Stylus Innovus Clock Concurrent
Common UI Optimization Technology with Conformal ECO
Advanced Synthesis with Genus Stylus Common UI
Stylus Common UI
ATPG Flow with Modus DFT Cadence® Certus™ Signoff Closure Solution with Stylus Common UI
Software Solution
Joules™ Power Calculator
Advanced

Advanced
Virtuoso® Digital Implementation
Artificial Intelligence and Machine Learning Fundamentals
Cadence® Cerebrus™ Intelligent Chip Explorer
New Course Number of days for Instructor-led Course Online Course Available Digital Badge Available Accelerated Learning Path Course © 2023 Cadence Design Systems, Inc.
 System Design and Verification Learning Map
Simulation, Coverage and Debug

Beginner
Beginner
Beginnr

Digital IC Design Fundamentals Xcelium™ Simulator Protium™ Introduction Palladium ® Introduction

Specman® Fundamentals for

Block-Level Environment
Cadence® RTL-To-GDSII Foundations of Metric-Driven Developers
Flow Verification Verisium™ Debug

Low-Power Simulation with

CPF
Xcelium Integrated
Coverage
Low-Power Simulation with
IEEE1801 UPF

VIP Basic Building Blocks and Verisium™ Manager Perspec™ System Verifier -
Usage Basic

UCIe VIP Introduction

Advanced

vManager Tool Usage in Batch Xcelium Fault Simulator Specman Advanced Verification
Advanced

Advanced
Mode

New Course Number of days for instructor-led course Accelerated Learning Path Course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning
System Mapand
Design Digital Design and
Verification SignoffMap
Learning
Design and Verification Languages

Beginner
Beginner

Verilog Language and Application VHDL Language and C++ Language Fundamentals
Application for Design and Verification

SystemC® Language
Real Modeling with Verilog Fundamentals
AMS SystemVerilog for Design and
Verification

SystemC Synthesis
Real Modeling with with Stratus HLS
SystemVerilog
UVM
SystemVerilog Assertions
Essential SystemVerilog for UVM SystemC Transaction-Level
SystemVerilog Real Number (optional) Modeling TLM2.0
Modeling (SV-RNM) Based
Advanced Verification SystemVerilog Accelerated
Verification Using UVM Jasper® Formal
Fundamentals
Perl for EDA Engineering
Advanced

Advanced
Tcl Scripting for EDA SystemVerilog Advanced Register Jasper® Formal Expert
Verification Using UVM

New Course Number of days for instructor-led course Accelerated Learning Path Course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning
Safety and Map DigitalPlatform
Reliability Design and Signoff
Learning Map
MIDAS Safety Platform

Beginner
Beginner

MIDAS™ Safety Platform Introduction

Midas™ Safety Analysis Authoring

Xcelium Fault Simulator

Functional Safety Implementation and

Verification with Midas™
Advanced

Advanced
New Course Number of days for instructor-led course Accelerated Learning Path Course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning Map
Tensilica Digital Design
Processor and Signoff
IP Learning Map 1 of 2 – see next page

Tensilica Xtensa LX ConnX DSP Fusion & FloatingPoint HiFi Audio DSP Vision DSP
DSP
Tensilica® Xtensa® LX
Processor Fundamentals

Tensilica Xtensa LX Tensilica ConnX BBE16EP Tensilica Fusion F1 DSP Tensilica Audio Codec API Tensilica Vision DSP Family
Processor Interfaces Baseband Engine

Tensilica Xtensa LX Tensilica ConnX BBE32EP Tensilica Fusion G3 DSP Tensilica HiFi 2/EP/Mini Tensilica Xtensa Neural
Hardware Verification and Baseband Engine Audio Engine ISA Network Compiler v2
EDA

Tensilica HiFi 3 Audio

Tensilica Instruction Tensilica ConnX BBE64EP Tensilica Fusion G6 DSP Engine ISA Tensilica DNA 100
Extension Language and Baseband Engine Architecture and
Design Programming
Tensilica HiFi 4 DSP
Tensilica System Tensilica ConnX 110 and Tensilica FloatingPoint
Modeling using XTSC 120 DSP Family DSP Family

Tensilica HiFi 5 DSP

Tensilica Xtensa Audio

Framework

New Course Number of days for instructor-led course Online Course Available © 2020 Cadence Design Systems, Inc.
 Learning Map
Tensilica Digital Design
Processor and Signoff
IP Learning Map 2 of 2 – see prior page

Tensilica Xtensa NX ConnX DSP Vision DSP

Tensilica® Xtensa® NX
Processor Fundamentals

Tensilica Xtensa NX Tensilica ConnX B10 Tensilica Vision DSP Family

Processor Interfaces DSP

Tensilica Xtensa NX Tensilica ConnX B20 Tensilica Xtensa Neural

Hardware Verification and DSP Network Compiler v2
EDA

Tensilica Instruction
Extension Language and
Design

Tensilica System
Modeling using XTSC

New Course Number of days for instructor-led course Online Course Available © 2020 Cadence Design Systems, Inc.
 Learning Map DigitalFluid
Computational Design and Signoff
Dynamics

Beginner
Beginner

CFD Academy Fidelity Fine

Turbomachinery Meshing Auto Aero Marine

CFD Online Course Fidelity Turbo: Fidelity Automesh for Fidelity Flow Fine Marine for Beginners
Introduction Unstructured Meshing

Fidelity Pointwise Fine Marine for Advanced Users

Meshing Foundations
Advanced

Advanced
New Course Number of days for instructor-led course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning Map Digital Design
Onboarding and Signoff
Curricula

Beginner
Beginner

PCB Design Custom IC, Analog, and RF Design Digital Design and Signoff System Design and Verification

PCB Layout Designer Analog Circuit Design and Simulation

Semiconductor 101
Onboarding Onboarding

Schematic Capture for Virtuoso Layout Onboarding

Digital IC Design Fundamentals
EEs Onboarding

Cadence® RTL-to-GDSII Flow

Advanced

Advanced
See also: https://www.cadence.com/en_US/home/training/bridging-the-learning-gap/onboarding-curricula.html
New Course Number of days for instructor-led course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
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