UNIT – II: PROGRAMMING OF 8085 PROCESSOR

PART - B

Unit – II: PART – B

1. Discuss in detail about the 8085 Instruction set, explaining about the various types of
operations. (Nov2013/May2016/Apr2018/May2019)
Instruction Set of 8085
 An instruction is a binary pattern designed inside a microprocessor to perform a specific function.
 The entire group of instructions that a microprocessor
supports is called Instruction Set.
 8085 has 246 instructions.
 Each instruction is represented by an 8-bit binary value.
 These 8-bits of binary value is called Op-Code or Instruction Byte.
Classification of Instruction Set
 Data Transfer Instruction
 Arithmetic Instructions
 Logical Instructions
 Branching Instructions
 Control Instructions
Data Transfer Instructions
 These instructions move data between registers, or between memory and registers.
 These instructions copy data from source todestination.
 While copying, the contents of source are not modified.

Opcode Operand Explanation of Description

Instruction

MOV Rd, Rs Copy from This instruction copies the contents of the source register
M, Rs source(Rs) to into the destination register; the contents of the source
Rd, M destination(Rd) register are not altered. If one of the operands is a
memory location, its location is specified by the contents
of the HL registers.
Example: MOV B, C or MOV B, M

MVI Rd, data Move immediate 8- The 8-bit data is stored in the destination register or
M, data bit memory. If the operand is a memory location, its location
is specified by the contents of the HL registers.
Example: MVI B, 57H or MVI M, 57H

LDA 16-bit Load accumulator The contents of a memory location, specified by a 16-bit
address address in the operand, are copied to the accumulator. The
contents of the source are not altered.
Example: LDA 2034H

LDAX B/D Reg. Load accumulator The contents of the designated register pair point to a
pair indirect memory location. This instruction copies the contents of
that memory location into the accumulator. The contents
of either the register pair or the memory location are not
altered.
Example: LDAX B
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LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair
16-bit data immediate designated in the operand.
Example: LXI H, 2034H or LXI H, XYZ

LHLD 16-bit Load H and L The instruction copies the contents of the memory
address registers direct location pointed out by the 16-bit address into register L
and copies the contents of the next memory location into
register H. The contents of source memory locations are
not altered.
Example: LHLD 2040H

STA 16-bit 16-bit address The contents of the accumulator are copied into the
address memory location specified by the operand. This is a 3-
byte instruction, the second byte specifies the low-order
address and the third byte specifies the high-order
address.
Example: STA 4350H

STAX Reg. pair Store accumulator The contents of the accumulator are copied into the
indirect memory location specified by the contents of the operand
(register pair). The contents of the accumulator are not
altered.
Example: STAX B

SHLD 16-bit Store H and L The contents of register L are stored into the memory
address registers direct location specified by the 16-bit address in the operand and
the contents of H register are stored into the next memory
location by incrementing the operand. The contents of
registers HL are not altered. This is a 3-byte instruction,
the second byte specifies the low-order address and the
third byte specifies the high-order address.
Example: SHLD 2470H

XCHG none Exchange H and L The contents of register H are exchanged with the
with D and E contents of register D, and the contents of register L are
exchanged with the contents of register E.
Example: XCHG

SPHL none Copy H and L The instruction loads the contents of the H and L registers
registers to the stack into
pointer the stack pointer register, the contents of the H register
provide the high-order address and the contents of the L
register provide the low-order address. The contents of
the H
and L registers are not altered.
Example: SPHL

XTHL none Exchange H and L The contents of the L register are exchanged with the
with top of stack stack location pointed out by the contents of the stack
pointer register. The contents of the H register are
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exchanged with the next stack location (SP+1); however,

the contents of the stack pointer register are not altered.
Example: XTHL

PUSH Reg. pair Push register pair The contents of the register pair designated in the operand
onto stack are copied onto the stack in the following sequence. The
stack pointer register is decremented and the contents of
the highorder register (B, D, H, A) are copied into that
location. The stack pointer register is decremented again
and the contents of the low-order register (C, E, L, flags)
are copied to that location.
Example: PUSH B or PUSH A

POP Reg. pair Pop off stack to The contents of the memory location pointed out by the
register pair stack pointer register are copied to the low-order register
(C, E, L, status flags) of the operand. The stack pointer is
incremented by 1 and the contents of that memory
location are copied to the high-order register (B, D, H, A)
of the operand. The stack pointer register is again
incremented by 1.
Example: POP H or POP A

OUT 8-bit port Output data from The contents of the accumulator are copied into the I/O
address accumulator to a port specified by the operand.
port with 8-bit Example: OUT F8H
address

IN 8-bit port Input data to The contents of the input port designated in the operand
address accumulator from a are read and loaded into the accumulator.
port with 8-bit Example: IN 8CH
address

Arithmetic Instructions
 These instructions perform the operations like:
 Addition
 Subtract
 Increment
 Decrement
Addition
 Any 8-bit number, or the contents of register, or the contents of memory location can be added to
the contents of accumulator.
 The result (sum) is stored in the accumulator.
 No two other 8-bit registers can be added directly.
 Example: The contents of register B cannot be added directly to the contents of register C.
Subtraction
 Any 8-bit number, or the contents of register, or the contents of memory location can be subtracted
from the contents of accumulator.
 The result is stored in the accumulator.
 Subtraction is performed in 2’s complement form.
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 If the result is negative, it is stored in 2’s complement form.

 No two other 8-bit registers can be subtracted directly.
Increment / Decrement
 The 8-bit contents of a register or a memory location can be incremented or decremented by 1.
 The 16-bit contents of a register pair can be incremented or decremented by 1.
 Increment or decrement can be performed on any register or a memory location.
Opcode Operand Explanation of Description
Instruction

ADD R Add register or The contents of the operand (register or memory) are added to
M memory, to the contents of the accumulator and the result is stored in the
accumulator accumulator. If the operand is a memory location, its location
is specified by the contents of the HL registers. All flags are
modified to reflect the result of the addition.
Example: ADD B or ADD M

ADC R Add register to The contents of the operand (register or memory) and M the
M accumulator with Carry flag are added to the contents of the accumulator and
carry the result is stored in the accumulator. If the operand is a
memory location, its location is specified by the contents of
the HL registers. All flags are modified to reflect the result of
the addition.
Example: ADC B or ADC M

ADI 8-bit Add immediate to The 8-bit data (operand) is added to the contents of the
data accumulator accumulator and the result is stored in the accumulator. All
flags are modified to reflect the result of the addition.
Example: ADI 45H

ACI 8-bit Add immediate to The 8-bit data (operand) and the Carry flag are added to the
data accumulator with contents of the accumulator and the result is stored in the
carry accumulator. All flags are modified to reflect the result of the
addition.
Example: ACI 45H

DAD Reg. Add register pair The 16-bit contents of the specified register pair are added to
pair to H and L the contents of the HL register and the sum is stored in the
registers HL register. The contents of the source register pair are not
altered. If the result is larger than 16 bits, the CY flag is set.
No other flags are affected.
Example: DAD H

SUB R Subtract register The contents of the operand (register or memory ) are
M or memory from subtracted from the contents of the accumulator, and the
accumulator result is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL
registers. All flags are modified to reflect the result of the
subtraction.
Example: SUB B or SUB M
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SBB R Subtract source The contents of the operand (register or memory ) and M the
M and borrow from Borrow flag are subtracted from the contents of the
accumulator accumulator and the result is placed in the accumulator. If the
operand is a memory location, its location is specified by the
contents of the HL registers. All flags are modified to reflect
the result of the subtraction.
Example: SBB B or SBB M

SUI 8-bit Subtract The 8-bit data (operand) is subtracted from the contents of the
data immediate from accumulator and the result is stored in the accumulator. All
accumulator flags are modified to reflect the result of the subtraction.
Example: SUI 45H

SBI 8-bit Subtract The contents of register H are exchanged with the contents of
data immediate from register D, and the contents of register L are exchanged with
accumulator with the contents of register E.
borrow Example: XCHG

INR R Increment register The contents of the designated register or memory) are
M or memory by 1 incremented by 1 and the result is stored in the same place. If
the operand is a memory location, its location is specified by
the contents of the HL registers.
Example: INR B or INR M

INX R Increment register The contents of the designated register pair are incremented
pair by 1 by 1 and the result is stored in the same place.
Example: INX H

DCR R Decrement The contents of the designated register or memory are M

M register or decremented by 1 and the result is stored in the same place. If
memory by 1 the operand is a memory location, its location is specified by
the contents of the HL registers.
Example: DCR B or DCR M

DCX R Decrement The contents of the designated register pair are decremented
register pair by 1 by 1 and the result is stored in the same place.
Example: DCX H

DAA None Decimal adjust The contents of the accumulator are changed from a binary
accumulator value to two 4-bit binary coded decimal (BCD) digits. This is
the only instruction that uses the auxiliary flag to perform the
binary to BCD conversion, and the conversion procedure is
described below. S, Z, AC, P, CY flags are altered to reflect
the results of the operation.
If the value of the low-order 4-bits in the accumulator is
greater than 9 or if AC flag is set, the instruction adds 6 to the
low-order four bits.
If the value of the high-order 4-bits in the accumulator is
greater than 9 or if the Carry flag is set, the instruction adds 6
to the high-order four bits.
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Example: DAA

Logical Instructions
 These instructions perform logical operations on data stored in registers, memory and status flags.
 The logical operations are:
 AND
 OR
 XOR
 Rotate
 Compare
 Complement
AND, OR, XOR
 Any 8-bit data, or the contents of register, or memory location can logically have
 AND operation
 OR operation
 XOR operation
with the contents of accumulator.
 The result is stored in accumulator.
Rotate
 Each bit in the accumulator can be shifted either left or right to the next position.
Compare
 Any 8-bit data, or the contents of register, or memory location can be compares for:
 Equality
 Greater Than
 Less Than
with the contents of accumulator.
 The result is reflected in status flags.
Complement
 The contents of accumulator can be complemented.
 Each 0 is replaced by 1 and each 1 is replaced by 0.
Opcode Operand Explanation of Description
Instruction

CMP R Compare register The contents of the operand (register or memory) are M
M or memory with compared with the contents of the accumulator. Both contents
accumulator are preserved . The result of the comparison is shown by
setting the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
Example: CMP B or CMP M

CPI 8-bit Compare The second byte (8-bit data) is compared with the contents of
data immediate with the accumulator. The values being compared remain
accumulator unchanged. The result of the comparison is shown by setting
the flags of the PSW as follows:
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if (A) < data: carry flag is set

if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H

ANA R Logical AND The contents of the accumulator are logically ANDed with M
M register or the contents of the operand (register or memory), and the
memory with result is placed in the accumulator. If the operand is a
accumulator memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANA B or ANA M

ANI 8-bit Logical AND The contents of the accumulator are logically ANDed with
data immediate with the
accumulator 8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANI 86H

XRA R Exclusive OR The contents of the accumulator are Exclusive ORed with M
M register or the contents of the operand (register or memory), and the
memory with result is placed in the accumulator. If the operand is a
accumulator memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: XRA B or XRA M

XRI 8-bit Exclusive OR The contents of the accumulator are Exclusive ORed with the
data immediate with 8-bit data (operand) and the result is placed in the
accumulator accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: XRI 86H

ORA R Logical OR The contents of the accumulator are logically ORed with M
M register or the contents of the operand (register or memory), and the
memory with result is placed in the accumulator. If the operand is a
accumulator memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: ORA B or ORA M

ORI 8-bit Logical OR The contents of the accumulator are logically ORed with the
data immediate with 8-bit data (operand) and the result is placed in the
accumulator accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: ORI 86H

RLC None Rotate Each binary bit of the accumulator is rotated left by one
accumulator left position. Bit D7 is placed in the position of D0 as well as in
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the Carry flag. CY is modified according to bit D7. S, Z, P,

AC are not affected.
Example: RLC

RRC none Rotate Each binary bit of the accumulator is rotated right by one
accumulator right position. Bit D0 is placed in the position of D7 as well as in
the Carry flag. CY is modified according to bit D0. S, Z, P,
AC are not affected.
Example: RRC

RAL None Rotate Each binary bit of the accumulator is rotated left by one
accumulator left position through the Carry flag. Bit D7 is placed in the Carry
through carry flag, and the Carry flag is placed in the least significant
position D0. CY is modified according to bit D7. S, Z, P, AC
are not affected.
Example: RAL

RAR None Rotate Each binary bit of the accumulator is rotated right by one
accumulator right position through the Carry flag. Bit D0 is placed in the Carry
through carry flag, and the Carry flag is placed in the most significant
position D7. CY is modified according to bit D0. S, Z, P, AC
are not affected.
Example: RAR

CMA None Complement The contents of the accumulator are complemented. No flags
accumulator are affected.
Example: CMA

CMC None Complement carry The Carry flag is complemented. No other flags are affected.
Example: CMC

STC None Set Carry Set Carry

Example: STC

Branching Instructions
 The branching instruction alter the normal sequential flow.
 These instructions alter either unconditionally or conditionally.

Opcode Operand Explanation of Description

Instruction

JMP 16-bit Jump The program sequence is transferred to

address unconditionally the memory location specified by the 16-
bit address given in the operand.
Example: JMP 2034H or JMP XYZ

Flag 16-bit Jump The program sequence is transferred to

Opcode Description address conditionally the memory location specified by the 16-
Status
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Jump on CY = bit address given in the operand based on

JC the specified flag of the PSW as described
Carry 1
below.
Jump on no CY =
JNC Example: JZ 2034H or JZ XYZ
Carry 0
Jump on
JP S=0
positive
Jump on
JM S=1
minus
Jump on
JZ Z=1
zero
Jump on no
JNZ Z=0
zero
Jump on
JPE P=1
parity even
Jump on
JPO P=0
parity odd

Flag 16-bit Unconditional The program sequence is transferred to

Opcode Description address subroutine call the memory location specified by the 16-
Status
bit address given in the operand. Before
Call on CY =
CC the transfer, the address of the next
Carry 1
instruction after CALL (the contents of
Call on no CY = the program counter) is pushed onto the
CNC
Carry 0 stack.
Call on Example: CALL 2034H or CALL XYZ
CP S=0
positive
Call on
CM S=1
minus
Call on
CZ Z=1
zero
Call on no
CNZ Z=0
zero
Call on
CPE P=1
parity even
Call on
CPO P=0
parity odd

RET none Return from The program sequence is transferred from

subroutine the subroutine to the calling program. The
unconditionally two bytes from the top of the stack are
copied into the program counter,and
program execution begins at the new
address.
Example: RET
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Flag none Return from The program sequence is transferred from

Opcode Description subroutine the subroutine to the calling program
Status
conditionally based on the specified flag of the PSW as
Return on CY =
RC described below. The two bytes from the
Carry 1
top of the stack are copied into the
Return on CY = program counter, and program execution
RNC
no Carry 0 begins at the new address.
Return on Example: RZ
RP S=0
positive
Return on
RM S=1
minus
Return on
RZ Z=1
zero
Return on
RNZ Z=0
no zero
Return on
RPE P=1
parity even
Return on
RPO P=0
parity odd

PCHL none Load program The contents of registers H and L are

counter with HL copied into the program counter. The
contents contents of H are placed as the high-order
byte and the contents of L as the low-
order byte.
Example: PCHL

RST 0-7 Restart The RST instruction is equivalent to a 1-

byte call instruction to one of eight
memory locations depending upon the
number. The instructions are generally
used in conjunction with interrupts and
inserted using external hardware.
However these can be used as software
instructions in a program to transfer
program execution to one of the eight
locations. The addresses are:
Resta
Instruc rt
tion Addr
ess
0000
RST 0
H
0008
RST1
H
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0010
RST 2
H
0018
RST 3
H
0020
RST 4
H
0028
RST 5
H
0030
RST 6
H
0038
RST 7
H
The 8085 has four additional interrupts
and these interrupts generate RST
instructions internally and thus do not
require any external hardware. These
instructions and their Restart addresses
are:
Resta
Interr rt
upt Addre
ss
TRA 0024
P H
RST 002C
5.5 H
RST 0034
6.5 H
RST 003C
7.5 H

Control Instructions
 The control instructions control the operation of microprocessor.
Opcode Operand Explanation of Description
Instruction

NOP None No operation No operation is performed. The instruction is fetched and

decoded. However no operation is executed.
Example: NOP

HLT None Halt and enter The CPU finishes executing the current instruction and halts any
wait state further execution. An interrupt or reset is necessary to exit from
the halt state.
Example: HLT
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DI None Disable The interrupt enable flip-flop is reset and all the interrupts
interrupts except the TRAP are disabled. No flags are affected.
Example: DI

EI None Enable The interrupt enable flip-flop is set and all interrupts are
interrupts enabled. No flags are affected. After a system reset or the
acknowledgement of an interrupt, the interrupt enable flipflop is
reset, thus disabling the interrupts. This instruction is
necessary to reenable the interrupts (except TRAP).
Example: EI

RIM None Read interrupt This is a multipurpose instruction used to read the status of
mas interrupts 7.5, 6.5, 5.5 and read serial data input bit. The
instruction loads eight bits in the accumulator with the following
interpretations.
Example: RIM

SIM none Set interrupt This is a multipurpose instruction and used to implement the
mask 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The
instruction interprets the accumulator contents as follows.
Example: SIM

RIM Instruction
RIM Read Interrupt Mask
 This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read
serial data input bit.
 The instruction loads eight bits in the accumulatorwith the following interpretations.
2. Explain the instruction format and addressing modes of 8085 microprocessor.
(May2015/Nov2015/Apr2018/May2019/Nov2019)
Instruction Format :
An instruction is a command to the microprocessor to perform a given task on a specified data. Each
instruction has two parts: one is task to be performed, called the operation code (opcode), and the second is
the data to be operated on, called the operand.
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
Addressing Modes in 8085:
The method by which the address of source of data or the address of destination of result is given in the
instruction is called Addressing Modes
 The term addressing mode refers to the way in which the operand of the instruction is specified.
Intel 8085 uses the following addressing modes
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Indirect Addressing Mode
5. Implied/implicit Addressing Mode
Immediate Addressing
In immediate addressing mode, the data is specified in the instruction itself. The data will be apart of the
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
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program instruction. All instructions that have ‘I’ in their mnemonics are of Immediate
addressing type.
Eg.MVI B, 3EH- Move the data 3EH given in the instruction to B register.
Direct Addressing
In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory.
In this addressing mode, the program instructions and data can be stored in
Different memory blocks. This type of addressing can be identified by 16-bit address present in the
instruction. Eg. LDA 1050H- Load the data available in memory location 1050H in accumulator.
Register Addressing
In register addressing mode, the instruction specifies the name of the register in which the data is
available. This type of addressing can be identified by register names (such as ‘A’, ‘B’....) in the
instruction.
Eg.MOV A, B -Move the content of B register to A register.
Register Indirect Addressing
In register indirect addressing mode, the instruction specifies the name of the register in which the
address of the data is available. Here the data will be in memory and the address will be in the
register pair. This type of addressing can be identified by letter ‘M’ present in the instruction.
Eg.MOV A, M - The memory data addressed by HL pair is moved to A register.
Implied Addressing
In implied addressing mode, the instruction itself specifies the type of operation and location of
data to be operated. This type of instruction does not have any address, register name, immediate
data specified along with it. Eg CMA - Complement the content of accumulator.

3. i. Draw the timing diagram for STA XXXX and LDA XXXX instruction of 8085.

Timing diagram for STA 526AH

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STA means Store Accumulator -The contents of the accumulator is stored in the specified address (526A).
The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH (see fig). - OF
machine cycle.Then the lower order memory address is read (6A). - Memory Read Machine Cycle
Read the higher order memory address (52).- Memory Read Machine Cycle
The combination of both the addresses are considered and the content from accumulator is written in 526A.
- Memory Write Machine Cycle.Assume the memory address for the instruction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 526A.

Timing diagram for LDA XXXX

Explanation:
The LDA XXXX command performs loading the content of location XXXX into the accumulator and this
operation is performed by 13 T states comprising of opcode fetch(4T) and three memory read operation of
total 9T states.
ii. Draw the timing diagram of the instruction MVI B, 45. Assume the memory address of the
opcode and the data is 2000H and 2001H respectively.
Explanation of the command – It stores the immediate 8 bit data to a register or memory location.
Example:MVIB,45
Opcode:MVI
Operand: B is the destination register and 45 is the source data which needs to be transferred to the register.
’45’ data will be stored in the B register.
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Algorithm –
Decide what the opcode is and what the data is. Here, opcode is ‘MVI B’ and data is 45.
The opcode fetch will be same in all the instructions.
Only the read instruction of the opcode needs to be added in the successive T states.
For the opcode fetch the IO/M (low active) = 0, S1 = 1 and S0 = 1. Also, 4 T states will be required to fetch
the opcode from memory.
For the opcode read the IO/M (low active) = 0, S1 = 1 and S0 = 0. Also, only 3 T states will be required to
read data from memory.
In Opcode fetch (t1-t4 T states) –
00 – lower bit of address where opcode is stored.
20 – Higher bit of address where opcode is stored.
ALE – Provides signal for multiplexed address and data bus. Only in t1 it used as address bus to fetch lower
bit of address otherwise it will be used as data bus.
RD (low active) – Signal is 1 in t1 & t4, no data is read by microprocessor. Signal is 0 in t2 & t3, data is
read by microprocessor.
WR (low active) – Signal is 1 throughout, no data is written by microprocessor.
IO/M (low active) – Signal is 0 in throughout, operation is performing on memory.
S0 and S1 – Signal is 1 in t1 to t4 states, as to fetch the opcode from the memory.
In Opcode read (t5-t7 T states) –
01 – Lower bit of address where data is stored.
20 – Higher bit of address where data is stored.
ALE – Provides signal for multiplexed address and data bus. Only in t5 it used as address bus to fetch lower
bit of address otherwise it will be used as data bus.
RD (low active) – Signal is 1 in t5 as no data is read by microprocessor. Signal is 0 in t6 & t7 as data is read
by microprocessor.
WR (low active) – Signal is 1 throughout, no data is written by microprocessor.
IO/M (low active) – Signal is 0 in throughout, operation is performing
on memory.
S0 – Signal is 0 in throughout, operation is performing on memory to read data 45.
S1 – Signal is 1 throughout, operation is performing on memory to read data 45.

4. (i) Write an ALP using 8085 instructions to find the biggest number in a block of data
stored in the memory locations from 70H-7FH. (Apr2018)
MEMORY LABEL MNEMONIC HEX COMMENT
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PART - B

CODE
4400 LXI H,4200 21 Load the array size to the HL pair
4401 00
4402 42
4403 MOV B,M 46 Copy the array size to B register
4404 INX H 23 Increment the memory
4405 MOV A,M 7E Copy the first data to the
Accumulator
4406 DCR B 05 Decrement the Array size by 1
4407 LOOP INX H 23 Increment the memory
4408 CMP M BE Compare accumulator content and
memory
4409 JNC AHEAD D2 Jump on no carry to label AHEAD
440A 0D
440B 44
440C MOV A,M 7E Copy the memory content to the
accumulator
440D AHEAD DCR B 05 Decrement register B by 1
440E JNZ LOOP C2
440F 07 Jump on non-zero to label LOOP
4410 44
4411 STA 4300 32
4412 00 Store accumulator content to 4300
4413 43
4414 HLT 76 Program ends

(ii) illustrate the timing diagram of opcode fetch machine cycle.

Opcode fetch machine cycle
The opcode fetch machine cycle (OFMC) involves the fetching of the opcode of the instruction to be
executed and the decoding process of that opcode. Usually, it consists of four T states.
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

1st T state
 During the first T state, the address of the location where the opcode is stored is loaded on the ad -
dress bus. In 8085, this address is stored in a 16-bit register called the program counter. Higher
eight bits of the address are loaded on A8-A15, and the lower eight bits of the address are loaded
into AD0-AD7 for demultiplexing.
 Also, the ALE signal becomes active in the first T state to indicate that the data on AD0-AD7 pins
are the lower address bits.
 IO/M signal becomes low at the beginning of the first T state to indicate that the opcode will be
fetched from memory (reading from memory).
 At the beginning of the first T state, signals S1 and S0 take the value 1 and 1 respectively to indicate
that it is an opcode fetch machine cycle.
2nd T state
 By the beginning of the 2nd T state or the end of 1st T state, the ALE signal goes low. By this time,
8085 expects that the lower address bits are latched, and AD0-AD7 is free to be used as a data bus.
 At the beginning of the second T state, RD goes low, indicating that the read process has started.
Meanwhile, higher address bits are present in A8-A15, and lower address bits are expected to be
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

latched.
 As RD goes low, the opcode (eight bits) is loaded into the data bus AD0-AD7.
3rd T state
 The opcode loaded on the data bus is present there until the middle of the third T state.
 During the third T state, RD goes up, indicating that the read operation is completed and ‘the op-
code is fetched’ and placed in the instruction register.
 The data on the data bus and the higher address bits on A8-A15 exist until the middle of this T state.
4th T state
 During the fourth T state, the fetched opcode is decoded. There is nothing much to observe in the
timing diagram during this process.
 In case of some simple one-byte instructions like STC (set carry flag), execution is also completed
during the fourth T state. One such instruction is MOV A, D.
 During the fourth T state, after decoding the opcode, the microprocessor decides if it needs fifth and
sixth T states, or should proceed to the next machine cycle.
 PC is incremented by 1 here or in the sixth T state if the OFMC is extended upto sixth T state.
5th and 6th T state
 In case of one-byte instructions that operate on 16-bit data and some other instructions, OFMC may
extend up to six T states. During the fifth and sixth T states, execution of these instructions takes
place. Since these instructions are simple, they get executed in the OFMC itself. Examples of such
instructions are DCX, INX, PCHL, SPHL, CALL, RSTN and conditional RET.
5. Write an 8085 assembly language program to divide an 8bit number by another 8bit
number and store the quotient and reminder in the memory locations 4253 and 4252
respectively. (Nov2015)
LXI H, 4250 : Load the register HL pair with address 5000H
MOV B, M ;Get the dividend in B - reg.
MVI C, 00 ;Clear C - reg for quotient
INX H ;Increment HL pair of registers
MOV A, M ;Get the divisor in A - reg
NEXT: CMP B ;Compare A - reg with register B.
JC LOOP ;Jump on carry to LOOP
SUB B ;Subtract A - reg from B - reg.
INR C ;Increment content of register C.
JMP NEXT ;Jump to NEXT
LOOP: STA 4253 ;Store the remainder in Memory
MOV A, C ;Move Content of C - Reg to A - Reg
STA 4252 ;Store the quotient in memory
HLT ;Terminate the program.
Input:
Data 1: FFH in memory location 4250
Data 2: FFH in memory location 4251
Output:
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

Data 1: 01H in memory location 4252 as Remainder

Data 2: FEH in memory location 4253 as Quotient

6. Write an ALP to convert Hexa to ASCII and sort numbers in ascending order.
(Nov2016/May2016/Dec2018)
PROGRAMM FOR HEXA TO ASCII CONVERSION:

ADDRESS HEX CODE LABEL MNEMONICS OPERAND

4100 21,00,45 LXI H,4500

4103 7E MOV A,M

4104 E6,0F ANI 0FH

4106 CD,00,42 CALL SR

4109 3A,00,45 LDA 4500

410C E6,F0 ANI F0H

410E 07 RLC

410F 07 RLC

4110 07 RLC

4111 07 RLC

4112 CD,00,42 CALL SR

4115 76 HLT

“SUB ROUTINE”

4200 FE,0A CPI OAH

4202 DA,07,42 JC L1

4205 C6,07 ADI 07

4207 C6,30 L1 ADI 30

4209 23 INX H
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

420A 77 MOV M,A

420B C9 RET

PROGRAMM FOR SORTING OF NUMBERS IN ASCENDING ORDER

ADDRESS HEX CODE LABEL MNEMONICS OPERAND

4100 3A,00,45 LDA 4500

4103 47 MOV B,A

4106 48 L3 MOV C,B

4107 21,01,45 LXI 4501H

4108 7E L2 MOV A,M

4109 23 INX H

410A BE CMP M

410B DA,13,41 JC L1

410C 56 MOV D,M

410D 77 MOV M,A

4110 2B DCX H

4111 72 MOV M,D

4112 23 INX H

4113 0D L1 DCR C

4114 C2,08,41 JNZ L2

4117 05 DCR B

4118 C2,04,41 JNZ L3

 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

411B 7E MOV A,M

411C E6 ANI OF

411D 30,00,43 STA 4300

4120 76 HLT

7. i) Write an ALP to multiply two 8 bit numbers and store in respective locations.
(Nov2016)

8 BIT MULTIPLICATION: DIRECT ADDRESSING

ADDRESS HEX CODE LABEL MNEMONICS OPERAND

4100 0E,00 MVI C,00

4102 3A,00,45 LDA 4500H

4105 47 MOV B,A

4106 3A,01,45 LDA 4501H

4109 57 MOV D,A

410A AF XRA A

410B 82 L2 ADD D

410C D2,10,41 JNC L1

410F 0C INR C

4110 05 L1 DCR B

4111 C2,0B,41 JNZ L2

4114 32,02,45 STA 4502H

4117 79 MOV A,C

 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

4118 32,03,45 STA 4503H

411B 76 HLT

ii) Write an ALP with its output to add two 16 bit numbers using 8085.
PROGRAM TABLE FOR 16 BIT ADDITIONS (DIRECT ADDRESSING)

HEX CODE LABEL MNEMONICS OPERAND

0E,00 MVI C,00

2A,00,45 LHLD 4500

EB XCHG

2A,02,45 LHLD 4502

7D MOV A,L

83 ADD E

6F MOV L,A

7C MOV A,H

82 ADC D

67 MOV H,A

D2,13,41 JNC L1

0C INR C

22,04,45 L1 SHLD 4504

79 MOV A,C

32,06,45 STA 4506

76 HLT

(Nov2021)
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

8. Define addressing mode. Identify the addressing mode of the following instructions
and explain them. (Dec2018)
(i) STA 6350 (ii) CMA (iii) MOV A, M (iv) MOV D, E (v) MVI A, A7H
Addressing Modes in 8085:
The method by which the address of source of data or the address of destination of result is given in the
instruction is called Addressing Modes
(i) STA 6350 - Direct Addressing
In direct addressing mode, the address of the data is specified in the instruction. The data will be in
memory. In this addressing mode, the program instructions and data can be stored in
different memory blocks. This type of addressing can be identified by 16- bit address present in
theinstruction.
STA 6350H- Store the data available in the accumulator into memory location 6350H.
(ii) CMA - Implied Addressing
In implied addressing mode, the instruction itself specifies the type of operation and location of
data to be operated. This type of instruction does not have any address, register name, immediate
data specified along with it. CMA - Complement the content of accumulator.
(iii) MOV A, M - Register Indirect Addressing
In register indirect addressing mode, the instruction specifies the name of the register in which the
address of the data is available. Here the data will be in memory and the address will be in the
register pair. This type of addressing can be identified by letter ‘M’ present in the instruction.
MOV A, M - The memory data addressed by HL pair is moved to A register.
(iv) MOV D,E - Register Addressing
In register addressing mode, the instruction specifies the name of the register in which the data is
available. This type of addressing can be identified by register names (such as ‘A’, ‘B’....) in the
instruction. MOV D, E -Move the content of E register to D register.
v) MVI A, A7H - Immediate Addressing
In immediate addressing mode, the data is specified in the instruction itself. The data will be apart
of the program instruction. All instructions that have ‘I’ in their mnemonics are of Immediate
addressing type. MVI A, A7H- Move the data A7H given in the instruction to accumulator.
9. Differentiate between the following instructions clearly.
(i) PUSH and POP
(ii) CALL and JUMP
(iii) ADD and ADC
(iv) INC and INX
(v) MOV B, B and MOV B, A
(vi) What is the general format of an 8085 Instruction set? (May2019)

(i) PUSH and POP:

There are two basic operations that can be performed on a stack to modify its contents, which are
called PUSH and POP. The main difference between PUSH and POP is what they do with the stack. PUSH
is used when you want to add more entries to a stack while POP is used to remove entries from it.
(ii) CALL and JUMP:
The differences Between CALL and JUMP instructions are:
SERIAL
NO. JUMP CALL

1. Program control is transferred to a Program Control is transferred to a memory

 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

memory location which is in the main location which is not a part of main
program program

Immediate Addressing Mode + Register

2. Immediate Addressing Mode Indirect Addressing Mode

Initialisation of SP(Stack Pointer) is not Initialisation of SP(Stack Pointer) is

3. mandatory mandatory

Value of Program Counter(PC) is not Value of Program Counter(PC) is

4. transferred to stack transferred to stack

After JUMP, there is no return

5. instruction After CALL, there is a return instruction

6. Value of SP does not changes Value of SP is decremented by 2

10 T states are required to execute this 18 T states are required to execute this
7. instruction instruction

3 Machine cycles are required to execute 5 Machine cycles are required to execute
8. this instruction this instruction

(iii) ADD and ADC:

ADC is the same as ADD but adds an extra 1 if processor's carry flag is set. Ah, so first, the lower 16-bit is
added by add ax, cx. Then the higher 16-bit is added using adc instead of add. It is because: if there are
overflows, the carry bit is automatically added in the higher 16-bit.
(iv) INC and INX:
INC is used to increment the content of register by 1 for example, INC B will increment the content of
register B by 1 whereas INX( increment with extended register) is used to increment the content of register
pair by 1 for example, INX H will increment the content of register pair which is 16 bit by 1.
(v) MOV B,B and MOV B,A:
MOV B,B is not allowed as it moves the content of same register and MOV B,A moves the content
of register A which is the accumulator to the register B but still the copy of same remains in A.
(vi) General format of an 8085 Instruction set:
Each Instruction Format of 8085 and Data Format of 8085 microprocessor has specific information fields.
These information fields of instructions are called elements of instruction. These are :
Operation code : The operation code field in the instruction specifies the operation to be performed. The
operation is specified by binary code, hence the name operation code or simply opcode. For example, for
8085 processor operation code for ADD B instruction is 80H.
Source / destination operand : The source/destination operand field directly specifies the
source/destination operand for the instruction. In the Instruction Format of 8085, the instruction MOV A,B
has B register contents as a source operand and A register contents as a destination operand because this
instruction copies the contents of register B to register A.
Source operand address : We know that the operation specified by the instruction may require one or more
operands. The source operand may be in the 8085 register or in the memory. Many times the Instruction
Format of 8085 specifies the address of the source operand so that operand(s) can be accessed and operated
by the 8085 according to the instruction.
Destination operand address : The operation executed by the 8085 may produce result. Most of the times
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

the result is stored in one of the operand. Such operand is known as destination operand. The Instruction and
Data Format of 8085 which produce result specifies the destination operand address. In 8085, the destination
operand address for instruction INR M is given by HL register pair because INR M instruction increments
the contents of memory location specified by HL register pair and stores the result in the same memory
location.
Next instruction address : The next instruction address tells the 8085 from where to fetch the next
instruction after completion of execution of current instruction. For BRANCH instructions the address of the
next instruction is specified within the instruction. However, for other instructions, the next instruction to be
fetched immediately follows the current instruction. For example, in 8085, instruction after INR B follows
it. The instruction JMP 2000H specifies the next instruction address as 2000H.
10. i) Write an ALP with its output to add two 16 bit numbers using 8085. (8)
PROGRAM TABLE FOR 16 BIT ADDITIONS (DIRECT ADDRESSING)

HEX CODE LABEL MNEMONICS OPERAND

0E,00 MVI C,00

2A,00,45 LHLD 4500

EB XCHG

2A,02,45 LHLD 4502

7D MOV A,L

83 ADD E

6F MOV L,A

7C MOV A,H

82 ADC D

67 MOV H,A

D2,13,41 JNC L1

0C INR C

22,04,45 L1 SHLD 4504

79 MOV A,C

32,06,45 STA 4506

 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

76 HLT

ii) Explain the operation of instructions related to rotation of accumulator bits with
example. (5) (Nov2021)
i) ROTATE is a logical operation of 8085 microprocessor. It is a 1 byte instruction. This instruc-
tion does not require any operand after the opcode. It operates the content of accumulator and the
result is also stored in the accumulator. The Rotate instruction is used to rotating the bits of accu-
mulator.
Types of ROTATE Instruction:
There are 4 categories of the ROTATE instruction: Rotate accumulator left (RLC), Rotate accumu-
lator left through carry (RAL), Rotate accumulator right (RRC), Rotate accumulator right through
carry (RAR). Among these four instructions; two are for rotating left and two are for rotating right.
All of them are explain briefly in the following sections:
1. Rotate accumulator left (RLC) –
In this instruction, each bit is shifted to the adjacent left position. Bit D7 becomes D0. Carry
flag CY is modified according to the bit D7. For example:-
A = D7 D6 D5 D4 D3 D2 D2 D0
//before the instruction
A = 10101010; CY=0
//after 1st RLC
A = 01010101; CY=1
//after 2nd RLC
A = 10101010; CY=0
2. Rotate accumulator left through carry (RAL) –
In this instruction, each bit is shifted to the adjacent left position. Bit D7 becomes the carry bit
and the carry bit is shifted into D0. Carry flag CY is modified according to the bit D7. For ex-
ample:
A = D7 D6 D5 D4 D3 D2 D2 D0
//before the instruction
A = 10101010; CY=0
//after 1st RAL
A = 01010100; CY=1
//after 2nd RAL
A = 10101001; CY=0
3. Rotate accumulator right (RRC) –
In this instruction, each bit is shifted to the adjacent right position. Bit D7 becomes D0. Carry
flag CY is modified according to the bit D0. For example:
A = D7 D6 D5 D4 D3 D2 D2 D0
//before the instruction
A = 10000001; CY=0
//after 1st RRC
A = 11000000; CY=1
//after 2nd RRC
A = 01100000; CY=0
4. Rotate accumulator right through carry (RAR) –
In this instruction, each bit is shifted to the adjacent right position. Bit D0 becomes the carry
bit and the carry bit is shifted into D7. Carry flag CY is modified according to the bit D0. For
example:
A = D7 D6 D5 D4 D3 D2 D2 D0
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

//before the instruction

A = 10000001; CY=0
//after 1st RAR
A = 01000000; CY=1
//after 2nd RAR
A = 10100000; CY=0

11. i) Differentiate RAL and RLC instruction.

i) In 8085 Instruction set, there is one mnemonic RLC stands for “Rotate Left Accumulator”. It
rotates the Accumulator contents to the left by 1-bit position. The following Fig. shows the
operation explicitly.

In this fig. it has been depicted that the most significant bit of the Accumulator will come out and left
rotate will create an empty space at the least significant bit place and this come out bit will be copied
at the empty bit place and also on the Cy bit in the flag register. Thus, Cy flag gets a copy of the bit
moved out from the MS bit position. Notice that Cy flag is not involved in the rotation, and it is only
8-bit rotation of Accumulator contents. Only Cy flag is affected by this instruction execution.
Mnemonics, Operand Opcode(in HEX) Byt
es

RLC 07 1
This instruction can be used in following different case studies.
To check whether the number is positive or negative. As the most significant of the Accumulator
content holds the sign bit.
To perform multiplication by 2, rotate the Accumulator to left. It works correctly for unsigned
numbers, as long as the MS bit of Accumulator is a 0 before rotation. As we know that multiplication
by 2n results n-bit left shift of the number.
Let us discuss some examples on this mnemonic usage.
Example 1
35H ---> 0011 0101
0 0110 1010 ---> 6AH
Before After

(A) 35H 6AH

(Cy) Any value 0

Address Hex Codes Mnemonic Comment

2002 07 RLC Rotate Left

Accumulator
Here the accumulation content has been doubled as we had 1-bit left shift and the MSB was 0.
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

In 8085 Instruction set, there is another mnemonic RAL,which stands or Rotate Accumulator Left and
also involving Cy flag in rotation. It rotates the Accumulator contents to the left by 1-bit position. The
following Fig. is depicting the execution logic of the instruction.

From the Figure we can see that the due to left rotation the bit which is coming out from the most
significant place will be copied to the Cy flag bit. And the previous Cy bit will be moved to least
significant bit place of the Accumulator. Thus it is a 9-bit rotation of Accumulator and Cy contents.
Only Cy flag is affected by this instruction execution.
Mnemonics, Operand Opcode(in HEX) Bytes

RAL 17 1
The instruction can be used for multiple purposes.
To find the most significant bit of the Accumulator, performing rotate left.
To perform multiplication by 2. We know that if we multiply a number by 2n then the number will
have n-bit left rotation.
As during rotation, an empty space will get created. So to put a new bit at that least significant space
we can use this mnemonic as well.
Let us consider the following examples for the better understanding.
Example 1
35H ---> 0011 0101
0 0110 1010 ---> 6AH (Prev. Cy bit as the Last bit)

Before After

(A) 35H 6AH

(Cy) 0 0

Address Hex Codes Mnemonic Comment

2003 17 RAL RotateAccumulator

Left
Note that Accumulator value has been doubled compared with the previous value.
Example 2
35H ---> 0011 0101
0 0110 1011 ---> 6BH(Prev. Cy bit as the Last bit)

Before After

(A) 35H 6BH

(Cy) 1 0
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

Address Hex Codes Mnemonic Comment

2003 17 RAL RotateAccumulator

Left
Here the current Accumulator content is not doubled compared to the initial content of the
Accumulator. As in this case because most significant bit of Accumulator was a 1 before rotation.

ii) Write an assembly language program for 8085 microprocessor to count even
numbers in series of 10 numbers.
Example:
INPUT
02 03 08 01 07
2050 2051 2052 2053 2054
04 0A 09 05 06
2055 2056 2057 2058 2059
OUTPUT:
05
3050
(Nov2019)
i) Algorithm –
Initialize register H with 20 and register L with 4F so that indirect memory points to memory location
204F.
Initialize register C with 00 and register D with 0A.
Increment indirect memory by 1.
Store value of M in accumulator A.
Check whether the content in A is even or odd by performing AND operation of A with 01.
If content of A is 00 after AND operation then number scanned was even, If so then increment C by
01 else if content of A is 01 after AND operation then number scanned was odd, If so then decrements
D by 01.
Check if zero flag is not set i.e. ZF = 0 then jump to step 3 otherwise store value of C at memory
location 3050.
Program –
MEMORY
ADDRESS MNEMONICS COMMENT

H <- 20, L
2000 LXI H 204F <- 4F

2003 MVI C, 00 C <- 00

2005 MVI D, 0A D <- 0A

M <- M +
2007 INX H 01

2008 MOV A, M A <- M

A <- A
2009 ANI 01 (AND) 01
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

Jump if ZF
200B JNZ 200F =0

200E INR C C <- C + 01

200F DCR D D <- D – 01

Jump if ZF
2010 JNZ 2007 =0

2013 MOV A, C A <- C

M[3050] <-
2014 STA 3050 A

2017 HLT END

Explanation – Registers A, B, C, D, H, L are used for general purpose.
LXI H 204F: assign 20 to H and 4F to L.
MVI C, 00: assign 00 to C.
MVI D, 0A: assign 0A to D.
INX H: increment indirect memory location M by 01.
MOV A, M: move content of M to A.
ANI 01: perform AND operation of A with 01 and store the result in A.
JNZ 200F: jump if ZF = 0 to memory location 200F.
INR C: increment C by 01.
DCR D: decrements D by 01.
JNZ 2007: jump if ZF = 0 to memory location 2007.
MOV A, C: moves the content of C to A.
STA 3050: store the content of A to memory location 3050.
HLT: stops executing the program and halts any further execution

12) i) Write an assembly language program to swap two 8-bit numbers using di-
rect addressing mode where the first 8-bit number is stored at 3000H and the sec-
ond 8-bit number is stored at 3001H memory address.
(7)
Example:

Load a 8-bit number from memory 3000 into accumulator

Move value of accumulator into register H
Load a 8-bit number from memory 3001 into accumulator
Move value of accumulator into register D
Exchange both the register pairs
Stop
Program –
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

Memory Mnemonics Operands Comment

2000 LDA [3000] [A] <- [3000]

2003 MOV H, A [H] <- [A]

2004 LDA [3001] [A] <- [3001]

2007 MOV D, A [D] <- [A]

2008 XCHG [H-L] [D-E]

2009 HLT Stop

Explanation – Registers A, H, D are used for general purpose.

LDA is used to load accumulator direct using 16-bit address (3 Byte instruction)
MOV is used to transfer the data (1 Byte instruction)
XCHG is used to exchange the data of both the register pair (H-L), (D-E) (1 Byte instruction)
HLT is used to halt the program.
ii) Explain the operation of instructions related to rotation of accumulator bits with
example. Also state any two applications of rotate instruction. (Nov2020)
ROTATE is a logical operation of 8085 microprocessor. It is a 1 byte instruction. This instruction
does not require any operand after the opcode. It operates the content of accumulator and the result
is also stored in the accumulator. The Rotate instruction is used to rotating the bits of accumulator.
Types of ROTATE Instruction:
There are 4 categories of the ROTATE instruction: Rotate accumulator left (RLC), Rotate accumu-
lator left through carry (RAL), Rotate accumulator right (RRC), Rotate accumulator right through
carry (RAR). Among these four instructions; two are for rotating left and two are for rotating right.
All of them are explain briefly in the following sections:
1. Rotate accumulator left (RLC) –
In this instruction, each bit is shifted to the adjacent left position. Bit D7 becomes D0. Carry
flag CY is modified according to the bit D7. For example:-
A = D7 D6 D5 D4 D3 D2 D2 D0
//before the instruction
A = 10101010; CY=0
//after 1st RLC
A = 01010101; CY=1
//after 2nd RLC
A = 10101010; CY=0
2. Rotate accumulator left through carry (RAL) –
In this instruction, each bit is shifted to the adjacent left position. Bit D7 becomes the carry bit
and the carry bit is shifted into D0. Carry flag CY is modified according to the bit D7. For ex-
ample:
A = D7 D6 D5 D4 D3 D2 D2 D0
//before the instruction
A = 10101010; CY=0
//after 1st RAL
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

A = 01010100; CY=1
//after 2nd RAL
A = 10101001; CY=0
3. Rotate accumulator right (RRC) –
In this instruction, each bit is shifted to the adjacent right position. Bit D7 becomes D0. Carry
flag CY is modified according to the bit D0. For example:
A = D7 D6 D5 D4 D3 D2 D2 D0
//before the instruction
A = 10000001; CY=0
//after 1st RRC
A = 11000000; CY=1
//after 2nd RRC
A = 01100000; CY=0
4. Rotate accumulator right through carry (RAR) –
In this instruction, each bit is shifted to the adjacent right position. Bit D0 becomes the carry bit
and the carry bit is shifted into D7. Carry flag CY is modified according to the bit D0. For ex-
ample:
A = D7 D6 D5 D4 D3 D2 D2 D0
//before the instruction
A = 10000001; CY=0
//after 1st RAR
A = 01000000; CY=1
//after 2nd RAR
A = 10100000; CY=0
Applications of ROTATE Instructions:
The ROTATE instructions are primarily used in arithmetic multiply and divide operations and for
serial data transfer. For example:
If A is 0000 1000 = 08H
1. By rotating 08H right : A = 0000 0100 = 04H
This is equivalent to dividing by 2.
2. By rotating 08H left : A = 0001 0000 = 10H
This is equivalent to multiplying by 2.
However, these procedures are invalid when logic 1 is rotated left from D7 to D0 or vice versa. For
example, if 80H is rotated left it becomes 01H.

13. Explain in detail about the 8085 Processor Data transfer Instruction set with examples
and mention the addressing mode and instruction format of each instruction.
(Nov2021)
Opcode Operand Explanation Description Addressin Instructi
of Instruction g mode on format

MOV Rd, Rs Copy from This instruction copies the Register/ One byte
M, Rs source(Rs) to contents of the source register Indirect
Rd, M destination(Rd) into the destination register; the
contents of the source register
are not altered. If one of the
operands is a memory location,
its location is specified by the
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

contents of the HL registers.

Example: MOV B, C or MOV
B, M

MVI Rd, data Move The 8-bit data is stored in the Immediate Two byte
M, data immediate 8- destination register or memory. / Indirect
bit If the operand is a memory
location, its location is specified
by the contents of the HL
registers.
Example: MVI B, 57H or MVI
M, 57H

LDA 16-bit Load The contents of a memory Direct Three byte

address accumulator location, specified by a 16-bit
address in the operand, are
copied to the accumulator. The
contents of the source are not
altered.
Example: LDA 2034H

LDAX B/D Reg. Load The contents of the designated Register One byte
pair accumulator register pair point to a memory Indirect
indirect location. This instruction copies
the contents of that memory
location into the accumulator.
The contents of either the
register pair or the memory
location are not altered.
Example: LDAX B

LXI Reg. Load register The instruction loads 16-bit data Immediate Three byte
pair, 16- pair immediate in the register pair designated in
bit data the operand.
Example: LXI H, 2034H or LXI
H, XYZ

LHLD 16-bit Load H and L The instruction copies the Direct Three byte
address registers direct contents of the memory location
pointed out by the 16-bit
address into register L and
copies the contents of the next
memory location into register H.
The contents of source memory
locations are not altered.
Example: LHLD 2040H

STA 16-bit 16-bit address The contents of the accumulator Direct Three byte
address are copied into the memory
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

location specified by the

operand. This is a 3-byte
instruction, the second byte
specifies the low-order address
and the third byte specifies the
high-order address.
Example: STA 4350H

STAX Reg. Store The contents of the accumulator Register One byte
pair accumulator are copied into the memory indirect
indirect location specified by the
contents of the operand (register
pair). The contents of the
accumulator are not altered.
Example: STAX B

SHLD 16-bit Store H and L The contents of register L are Direct Three byte
address registers direct stored into the memory location
specified by the 16-bit address
in the operand and the contents
of H register are stored into the
next memory location by
incrementing the operand. The
contents of registers HL are not
altered. This is a 3-byte
instruction, the second byte
specifies the low-order address
and the third byte specifies the
high-order address.
Example: SHLD 2470H

XCHG none Exchange H The contents of register H are Implied One byte
and L with D exchanged with the contents of
and E register D, and the contents of
register L are exchanged with
the contents of register E.
Example: XCHG

SPHL none Copy H and L The instruction loads the Implied One byte
registers to the contents of the H and L registers
stack pointer into
the stack pointer register, the
contents of the H register
provide the high-order address
and the contents of the L
register provide the low-order
address. The contents of the H
and L registers are not altered.
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

Example: SPHL

XTHL none Exchange H The contents of the L register Implied One byte
and L with top are exchanged with the stack
of stack location pointed out by the
contents of the stack pointer
register. The contents of the H
register are exchanged with the
next stack location (SP+1);
however, the contents of the
stack pointer register are not
altered.
Example: XTHL

PUSH Reg. Push register The contents of the register pair Register One byte
pair pair onto stack designated in the operand are indirect
copied onto the stack in the
following sequence. The stack
pointer register is decremented
and the contents of the
highorder register (B, D, H, A)
are copied into that location.
The stack pointer register is
decremented again and the
contents of the low-order
register (C, E, L, flags) are
copied to that location.
Example: PUSH B or PUSH A

POP Reg. Pop off stack The contents of the memory Register One byte
pair to register pair location pointed out by the stack indirect
pointer register are copied to the
low-order register (C, E, L,
status flags) of the operand. The
stack pointer is incremented by
1 and the contents of that
memory location are copied to
the high-order register (B, D, H,
A) of the operand. The stack
pointer register is again
incremented by 1.
Example: POP H or POP A

OUT 8-bit Output data The contents of the Direct Two byte
port from accumulator are copied into the
address accumulator to I/O port specified by the
a port with 8- operand.
bit address Example: OUT F8H
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

IN 8-bit Input data to The contents of the input port Direct Two byte
port accumulator designated in the operand are
address from a port read and loaded into the
with 8-bit accumulator.
address Example: IN 8CH

PART –C

1. Write an ALP using 8085 instructions to find the average of 10 numbers and find
the execution time of program. (Apr2018)
ALGORITHM:
STEP 1: Load HL register pair with a memory pointer.
STEP 2: Get the count to B register and clear accumulator.
STEP 3: Push the count to stack pointer.
STEP 4: Increment memory pointer.
STEP 5: Add the content of memory location to accumulator.
STEP 6: If carry results increment D register.
STEP 7: Decrement count. If it is not zero go to STEP 4.
STEP 8: Else move the sum to E register.
STEP 9: Get the count from stack pointer.
STEP10: Subtract the count from sum(content of DE pair).
STEP11:If the subtraction results a carry add the count to the result and get the remainder
STEP12: Otherwise increment B register content and go to STEP10.
STEP 13: Store the quotient and remainder in successive memory location.
PROGRAM:
MEMORY MACHINE LABEL MNEMONICS COMMENTS
LOATION CODE
4100 21,00,42 LXI H, 4200 Initialize HL register
pair with memory
pointer
4103 46 MOV B,M Transfer the memory
content to B register
4104 C5 PUSH B Push the content of B
register to stack pointer
4105 AF XRA A Clear accumulator
4106 57 MOV D,A Clear D register
4107 5F MOV E,A Clear E register
4108 23 LOOP1 INX H Increment memory
pointer
4109 86 ADD M Add the content of
memory location to
accumulator
410A D2,0E,41 JNC LOOP2 Jump on no carry to
LOOP2
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

410D 14 INR D Increment D register

content
410E 05 LOOP2 DCR B Decrement B register
content
410F C2,08,41 JNZ LOOP1 Jump on zero to
LOOP1
4112 5F MOV E,A Move the content of
accumulator to E
register
4113 C1 POP B Retrieve the content of
B register from stack
4114 26,00 MVI H,00 Clear H register
4116 68 MOV L,B Move the [B] to L
register
4118 7B LOOP4 MOV A, E Mover the[E] content
to accumulator
4119 95 SUB L Subtract [L] content
from accumulator
411A 5F MOV E,A Move the accumulator
content to E register
411B 7A MOV A, D Move the[D] to
accumulator
411C 9C SBB H Subtract [H] from
accumulator through
borrow
411D DA,25,41 JC LOOP3 Jump on carry to
LOOP3
4120 57 MOV D,A Move accumulator
content to D register
4121 04 INR B Increment B register
4122 C3,18,41 JMP LOOP 4 Jump to LOOP4
4125 7B LOOP3 MOV A,E Move[E] to
accumulator
4126 85 ADD L Add [L] with
accumulator content
4217 5F MOV E,A Move accumulator
content to E register
4128 78 MOV A,B Move [B] register to
accumulator
4129 32,00,43 STA 4300 Store the accumulator
content in 4300
412C EB XCHG Exchange [DE]
With [HL]
412D 22,01,43 SHLD 4301 Store the remainder in
4301 and 4302
4130 76 HLT Ends execution
 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

Calculate Execution time by finding T states of each instruction.

2. Write an assembly language program to calculate the sum of series of even

numbers from the given list of numbers. The length of the list is in memory lo-
cation 2200H and the series begins from memory location 2201H. Result will
store at memory location 2210H.
Sample Input: Sample Output:
2200H = 4H Result 2210H = 46H
2201H = 20H
2202H = 15H
2203H = 13H
2204H = 22H (Nov2020)
MNEMONICS OPERANDS COMMENTS

LDA 2200H [A] <- 2200H

MOV C, A Initialize counter

MVI B, 00H sum = 0

LXI H, 2201H Initialize pointer

BACK: MOV A, M Get the number

ANI 0lH Mask Bit l to Bit7

JNZ SKIP Don’t add if number is ODD

MOV A, B Get the sum

ADD M SUM = SUM + data

MOV B, A Store result in B register

SKIP: INX H increment pointer

DCR C Decrement counter

JNZ BACK if counter 0 repeat

 UNIT – II: PROGRAMMING OF 8085 PROCESSOR
PART - B

MNEMONICS OPERANDS COMMENTS

MOV A, B Store result in A register

STA 2210H store sum

HLT Terminate program execution

Explanation –
A microprocessor is a computer processor that incorporates the functions of a central process-
ing unit on a single integrated circuit.
1. A is an 8-bit accumulator which is used to load and store the data directly.
2. LDA is used to load accumulator direct using 16-bit address (3 Byte instruction).
3. Instructions like MOV, MVI, LDA are the data transfer instructions.
4. ADD is used to add data.
3. HLT is used to halt the program.