PIC18F Family

Lecturer 5
 Overview of PIC18 Family

Microchip Technology Inc. (1989)
 Introduced microcontrollers called PIC

Peripheral Interface Controller(PIC)
 8-bit MCUs

PIC10, PIC12, PIC16, PIC18
 16-bit MCUs

PIC24
 32-bit MCUs

PIC32
 www.Microchip.com
 Programming a PIC

ifile:///home/guta/Pictures/Screenshots/
Screenshot%20from%202024-04-19%2018-14-
56.png
Software Program Flow
 PIC18 family

PIC18 one of the higher performers of the Microchip’s PIC families.
There is now both a 32 bit PIC32 family and DSPIC (16 bit) with high
performance.

PIC families come in 18 to 80 pin packages.

Select family based on performance, footprint, etc., needed, use
selection guide.
Architecture of PIC family of devices
Architecture of PIC family of devices
 What is a Register?

Register
 A place inside the PIC that can be written to, read from, or both (8-
bit numbers)
 WREG

Working Register is the same as the accumulator in other
microprocessors

Used for all arithmetic/logic instructions
 Avoids use of main memory
 Close as possible to the ALU within the CPU

Can only hold 0-255 dec (0-FFh)
 Truncates larger values and causes warning
 1001 1101 1100 = 2,524dec = 9DCh
 0000 1101 1100 = 220dec = DCh
 Assembly Language Programming

WREG
 8 bit register in PIC (Working Register)
 used for most instructions
MOVLW K

Move (“MOV”) the number (“L” for “literal”) K into the working
register (“W”)
 MOVLW 0xA

That is, load W with the value 0xA

Note: ‘WREG’ sometimes shortened to ‘W’
 Moving to WREG

MOVLW K; move literal value K into WREG

Once again K is an 8 value 0-255 decimal or 00-FF in hex

Ex.

MOVLW 25H; move 25H (0x25) into WREG (WREG = 25H)
 Move and Add Instructions

MOVLW 12H ;load value 12H -> WREG


ADDLW 16H ;add 16H to WREG


ADDLW 11H ;add 11H to WREG


ADDLW 43H ;add 43H to WREG
 FILE REGISTER

File Register = Data Memory (RAM)
 Read/write memory used by CPU for data storage
 Varies from 32 bytes to thousands depending on chip size (family)
 Can perform arithmetic/logic operations on many locations of File
Register data

Divided into two sections:
 Special Function Registers (SFR)
 General Purpose Registers (GPR) or (GP RAM)
 FILE REGISTER

SFR – special functions (8-bit wide regs)
 Functionality of each is fixed in design
 Usually for all of the peripherals

ALU status

Timers
 Ex: the more timers the more SFR in a PIC


Serial communications

I/O Ports

A/D
 FILE REGISTER

GPR – general-purpose (8-bit wide regs)
 RAM locations used for ANY data storage and scratch pad as long
as it’s 8 bits (data RAM size same as GFR size)
 Larger GPR = more difficult to manage in ASM
 C compilers now handle management/addressing

GPR ≠ EEPROM
 GPR used by CPU for “internal” data storage
 EEPROM considered “add-on” memory
 FILE REGISTER

PIC File Register has max 4K or 000-FFFH
Addresses (locations) are 12-bit wide

Divided into 16 banks of 256 bytes

All PIC’s have at least one bank…
Access Bank

The access bank divided into 2 sections of 128 bytes, SFR and GPR
 PIC18 File Register and Access Bank

Bank switching required (as only 256 bytes are addressable) in File
Registers if using more than 256 bytes:

MOVWF used to copy from work register into file register:

MOVLW 12H ; 12H -> WREG

MOVWF 16H ; (WREG) -> File Register 16H

MOVWF PORTC ; (WREG) -> PORTC (F8BH)
Moving Data Directly Among the fileReg Locations
 Choosing Location to Store Result

ADDWF fileReg, D ; (D = Destination Bit)

Contents of WREG added to contents of fileReg address location
 If D = 0, result placed in WREG
 If D = 1, result placed in fileReg location
e.g., ADDWF 16H, 0 ; add the value contained in 16H to the value of W
(thus store in W)
e.g., ADDWF PORTC, 1 ; add the value contained in W to the value of
PORTC/F82H (thus store in F82H/PORTC’s IO Pins)
 Add with CARRY or Not

ADDWF fileReg, d ;ADD WREG & fileReg

W+F→ d
 If d = 0, result put in WREG
 If d = 1, result put in F (location)

ADDWFC fileReg, d ;ADD WREG & fileReg & Carry

W+F+C → d
 If d = 0, result put in WREG
 If d = 1, result put in F (location)
STATUS Register in the CPU
Bits of Status Register
 Carry Flag

C Flag is set (1) when there is a “carry out” from the D7 bit

Can be set by an ADD or SUB
 1101 1010
 + 1010 1111
 = 1 1000 1001
 Digital Carry Flag

DC Flag is set (1) when there is a “carry” from the D3 to D4 bits
 Can be set by an ADD or SUB
 1101 1010
 + 1010 1111
 = 1 1000 1001
 Used by instructions that perform BCD arithmetic
 Zero Flag

Z Flag indicates if the the result of an arithmetic or logic operation is
0
 Result = 0; Z = 1
 Result ≠ 0; Z = 0
 Overflow Flag

OV Flag is set (1) when the result of a signed number operation is too
large
 The numerical result overflows/overtakes the sign bit of the
number

Usually used to detect errors in signed operations
 Negative Flag

N Flag is set (1) when the result of an arithmetic
operation is less than zero
 If D7 bit = 0, N = 0, positive result
 If D7 bit = 1, N = 1, negative result
 Flags Affected Following
Execution of Most Instructions

ADDLW can affect C, DC, Z, OV N

ANDLW can affect Z

MOVF can affect Z

Move instructions (except for MOVF) will not affect
any status bits
ADDLW Example
ADDLW Example:Solution
Flag Bits used in Branching
 Reference

The University of Texas at Arlington: Based
heavily on slides by Dr. Gergely Záruba and Dr.
Roger Walker