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B SIDDALING CV

Im B Siddaling trained physical design engineer.. i have attained many interviews they are still excepting technical knowledge so I'm searching for a good notes to prepare.

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siddu chinnu
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29 views3 pages

B SIDDALING CV

Im B Siddaling trained physical design engineer.. i have attained many interviews they are still excepting technical knowledge so I'm searching for a good notes to prepare.

Uploaded by

siddu chinnu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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B SIDDALING .

PHYSICAL DESIGN ENGINEER.


[email protected]

8861589765

linkedin.com/in/ b-siddaling-917817226

male

12th December 2000

Bangaluru, Karnataka, India.

PROFILE

Motivated VLSI fresher in advanced physical design and verification. i am seeking a challenging role in the field of VLSI
where i can apply my technical proficiency and collaborate with the dynamic team. Dedicated to contributing innovation
solutions and continuous learning in a professional environment.

PROFESSIONAL TRAINING
Advanced VLSI Physical Design
Institute : Maven silicon VLSI training center, Bangalore.
•

Course : Advanced physical design and verification.


•

Duration : 29th June 2023 - February 2024.


•

EDUCATION
Bachelor of engineering (ECE)
APS College of Engineering, Bangalore
2018-2023
CGPA: 6.5

pre-university college
Pupil tree PU college, Bellary
2016-2018
CGPA: 6.1

secondary school leaving certificate


Satyam international school Bellary
2015-2016
CGPA: 8.00
VLSI Domain Skills
Digital electronics
•

CMOS VLSI design


•

Linux
•

Physical design
•

Floor planning and placement


•

Clock tree synthesis (CTS)


•

Routing
•

Static timing analysis (STA)


•

TECHNICAL SKILLS
Tools used under VLSI Domain
Synthesis : Design compiler (Synopsys)
•

Simulation : Modelsim, Questasim (Mentor graphic's)


•

S-Edit : Tanner tools suite used for schematic capture (Siemens)


•

L-Edit : Tanner tool supports schematic-driven layout (SDL)


•

STA : Prime time (Synopsys) used for static timing analysis


•

PNR : Fusion compiler (Synopsys)


•

INTERNSHIP

Title : Introduction to VLSI


Platform : Internshala
Duration : 3 months
Location : remote

PROJECTS
VLSI Domain project's
Title : RISC -V IP physical design Implementation using Fusion DC and ICC2.
Description : Design compiler excels in optimizing design to deliver a compact and high speed logical functions
representation.

Academic project
Title : All time medicine (ATM)
Description : All time medicine is a machine which delivers the medicine in emergency cases and ensures availability of
drugs 24*7 and hence the name called "All time medicine".

CERTIFICATE
Advanced Physical design and Verification
•

Introduction to VLSI
•
STRENGTH
Self-Discipline
•

Team work
•

Adaptable
•

Time management
•

Self-motivation
•

LANGUAGES
English
•

Kannada
•

Hindi
•

Telugu
•

HOBBIES

sports
•

Bike rider
•

watching historical movies


•

learning new languages


•

stunts
•

DECLARATION
I hereby declare that the information provided here in is accurate and complete to the best of my knowledge.

Date : Place :

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