Data Sheet LT 1358
Data Sheet LT 1358
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TYPICAL APPLICATIO
DAC I-to-V Converter AV = –1 Large-Signal Response
6pF
12 5k
DAC
INPUTS –
565A-TYPE 1/2
VOUT
LT1358
+
0.1µF 5k
VOUT
VOS + I OS ( 5kΩ )+ < 1LSB
A VOL
135859 TA01
135859 TA02
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LT1358/LT1359
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ABSOLUTE AXI U RATI GS (Note 1)
Total Supply Voltage (V+ to V –) ............................... 36V Specified Temperature Range (Note 8) ....–40°C to 85°C
Differential Input Voltage Maximum Junction Temperature (See Below)
(Transient Only) (Note 2)................................... ±10V Plastic Package ................................................ 150°C
Input Voltage ............................................................ ±VS Storage Temperature Range ..................–65°C to 150°C
Output Short-Circuit Duration (Note 3) ............ Indefinite Lead Temperature (Soldering, 10 sec).................. 300°C
Operating Temperature Range (Note 7) ...–40°C to 85°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW TOP VIEW
OUT A 1 8 V+ OUT A 1 8 V+
N8 PACKAGE S8 PACKAGE
8-LEAD PDIP 8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 130°C/ W TJMAX = 150°C, θJA = 190°C/ W
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LT1358/LT1359
ELECTRICAL CHARACTERISTICS TA = 25°C, VCM = 0V unless otherwise noted.
3
LT1358/LT1359
ELECTRICAL CHARACTERISTICS TA = 25°C, VCM = 0V unless otherwise noted.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the temperature range
0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
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LT1358/LT1359
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the temperature range –
40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted. (Note 8)
Note 1: Absolute Maximum Ratings are those values beyond which the life Note 5: Full power bandwidth is calculated from the slew rate
of a device may be impaired. measurement: FPBW = (SR)/2πVP.
Note 2: Differential inputs of ±10V are appropriate for transient operation Note 6: This parameter is not 100% tested.
only, such as during slewing. Large, sustained differential inputs will cause Note 7. The LT1358C/LT1359C and LT1358I/LT1359I are guaranteed
excessive power dissipation and may damage the part. See Input functional over the operating temperature range of –40°C to 85°C.
Considerations in the Applications Information section of this data sheet Note 8: The LT1358C/LT1359C are guaranteed to meet specified
for more details. performance from 0°C to 70°C. The LT1358C/LT1359C are designed,
Note 3: A heat sink may be required to keep the junction temperature characterized and expected to meet specified performance from – 40°C to
below absolute maximum when the output is shorted indefinitely. 85°C, but are not tested or QA sampled at these temperatures. The
Note 4: Slew rate is measured between ±10V on the output with ±6V input LT1358I/LT1359I are guaranteed to meet specified performance from
for ±15V supplies and ±1V on the output with ±1.75V input for ±5V – 40°C to 85°C.
supplies.
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LT1358/LT1359
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage Input Common Mode Range vs Input Bias Current vs
and Temperature Supply Voltage Input Common Mode Voltage
3.0 V+ 400
TA = 25°C VS = ±15V
–0.5 ∆VOS < 1mV TA = 25°C
300
2.5 –1.0 IB + + I B –
125°C –1.5 2
200
2.0 –2.0
25°C
100
–55°C
1.5 2.0
0
1.5
1.0 1.0
–100
0.5
0.5 V– –200
0 5 10 15 20 0 5 10 15 20 –15 –10 –5 0 5 10 15
SUPPLY VOLTAGE (±V) SUPPLY VOLTAGE (±V) INPUT COMMON MODE VOLTAGE (V)
135859 G01 135859 G02
135859 G03
RS = 100k
100 60
50
0 1 0.1 50
– 50 –25 0 25 50 75 100 125 10 100 1k 10k 100k 10 100 1k 10k
TEMPERATURE (°C) FREQUENCY (Hz) LOAD RESISTANCE (Ω)
135859 G04 135859 G05 135859 G06
–1.5
99
OPEN-LOOP GAIN (dB)
–2 RL = 500Ω –2.0
98 –2.5
–3 25°C
25°C
97
3
96 RL = 500Ω 2.5
85°C
2 2.0
95 –40°C
1.5
94 1 RL = 1k 1.0
93 V– V – +0.5
– 50 –25 0 25 50 75 100 125 0 5 10 15 20 –50 –40 –30 –20 –10 0 10 20 30 40 50
TEMPERATURE (°C) SUPPLY VOLTAGE (±V) OUTPUT CURRENT (mA)
135859 G07 135859 G08 135859 G09
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LT1358/LT1359
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TYPICAL PERFOR A CE CHARACTERISTICS
Output Short-Circuit Current vs Settling Time vs Output Step Settling Time vs Output Step
Temperature (Noninverting) (Inverting)
65 10 10
VS = ±5V VS = ±15V
OUTPUT SHORT-CIRCUIT CURRENT (mA)
8 10mV 8
60 AV = 1 10mV
6 6
55 1mV
1mV 4
45 0 0 VS = ±15V
SINK AV = –1
–2 –2
40 10mV
SOURCE –4 –4
35 1mV
–6 –6
1mV
30 –8 –8
10mV
25 –10 –10
– 50 –25 0 25 50 75 100 125 50 100 150 200 250 50 100 150 200 250
TEMPERATURE (°C) SETTLING TIME (ns) SETTLING TIME (ns)
135859 G10 135859 G11 135859 G12
AV = 100
OUTPUT IMPEDANCE (Ω)
0 C = 50pF 28 40
AV = 1
1 –2 26 38
–4 24 36
PHASE MARGIN
PHASE MARGIN (DEG)
32 44 2 2
VS = ±5V
30 42 1 1
GAIN (dB)
GAIN (dB)
28 40 0 0
26 GAIN BANDWIDTH 38 –1 –1
VS = ±15V ±5V
24 36 –2 –2
±5V ±15V
22 34 –3 –3
GAIN BANDWIDTH ±2.5V
20 VS = ±5V 32 –4 ±2.5V –4
18 30 –5 –5
– 50 –25 0 25 50 75 100 125 100k 1M 10M 100M 100k 1M 10M 100M
TEMPERATURE (°C) FREQUENCY (Hz) FREQUENCY (Hz)
135859 G16 135859 G17 135859 G18
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LT1358/LT1359
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TYPICAL PERFOR A CE CHARACTERISTICS
Power Supply Rejection Ratio Common Mode Rejection Ratio
Gain and Phase vs Frequency vs Frequency vs Frequency
70 120 100 120
+PSRR VS = ±15V
VS = ±15V
PHASE (DEG)
VS = ±15V 80
40 GAIN 60 60
GAIN (dB)
VS = ±5V
30 40 60
VS = ±5V
20 20 40
40
10 0
TA = 25°C 20
20
0 AV = –1
RF = RG = 2k
–10 0 0
10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
135859 G14 135859 G20 135859 G21
Slew Rate vs Supply Voltage Slew Rate vs Temperature Slew Rate vs Input Level
1000 600 1000
TA = 25°C
TA = 25°C VS = ±15V 900 VS = ±15V
AV = –1 500 AV = –1
800 800
RF = RG = 2k AV = –2 RF = RG = 2k
SR+ + SR– SR+ + SR– 700 SR+ + SR –
SR = —————
SLEW RATE (V/µs)
VO = 3VRMS
25 AV = –1
RL = 2k 8
OUTPUT VOLTAGE (VP-P)
OUTPUT VOLTAGE (VP-P)
AV = 1
20 AV = 1
AV = –1 6
0.001 15
4
AV = 1
10
VS = ±15V
RL = 2k 2 VS = ±5V
5 RL = 2k
AV = 1, 1% MAX DISTORTION
AV = –1, 2% MAX DISTORTION 2% MAX DISTORTION
0.0001 0 0
10 100 1k 10k 100k 100k 1M 10M 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
135859 G25 135859 G26 135859 G27
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LT1358/LT1359
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TYPICAL PERFOR A CE CHARACTERISTICS
2nd and 3rd Harmonic Distortion
vs Frequency Crosstalk vs Frequency Capacitive Load Handling
–30 – 40 100
VS = ±15V TA = 25°C TA = 25°C
VO = 2VP-P – 50 VIN = 0dBm VS = ±15V
–40 RL = 2k 3RD HARMONIC
HARMONIC DISTORTION (dB)
RL = 500Ω
AV = 2 – 60 AV = 1
–50
OVERSHOOT (%)
CROSSTALK (dB)
– 70 AV = 1
–60 – 80 50
– 90 AV = –1
–70
2ND HARMONIC –100
–80
–110
–90 –120 0
100k 200k 400k 1M 2M 4M 10M 100k 1M 10M 100M 10p 100p 1000p 0.01µ 0.1µ 1µ
FREQUENCY (Hz) FREQUENCY (Hz) CAPACITIVE LOAD (F)
135859 G28 135859 G29 135859 G30
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LT1358/LT1359
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APPLICATIO S I FOR ATIO
Layout and Passive Components Input Considerations
The LT1358/LT1359 amplifiers are easy to use and toler- Each of the LT1358/LT1359 inputs is the base of an NPN
ant of less than ideal layouts. For maximum performance and a PNP transistor whose base currents are of opposite
(for example, fast 0.01% settling) use a ground plane, polarity and provide first-order bias current cancellation.
short lead lengths, and RF-quality bypass capacitors Because of variation in the matching of NPN and PNP beta,
(0.01µF to 0.1µF). For high drive current applications use the polarity of the input bias current can be positive or
low ESR bypass capacitors (1µF to 10µF tantalum). negative. The offset current does not depend on NPN/PNP
beta matching and is well controlled. The use of balanced
The parallel combination of the feedback resistor and gain
source resistance at each input is recommended for
setting resistor on the inverting input combine with the
applications where DC accuracy must be maximized.
input capacitance to form a pole which can cause peaking
or oscillations. If feedback resistors greater than 5k are The inputs can withstand transient differential input volt-
used, a parallel capacitor of value ages up to 10V without damage and need no clamping or
source resistance for protection. Differential inputs, how-
CF > RG x CIN / RF ever, generate large supply currents (tens of mA) as
required for high slew rates. If the device is used with
should be used to cancel the input pole and optimize sustained differential inputs, the average supply current
dynamic performance. For unity-gain applications where will increase, excessive power dissipation will result and
a large feedback resistor is used, CF should be greater than the part may be damaged. The part should not be used
or equal to CIN. as a comparator, peak detector or other open-loop
application with large, sustained differential inputs.
Capacitive Loading Under normal, closed-loop operation, an increase of power
The LT1358/LT1359 are stable with any capacitive load. dissipation is only noticeable in applications with large
As the capacitive load increases, both the bandwidth and slewing outputs and is proportional to the magnitude of
phase margin decrease so there will be peaking in the the differential input voltage and the percent of the time
frequency domain and in the transient response. Coaxial that the inputs are apart. Measure the average supply
cable can be driven directly, but for best pulse fidelity a current for the application in order to calculate the power
resistor of value equal to the characteristic impedance of dissipation.
the cable (i.e., 75Ω) should be placed in series with the
output. The other end of the cable should be terminated
with the same value resistor to ground.
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LT1358/LT1359
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APPLICATIO S I FOR ATIO
Circuit Operation Power Dissipation
The LT1358/LT1359 circuit topology is a true voltage The LT1358/LT1359 combine high speed and large output
feedback amplifier that has the slewing behavior of a drive in small packages. Because of the wide supply
current feedback amplifier. The operation of the circuit can voltage range, it is possible to exceed the maximum
be understood by referring to the simplified schematic. junction temperature under certain conditions. Maximum
The inputs are buffered by complementary NPN and PNP junction temperature (TJ) is calculated from the ambient
emitter followers which drive a 500Ω resistor. The input temperature (TA) and power dissipation (PD) as follows:
voltage appears across the resistor generating currents
LT1358N8: TJ = TA + (PD x 130°C/W)
which are mirrored into the high impedance node. Comple-
LT1358S8: TJ = TA + (PD x 190°C/W)
mentary followers form an output stage which buffers the
LT1359N: TJ = TA + (PD x 110°C/W)
gain node from the load. The bandwidth is set by the input
LT1359S: TJ = TA + (PD x 150°C/W)
resistor and the capacitance on the high impedance node.
LT1359S14: TJ = TA + (PD x 160°C/W)
The slew rate is determined by the current available to
charge the gain node capacitance. This current is the Worst case power dissipation occurs at the maximum
differential input voltage divided by R1, so the slew rate is supply current and when the output voltage is at 1/2 of
proportional to the input. Highest slew rates are therefore either supply voltage (or the maximum swing if less than
seen in the lowest gain configurations. For example, a 10V 1/2 supply voltage). For each amplifier PDMAX is:
output step in a gain of 10 has only a 1V input step,
whereas the same output step in unity gain has a 10 times PDMAX = (V+ – V–)(ISMAX) + (V+/2)2/RL
greater input step. The curve of Slew Rate vs Input Level
illustrates this relationship. The LT1358/LT1359 are tested Example: LT1358 in S8 at 70°C, VS = ±15V, RL = 500Ω
for slew rate in a gain of –2 so higher slew rates can be
expected in gains of 1 and –1, and lower slew rates in PDMAX = (30V)(2.9mA) + (7.5V)2/500Ω = 200mW
higher gain configurations.
TJMAX = 70°C + (2 x 200mW)(190°C/W) = 146°C
The RC network across the output stage is bootstrapped
when the amplifier is driving a light or moderate load and
has no effect under normal operation. When driving a
capacitive load (or a low value resistive load) the network
is incompletely bootstrapped and adds to the compensa-
tion at the high impedance node. The added capacitance
slows down the amplifier which improves the phase
margin by moving the unity-gain frequency away from the
pole formed by the output impedance and the capacitive
load. The zero created by the RC combination adds phase
to ensure that even for very large load capacitances, the
total phase lag can never exceed 180 degrees (zero phase
margin) and the amplifier remains stable.
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LT1358/LT1359
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SI PLIFIED SCHE ATIC
V+
R1
500Ω +IN RC
–IN OUT
C CC
V– 135859 SS01
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LT1358/LT1359
U
PACKAGE DESCRIPTIO Dimension in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8 7 6 5
0.255 ± 0.015*
(6.477 ± 0.381)
1 2 3 4
0.065
(1.651)
0.009 – 0.015 TYP
(0.229 – 0.381) 0.125
(3.175) 0.020
+0.035 MIN (0.508)
0.325 –0.015
( )
0.100 0.018 ± 0.003 MIN
+0.889
8.255 (2.54) (0.457 ± 0.076)
–0.381 BSC N8 1098
N Package
14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
14 13 12 11 10 9 8
0.255 ± 0.015*
(6.477 ± 0.381)
1 2 3 4 5 6 7
0.020
(0.508)
MIN 0.065
0.009 – 0.015 (1.651)
(0.229 – 0.381) TYP
+0.035
0.325 –0.015 0.005
0.018 ± 0.003
( )
0.125
+0.889 (0.125)
8.255 (3.175) (0.457 ± 0.076)
–0.381 MIN MIN 0.100
(2.54)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. BSC
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) N14 1098
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LT1358/LT1359
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PACKAGE DESCRIPTIO Dimension in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8 7 6 5
1 2 3 4
0.010 – 0.020
× 45° 0.053 – 0.069
(0.254 – 0.508)
(1.346 – 1.752)
0.004 – 0.010
0.008 – 0.010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)
0.016 – 0.050
0.014 – 0.019 0.050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
TYP BSC
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 1298
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
0.010 – 0.020
× 45° 0.053 – 0.069
(0.254 – 0.508)
(1.346 – 1.752)
0.004 – 0.010
0.008 – 0.010
0° – 8° TYP (0.101 – 0.254)
(0.203 – 0.254)
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LT1358/LT1359
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PACKAGE DESCRIPTIO Dimension in inches (millimeters) unless otherwise noted.
S Package
14-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.337 – .344
.045 ±.005 (8.560 – 8.738)
.050 BSC NOTE 3
14 13 12 11 10 9 8
N
N
.245
MIN .160 ±.005
.228 – .244 .150 – .157
(5.791 – 6.197) (3.810 – 3.988)
NOTE 3
1 2 3 N/2 N/2
.030 ±.005
TYP RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7
.010 – .020
× 45° .053 – .069
(0.254 – 0.508)
(1.346 – 1.752)
.008 – .010 .004 – .010
(0.203 – 0.254) 0° – 8° TYP (0.101 – 0.254)
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1358/LT1359
U
TYPICAL APPLICATIO S
Instrumentation Amplifier
R5 R4
432Ω 20k
R1 R2
20k 2k
– R3
1/2 2k
LT1358
–
1/2
– + LT1358
VOUT
VIN +
+
R4 ⎡ 1 ⎛ R2 R3 ⎞ R2 + R3 ⎤
AV = 1+ + + = 1044
R3 ⎢⎣ 2 ⎜⎝ R1 R4 ⎟⎠ R5 ⎥⎦
3.4k 2.61k
100pF
47pF
3.4k 5.62k
VIN –
2.61k 5.11k
1/2
330pF
LT1358
–
1/2
+ 1000pF
LT1358
VOUT
+
135859 TA04
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LT1355/LT1356 Dual and Quad 12MHz, 400V/µs Op Amps Lower Power Version of LT1358/LT1359, VOS = 0.8mV, IS = 1mA/Amplifier
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LT1814
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