Processor Fundamentals

(Chapter 4)
Computer Architecture

Central Processing Unit (CPU):

The central processing unit (CPU) processes instructions and data that are input into the
computer so that the result can be output.
The CPU (also known as microprocessor or processor) is central to all modern computer
systems including tablets & smartphones.
Microprocessor:
A microprocessor is a type of integrated circuit on a single chip.
The CPU (processor) consists of the following components:
Control Unit (CU)
Arithmetic & Logic Unit (ALU)
Registers & Buses

Von Neumann Architecture:

In early years, computers were not able to store programs until 1945; John von Neumann developed
the concept of the stored program computer, referred to as Von Neumann Architecture concept.
He designed architecture for an electronic digital computer with subdivisions of a central arithmetic
part, a central control part, a memory to store both data and instructions, external storage, and input
and output mechanisms.
The von Neumann architecture had the following main features:
The concept of a central processing unit (CPU or processor)
The CPU was able to access the memory directly
The computer memories could store programs as well as data
The stored programs were made up of instructions which could be executed in sequential
order.

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The following diagram is a simple representation of von Neumann CPU architecture:

Components of the Central Processing Unit (CPU):

There are different purposes of components in a CPU, in a computer that has a Von Neumann
architecture. Those components include:

1) Units:
– arithmetic logic unit (ALU)
– control unit (CU) including system clock
2) Registers:
– program counter (PC)
– memory address register (MAR)
– memory data register (MDR) // memory buffer register (MBR)
– current instruction register (CIR)
– accumulator (ACC)
3) Buses:
– address bus
– data bus
– control bus

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The Von Neumann model for a computer system has several components other than the CPU
and those within the CPU.
These components include:
1. Immediate Access Store (IAS)
2. Main Memory (RAM)
3. Input Device
4. Output Device
5. Secondary Storage Device

Immediate Access Store (IAS):

It temporarily holds data and instructions waiting to be processed after they are loaded from
the main memory.
It is used because read/write operations carried out using the IAS are considerably faster and
so any key data needed by an application will be stored temporarily in IAS to speed up
operations.
The Immediate Access Store (IAS) is another name for primary main memory (RAM).

Main Memory (RAM):

What is main memory and how it is used in the Von Neumann model for a computer system:
The main memory means the primary memory or RAM.
It is a volatile memory.
It is used to hold data/instructions that are currently in use.
It is directly accessed by the central processing unit (CPU).
Stored Program Concept when applied to the Von Neumann Model:
The program is stored on a secondary storage device.
The data and instructions are moved to main memory/RAM.
The data and instructions are stored in the same memory/RAM.
The data and instructions are moved to registers to be executed.
The instructions are fetched and executed in a sequence, one after another..

Input & Output Devices:

It is used to allow interaction with the computer.
Input device allows data to be entered into a computer system (e.g. keyboard, touch screen
& microphone etc.).
Output device allows the user to view/hear the data that has been entered into a computer
system (e.g. printer, monitor & loudspeaker etc.).

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The main components of the CPU (processor) are the arithmetic logic unit (ALU), the control unit
(CU) and the system clock.

Units:
Arithmetic & Logic Unit (ALU):
It is the component within the CPU that carries out calculations.
It performs arithmetic operations such as addition, subtraction, multiplication, division and
logical operations/comparisons such as AND, OR, NOT etc.
It holds temporary values during calculations in a register called the accumulator (ACC).

Control Unit (CU):

It is the component within the CPU that controls the flow of data and manages operations
between the components of the CPU (processor).
It sends/receives control signals that manage the transfer of data and execution of
instructions within the CPU.
It decodes an instruction using an instruction set.
It fetches instructions from memory, decodes them and synchronizes the operations before
sending signals to other components of the computer telling them “what to do”.
A system clock is used to generate the timing signals on the control bus to synchronize all
the components on the motherboard.
It controls the operations of memory, processor, and input/output.

Registers:
A register is a small piece of fast memory.
It is a temporary storage of data and instructions which is about to be or has been processed.
It is part of the processor.
A register can be general or special purpose.

Special Purpose Registers:

Memory Address Register (MAR):

It holds the address of the next/current instruction to be fetched/processed.
It holds the memory address of where the data needs to be stored.
It uses the address bus to send an address to another component.

Memory Data/Buffer Register (MDR):

It holds data or an instruction that are in use and has been fetched from the memory/the
address stored in MAR.
It is temporary storage of data between the CPU and primary memory.

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Program Counter (PC):
It holds the address of the next/current instruction to be fetched/processed/executed.
It uses the address bus to send an address to another component.
It increments to point to the address of the next instruction to be fetched and so stores the
number of processes that have been completed.

Current Instruction Register (CIR):

It holds the data received from the MDR.
It holds the current instruction that is to be executed/being processed.

Accumulator (ACC):
It is built into the arithmetic logic unit (ALU).
It temporarily holds the result of a calculation OR temporarily holds the data that is currently
being used in a calculation.

Memory:
The computer memory is made up of a number of partitions; each consisting of an address
and its contents.
The address uniquely identifies each location in the memory and the content is the binary
value stored in each location.

The following is a section of computer memory:

Address Contents

1111 0000 0111 0010

1111 0001 0101 1011

1111 0010 1101 1101

1111 0011 0111 1011

1111 1100 1110 1010

1111 1101 1001 0101

1111 1110 1000 0010

1111 1111 0101 0100

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Let us now consider two examples of how the MAR & MDR registers can be used when carrying out
a read and write operation to and from memory:

READ & WRITE Operations:

READ operation:

We will use the memory section shown below. Suppose we want to READ the contents of
memory location 1111 0001. We will use this address and its content:

Address Contents

1111 0000 0111 0010

1111 0001 0101 1011

1111 0010 1101 1101

1111 0011 0111 1011

1111 1100 1110 1010

1111 1101 1001 0101

1111 1110 1000 0010

1111 1111 0101 0100

The address of location 1111 0001 to be READ from is first WRITTEN into the MAR (memory
address register):

MAR 1 1 1 1 0 0 0 1

A read signal is sent to the computer memory using the control bus.
Then the contents of the memory location 1111 0001 are put into the MDR (memory data
register):

MDR 0 1 0 1 1 0 1 1

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WRITE operation:

We will again use the memory section shown below. Suppose we want to show how the value
1001 0101 was WRITTEN into the memory location 1111 1101.

Address Contents

1111 0000 0111 0010

1111 0001 0101 1011

1111 0010 1101 1101

1111 0011 0111 1011

1111 1100 1110 1010

1111 1101 1001 0101

1111 1110 1000 0010

1111 1111 0101 0100

The data to be stored is first WRITTEN into MDR (memory data register):

MDR 1 0 0 1 0 1 0 1

This data has to be WRITTEN into memory location with the address 1111 1101; so, this
address is now written into MAR (memory address register):

MAR 1 1 1 1 1 1 0 1

Finally, a write signal is sent to the computer memory using the control bus and the value
1001 0101 will then be written into the correct memory location.

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Examination Question Tips:
The examiner will give you a table of memory section like the ones above.
You will be asked to perform either READ or WRITE or maybe both operations.

In the part of READ operation:

The examiner will tell you that the content of a memory location e.g. 1111 0000 is to be READ
and then ask you to show contents of MAR and MDR during this READ operation.
There will be two registers given to you, one for MAR and one for MDR.
Now you simply have to write the address which is to be read e.g. 1111 0000 in the MAR
register.
The content value given in the table at this address will be simply copied and written into the
MDR register.

In the part of WRITE operation:

The examiner will tell you that the value e.g. 1100 1100 is to be written into memory location
e.g. 0011 1111 and then again ask you to show contents of MAR and MDR during this WRITE
operation.
There will be two registers given to you, one for MAR and one for MDR.
Now you simply have to write the value (content) which is to be written e.g. 1100 1100 in the
MDR register.
The memory location in which this value is to be written e.g. 0011 1111 will be simply written
in MAR register.

In the end:
The examiner may ask you to state or show any changes to the memory following the read
and write operations.
In this case, just look at the table of memory sections. Look at the two addresses used in both
parts of the questions.
If you find that any address has the value of its content missing, just state that value over
there which was given to you in any of the both parts depending upon which parts content
value is missing.

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Exam Style Questions:
Question 1:

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Question 2:

Answer:

(a)(i) 10010
(a)(ii) 11110001

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The following diagram shows how buses are used to connect the CPU to the memory and to
input/output devices:

Buses:
They are used to connect together the internal components of the CPU and provide a pathway
for transmitting data and instructions.
The data, address and control buses connect the processor, memory, and I/O controllers.
They essentially move data around the computer and send out control signals to ensure
everything is properly synchronized.

There are three common buses used in the Von Neumann architecture given below:
Address Bus:
It is a unidirectional bus (signals travel in one direction only).
It carries signals relating to addresses between the CPU/processor and the memory of the
next item to be fetched.

Width of Address Bus:

The width of the address bus determines the number of directly accessible memory locations.
Increasing the width of address bus significantly increases the number of directly
accessible/addressable memory locations.

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Benefit of increasing the address bus width from 16 bits to 32 bits:

A bus width of 16 bits can address 216 memory locations whereas a bus width of 32 bits allows
232 memory locations to be simultaneously accessed.

Data Bus:
It is a bi-directional bus (data can travel in both directions).
It sends data between the processor, the memory unit and the input/output devices that is
currently being processed.
The data can be an address, an instruction, or a numerical value.

Width of Data Bus:

The width of the data bus determines the number of bits that can be simultaneously
transferred.
Increasing the width of data bus increases the number of bits/amount of data that can be
moved at one time.
It improves processing speed and computer performance as fewer transfers are needed.
For example, double the width of the data bus moves 2x data per clock pulse.

Control Bus:
It is a bi-directional bus (signals can travel in both directions).
It carries control signals around the CPU and transmits timing signals to control all the
components.
It carries signals to synchronize the fetch-execute cycle.

It is usually 8-bits wide as there is no need for it to be any wider since it only carries control signals.

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Fetch–Decode–Execute Cycle:
The processor firstly fetches some data and instructions from memory and stores them in
suitable registers.
Both the address bus and data bus are used in this process.
Each instruction is then decoded before finally being executed.
This is known as the Fetch–Decode–Execute cycle.
To process an instruction, a central processing unit (CPU) goes through a cycle that has three
main stages:
Stage 1 → Fetch
Stage 2 → Decode
Stage 3 → Execute
How an instruction is fetched in a computer based on the Von Neumann model:
The program counter (PC) holds the address of the instruction.
The address held in the program counter (PC) is sent to memory address register (MAR).
The address is sent using the address bus.
The program counter (PC) is incremented.
The instruction is sent from the address in memory to memory data register (MDR).
The instruction is transferred using the data bus.
The instruction is sent to the current instruction register (CIR).
The component of the CPU that is responsible for decoding instructions:
Control Unit (CU)
How an instruction is executed in a computer based on the Von Neumann model:
The CPU passes the decoded instruction as a set of control signals using the control bus to
the appropriate components within the computer system.
This allows each instruction to be carried out in its logical sequence.

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The following diagram shows how the Fetch–Decode–Execute cycle is carried out in the Von
Neumann computer model:

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The stages in the fetch-execute cycle are shown in register transfer notation:

1. MAR  [PC]
2. PC  PC + 1
3. MDR  [ [MAR] ]
4. CIR  [MDR]
Purpose of the double brackets in [ [MAR] ]:
• The contents of the MAR is an address and it is the contents of that address which is
transferred to MDR.
Clock speed:
• It is a factor that affects the performance of a PC.
• The clock sends out a number of pulses in a given time interval (clock speed).
• Each processor instruction takes a certain number of clock cycles to execute.
• The higher the clock frequency, the shorter the execution time for the instruction so
increasing the clock frequency improves performance.

Alternative:
• It determines the number of cycles the CPU can execute per second.
• Increasing clock speed increases the number of operations/number of fetch-execute cycles
that can be carried out pet unit of time.
• However, there is a limit on clock speed because the heat generated by higher clock speeds
cannot be removed fast enough.
Purpose of a port:
• It provides a connection to peripheral devices and an interface between the computer and
other devices.

Benefits of using USB ports:

• The devices are automatically detected and configured when first attached so usually there is
no need to install separate device drivers.
• It allows fast data transfer that is useful when transferring large files such as video file.
• It has become an industrial standard adopted by many manufacturers meaning all new
computers will be equipped with USB ports.
• It allows power to be drawn to charge portable devices through USB so external devices may
be charged while working at the computer.
• It is nearly impossible to wrongly connect a device.
• USB 3.0 allows full duplex data transfer.
• The later versions are backwards compatible with earlier USB systems.

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Interrupt:
▪ It is a signal from a software source or hardware device seeking the attention of the processer.
Interrupt Handling:
▪ Transferring control to another routine when a service is required.
Describe the sequence of steps which would be carried out by the interrupt handler software
when an interrupt is received and serviced.
1. It will identify the source of the interrupt.
2. It will disable all interrupts of a lower priority.
3. It will save the contents of the PC and save the contents of the other registers onto the stack.
4. It will load and run the appropriate interrupt service routine (ISR) code.
5. Once the interrupting task is serviced then, it will restore the registers from the stack.
6. It will enable all interrupts.
7. It will continue execution of the interrupted process.

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Core, Cache & Clock:
We need to understand the meaning of the core, cache, and clock in a CPU. The number of cores,
size of the cache and speed of the clock can affect the performance of a CPU.

System Clock:
The control unit sends the signals on the control bus to coordinate events based on the pulses
of the system clock.
The system clock generates the timing signals and clock pulses are used to synchronize all
components on the motherboard.
It determines the number of cycles the CPU can execute per second as the clock sends out a
number of pulses in a given time interval (clock speed).
Clock Speed:
It is a factor that affects the performance of a PC.
Each instruction is executed on a clock pulse e.g., one F-E cycle is run on each clock pulse.
So, the clock speed dictates the number of instructions that can be run per second.
Increasing the clock speed increases the number of instructions/number of fetch-execute
cycles that can be run per second.
The higher the clock frequency, the shorter the execution time for the instruction so
increasing the clock frequency improves performance.

However, there is a limit on clock speed because the heat generated by higher clock speeds
cannot be removed fast enough.

Overclocking: The clock speed can be changed by accessing the BIOS (Basic Input/Output
System) and altering the settings.

Using clock speed higher than the computer was designed for can lead to problems, such as:

1. The execution of instructions outside design limits, which can lead to seriously
unsynchronized operations (in other words, an instruction is unable to complete in time
before the next one is due to be executed) and the computer would frequently crash
and become unstable.
2. It can cause serious overheating of the CPU leading to unreliable performance.

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Computer Performance:
As discussed earlier, by increasing the clock speed the processing speed of the computer is also
increased. However, it is not possible to say that a computer’s overall performance is necessarily
increased by using a higher clock speed.

Four other factors need to be considered:

1. The width of the address bus and data bus can affect computer performance.

Increasing the width of buses allows more memory locations to be directly accessed and
allows the transfer of more data per clock pulse. It improves processing speed and computer
performance.

2. Overclocking: using a clock speed higher than the computer was designed for can lead
to problems, such as:

1) The execution of instructions outside design limits, which can lead to seriously
unsynchronized operations (in other words, an instruction is unable to complete in
time before the next one is due to be executed) and the computer would frequently
crash and become unstable
2) It can cause serious overheating of the CPU leading to unreliable performance.

3. The use of cache memory can also improve CPU performance.

Cache memory is located within the CPU, and it uses SRAM so cache memories will have
faster access times, since there is no need to keep refreshing, which slows down access time.
Cache memory stores frequently used instructions and data that need to be accessed faster.
The larger the cache memory size, the more frequency used instructions it can store for fast
access and better the CPU performance.

4. The use of a different number of cores can improve computer performance (one core
is made up of an ALU, a CU and the registers).

Many computers are dual core (the CPU is made up of two cores) or quad core (the CPU is
made up of four cores).
Each core processes one instruction per clock pulse. More/multiple cores mean that sequence
of instructions can be split between them and so more than one instruction is executed per
clock pulse and more sequence of instructions can be run at the same time.
Therefore, more cores decrease the time taken to complete task and improves CPU
performance.

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 Potential Problem:

However, doubling the number of cores does not necessarily double the computer’s
performance since CPU needs to communicate with each core and this will reduce overall
performance.
For example:
The dual core has one channel and needs the CPU to communicate with both cores
using one channel, reducing some of the potential increase in its performance.
The quad core has six channels and needs the CPU to communicate with all four cores
using six channels, considerably reducing potential performance.

Summary of factors affecting computer performance:

1. Clock Speed: higher clock speed means more Fetch—Decode—Execute cycles per second.
2. Number of Cores: more cores mean more instructions can be carried out simultaneously.
3. Bus Width: increasing width allows transfer of more data each time and allows more memory
location to be directly accessed.
4. Cache: the higher the capacity of cache memory, the more frequently used instructions it can
store for fast access.

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3.1.4 Instruction Set:
An instruction set is a list of all the commands that can be processed by a CPU and the commands
are machine code.
The instructions are a set of operations which are decoded in a sequence by CPU using the sequence
of steps of Fetch–Decode–Execute cycle to process each instruction in sequence.
The Current Instruction Register (CIR) holds the op code and operand of an instruction ready for it
to be decoded.
Operations:
Each operation will instruct the Arithmetic Logic Unit (ALU) & Control Unit (CU) which are part
of the Central Processing Unit (CPU).
An operation is made up of an opcode & operand.
Some examples of instruction set operations include ADD, JMP, LDA, and so on.
Opcode & Operand:
The opcode informs the CPU what operation needs to be done.
The operand is the data which needs to be acted on or it can refer to a register in the memory.
Example of Instruction Set:
An example of an instruction set is the X86, a common CPU standard used in many modern
computers.
If the computer is based on the X86 CPU then all designs will share almost identical instruction
sets despite different electronic designs.
Differences between Program Code & Instruction Set:
The instruction set is machine code instructions that instruct the CPU about how to carry out
an operation.
The program code needs interpreters or compilers to convert the code into the instruction
set understood by the computer.
Therefore, instruction sets must not be confused with program code.

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Addressing:
Direct addressing:
• The operand is the address where the data is stored / the operand is the address of the value
to be used.
• It loads the contents of the given address to Accumulator (ACC).
• For example: LDD 300

Indirect addressing:
• The operand is an address, that address holds another address where the data is stored /
another address of the value to be used.
• It loads the contents of the address held at the given address to Accumulator (ACC).

Indexed addressing:
• The operand plus contents of Index Register (IX) is the address of the value to be used.
• It then loads the contents of the calculated address to Accumulator (ACC).
• For example: LDX 20

Immediate addressing:
• The operand is not an address but instead the actual value to be loaded / the operand is the
value to be used.
• It loads the given value directly to Accumulator (ACC).
• For example: ADD #20, LDM #300

Relative addressing:
• The operand is the offset from the current address where the value to be used is stored.
• It forms the address by adding the given number to a base address.
• It loads the contents of the calculated address to the Accumulator (ACC).

Symbolic addressing:
• The operand is a word/symbol.
• A word/symbol represents the memory location/address.
• For example: ADD num1

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Absolute addressing:
• The operand is a numeric address.
• The numeric address refers directly to a memory location.
• For example: ADD 230

Assembly Language:
Solve Topicals
Logical Shifts:
Added In Chapter 1

Bit Manipulation Used in Monitoring & Control:

The controlling computer or microprocessor has to have a real-time program running
continuously. The program can set values for Boolean variables subject to what the sensors
detect. For instance, if a controlled environment had two properties to be monitored
and controlled, four Boolean variables could be used. Values could be set by assignment
statements such as:
IF SensorDifference1 > 0 THEN Sensor1HighFlag ← TRUE
IF SensorDifference1 < 0 THEN Sensor1LowFlag ← TRUE
IF SensorDifference2 > 0 THEN Sensor2HighFlag ← TRUE
IF SensorDifference2 < 0 THEN Sensor2LowFlag ← TRUE
Another part of the monitoring and control program would then be checking whether any of
the four flags were set. The machine code for running such a program could use individual
bits to represent each flag. The way that flags could be set and read are illustrated by the
following assembly language code fragments. In these code fragments the three least
significant bits (positions 0, 1 and 2) of the byte are used as flags

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The following illustrates the setting of all bits to zero
which might be used when the system is
switched on.
LDD 0034 Loads a byte into the accumulator from an address.
Uses a bitwise AND operation of the contents of the
AND #B00000000 accumulator with the
operand to convert each bit to 0.
STO 0034 Stores the altered byte in the original address.
The following illustrates the toggling of the value for one
bit. This changes the value of the flag it
represents. It might be needed because a problem has
been encountered or alternatively because a
problem has been solved.
LDD 0034 Loads a byte into the accumulator from an address.
Uses a bitwise XOR operation of the contents of the
XOR #B00000001 accumulator with the
operand to toggle the value of the bit stored in position 0.
STO 0034 Stores the altered byte in the original address.
The following illustrates the setting of a bit to have value 1
irrespective of its existing value. This would be
a simple way of just reporting a condition repetitively.
LDD 0034 Loads a byte into the accumulator from an address.
Uses a bitwise OR operation of the contents of the
accumulator with the
OR #B00000100 operand to set the flag represented by the bit in position 2.
All other bit
positions remain unchanged.
STO 0034 Stores the altered byte in the original address.
The following illustrates setting all bits to zero except one
bit which is of interest. Following this operation,
a comparison can be made with a binary value to check if
the bit is set. In this example the value would
be compared to the binary equivalent of denary 2.
LDD 0034 Loads a byte into the accumulator from an address.
Uses a bitwise AND operation of the contents of the
accumulator with the
AND #B00000010 operand to leave the value in position 1 unchanged but to
convert every other
bit to 0.
STO 0034 Stores the altered byte in the original address.

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