Synthesis

Onkar Sanjay Mane

 © Onkar Sanjay Mane
What is Synthesis?
• A process of converting high level description of design into
optimized gate-level representation (Netlist) given a standard cell
library and certain design constraints.

Netlist: It is a detailed representation of a digital circuit that

describes its implementation using logic gates and their
interconnections
 © Onkar Sanjay Mane
RTL Code LIB
Optimized
Gate-Level SDC
LEF TECH file Synthesis Tool Netlist

UPF Report Files

UPF file RLC file

INPUTS
DEF file

Netlist
OUTPUTS

SDC file DEF file Optimized

Synthesis Tool
Netlist
INPUTS
 © Onkar Sanjay Mane
Steps Steps :
Translation
INPUTS Synthesis Tool Optimization
Mapping

Steps :
Netlist Optimization
of netlist

Optimized OUTPUTS
INPUTS Synthesis Tool Netlist
 © Onkar Sanjay Mane
Input files
1) High-Level Description:
A hardware description of the design, typically written in a hardware
description language (HDL) like Verilog or VHDL. This description captures
the intended functionality of the digital circuit.

Example:

module not_gate ( input wire a, output wire y);

assign y = ~a;
endmodule
 © Onkar Sanjay Mane
2)Liberty File (.lib)
• LIB file is an ASCII representation of timing parameters associated
with cells inside the standard cell library of a particular technology
node.

Standard cells are pre-designed and pre-characterized building

blocks used to create complex digital circuits, such as logic gates
(AND, OR, NOT), flip-flops, and other functional elements.

• Lib file is basically a timing model file which contains cell delay,
cell transition time, setup and hold time requirement of the cell.

• Lib file basically contains the timing and electrical characteristics

of a cell or macros.
 © Onkar Sanjay Mane
Components of a .lib File:
I. Library Header : Contains metadata about the library, including its
name, version, and other general information.
Example:

II. Cell Definitions:

Defines individual standard cells within the library.
Example:
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III. Pin Information: Specifies the pins for each cell, including their
directions (input, output, or inout), and sometimes the physical
location or layout of the pins.
Example:

IV. Timing Information: Describes how the cell's output timing is related
to its inputs, including setup and hold times, propagation delays, and
other timing constraints.
Example:
 © Onkar Sanjay Mane
V. Power and Ground Information: Provides details about the power
(VDD) and ground (GND) connections of the cell.
Example:

VI. Cell Area: Specifies the physical area of the cell, which can be
important for placement and floor-planning during chip design.
 © Onkar Sanjay Mane
3) LEF file:
• The LEF (Library Exchange Format) file is a text-based format used to
describe the physical characteristics of cells in a semiconductor library.

Components of a .lef File:

I. Header Section: The header section provides general information
about the LEF file and its version.
Example:
 © Onkar Sanjay Mane
II. Library Section: This section describes the overall library and its
properties.
Example:

III. Cell Definitions: Each cell is defined in this section,

including its size, pin locations, and any
obstructions.
Example:
 © Onkar Sanjay Mane
IV. Layer Definitions: This section describes the different layers used in the
design, including their properties Example:

V. End of File: The end of the LEF file is marked with an ‘END’ statement
that closes the library definition.
Example:
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4) SDC File:
• An SDC (Synopsys Design Constraints) file is a critical component in
digital design for defining and managing timing and physical constraints in
an ASIC design flow.

• The SDC file provides essential information that helps these tools optimize
the design to meet performance requirements and ensure proper
functionality.
Example:

• During synthesis, the SDC file helps the synthesis tool optimize the design
to meet timing requirements and other constraints.
 5)UPF file:

© Onkar Sanjay Mane

• A UPF (Unified Power Format) file is used in digital design, particularly in
the context of power management for integrated circuits.
• It's a standard format developed to specify power intent, which helps in
ensuring that the design operates correctly within its power constraints
and can be optimized for power consumption.
• Key Terminologies:
1. Power Domain: A power domain represents a group of design blocks
that can be independently powered or powered off.
2. Power Source: Power sources are the voltage supplies that provide
power to the power domains.
3. Power States: Power states define the operational modes of power
domains, such as whether they are powered on or off.
 © Onkar Sanjay Mane
4. Power Mode: Power mode determines how power domains are
powered or controlled during different operating conditions or modes
of the design.
5. Power Gating and Isolation:
Power Gating: Technique to shut off power to certain parts of the
design to save energy. UPF supports specifying how and when power
gating should occur.
Isolation: Ensures that powered-down sections of the design do not
interfere with powered sections. UPF allows you to define isolation cells
and their behaviour.
 6)RLC file

© Onkar Sanjay Mane

• An RLC file contains parasitic information about the physical interconnects in
a design. This file provides details on resistance, inductance, and capacitance
values of the interconnects, which are crucial for accurate signal integrity and
timing analysis.
• RC Delay Impact: Resistance (R) and capacitance (C) of interconnects
significantly affect signal propagation delays (RC delay), which can lead to
timing violations. Synthesis tools must optimize the design to meet timing
requirements despite these delays.
• Capacitance and Resistance Constraints: Load capacitance impacts delay and
power consumption, while wire resistance affects voltage drops and signal
integrity. Synthesis tools impose constraints on maximum capacitance and
manage resistance to ensure reliable circuit operation.
• Optimization Techniques: To manage RC delays and meet design
specifications, synthesis tools use techniques like buffer insertion, wire sizing,
and gate sizing, balancing trade-offs between delay, power, and area.
 © Onkar Sanjay Mane
7) DEF File
• The DEF file is a standard format used to describe the physical layout
of an integrated circuit (IC) design. It contains detailed information
about the placement of cells, pin locations, blockages, and various
other layout aspects
• How DEF File Impacts Synthesis
Synthesis Tools Optimization: The DEF file provides physical layout
information that allows synthesis tools to generate a netlist optimized
for the existing layout
Efficient Integration: The DEF file helps in creating a more cohesive
design flow by ensuring that synthesis and physical design tools work
with consistent and accurate information.
 © Onkar Sanjay Mane
Outputs of the synthesis:
1) Optimized gate level netlist: It is a key output of the synthesis
process in digital IC design. It represents the circuit in terms of
gates and their interconnections, optimized for both
functionality and performance based on a set of constraints.
Optimized means?
Optimization means that the synthesis process has refined the
netlist to meet specific design constraints, such as timing, area,
and power consumption.
Example:
2)Report Files:

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Timing Report:
Summary Report: • Clock Frequencies
• Design Summary • Critical Path
• Number of Cells • Setup and Hold Times
• Total Area • Slack

Power Report:
• Power Estimates Area Report:
• Leakage Power • Cell Area
• Dynamic Power • Utilization
• Power Distribution
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3) Output DEF file:
During synthesis, a DEF file is generated that includes information about
macro and standard cell placements. This DEF file can be directly used in
the physical implementation stage, eliminating the need to start cell
placement from scratch and thereby saving runtime

4) Output SDC file:

The output SDC file is an updated version of the input SDC file. During
synthesis, the constraints provided by the designer are applied, and
additional local constraints are used to enhance the overall Quality of
Results (QoR) of the design. Consequently, the updated SDC file is
generated after the synthesis process.
 © Onkar Sanjay Mane
5) Output UPF file:
The output UPF file is an updated version of the input UPF file.
During synthesis, logic optimization is performed, which can
introduce new power intents. Therefore, the UPF file is regenerated
after synthesis to reflect these updates.