History of Intel Microprocessors

Intel, with the help of Ted Hoff, introduced the world's

first microprocessor, the Intel 4004, on November 15, 1971.
The 4004 had 2,300 transistors, performed 60,000 OPS
(operations per second), addressed 640 bytes of memory, and
cost $200.00.
Intel introduced the 8008 processor on April 1, 1972.
Intel's improved microprocessor chip was introduced on April 1,
1974; the 8080 became a standard in the computer industry.
Intel introduced the 8085 processor in March 1976.
The Intel 8086 was introduced on June 8, 1978.
The Intel 8088 was released on June 1, 1979.
The Intel 80286 was introduced on February 1, 1982.
Intel introduced the first 80386 in October 1985.
Intel 80386SX was introduced in 1988.
Intel introduced the Intel 486SX chip in April to help bring a
lower-cost processor to the PC market selling for $258.00.
Intel released the 486DX2 chip on March 2, 1992, with a clock
doubling ability that generates higher operating speeds.
Intel released the Pentium processor on March 22, 1993. The
processor was a 60 MHz processor, incorporates 3.1 million
transistors, and sells for $878.00.

Pin Diagram and Pin description of 8086

The following pin function descriptions are for the microprocessor 8086 in either minimum or
maximum mode.

AD0 - AD15 (I/O): Address Data Bus

These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1) and
data during T2, T3 and T4 clock cycles. A0 is analogous to BHE for the lower byte of the data bus,
pins D0-D7. A0 bit is Low during T1 state when a byte is to be transferred on the lower portion of the
bus in memory or I/O operations. 8-bit oriented devices tied to the lower half would normally use A0
to condition chip select functions. These lines are active high and float to tristate during interrupt
acknowledge and local bus "Hold acknowledge"…..
A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status

During T1 state these lines are the four most significant address lines for memory operations. During
I/O operations these lines are low. During memory and I/O operations, status information is available
on these lines during T2, T3, and T4 states.S5: The status of the interrupt enable flag bit is updated at
the beginning of each cycle. The status of the flag is indicated through this bus.

S6:

When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock period,
the 8086 tri-states the S6 pin and thus allows another bus master to take control of the status bus.

S3 & S4:

Lines are decoded as follows:

A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

After the first clock cycle of an instruction execution, the A17/S4 and A16/S3 pins specify which
segment register generates the segment portion of the 8086 address. Thus by decoding these lines
and using the decoder outputs as chip selects for memory chips, up to 4 Megabytes (one Mega per
segment) of memory can be accesses. This feature also provides a degree of protection by
preventing write operations to one segment from erroneously overlapping into another segment
and destroying information in that segment.

BHE /S7 (O): Bus High Enable/Status

During T1 state the BHE should be used to enable data onto the most significant half of the data bus,
pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to
control chip select functions. BHE is Low during T1 state of read, write and interrupt acknowledge
cycles when a byte is to be transferred on the high portion of the bus.
The S7 status information is available during T2, T3 and T4 states. The signal is active Low and floats
to 3-state during "hold" state. This pin is Low during T1 state for the first interrupt acknowledge cycle.

RD (O): READ

The Read strobe indicates that the processor is performing a memory or I/O read cycle. This signal is
active low during T2 and T3 states and the Tw states of any read cycle. This signal floats to tri-state in
"hold acknowledge cycle".

TEST (I)

TEST pin is examined by the "WAIT" instruction. If the TEST pin is Low, execution continues.
Otherwise the processor waits in an "idle" state. This input is synchronized internally during each
clock cycle on the leading edge of CLK.
INTR (I): Interrupt Request

It is a level triggered input which is sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt acknowledge operation. A subroutine is
vectored to via an interrupt vector look up table located in system memory. It can be internally
masked by software resetting the interrupt enable bit INTR is internally synchronized. This signal is
active HIGH.

NMI (I): Non-Maskable Interrupt

An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt
vector look up table located in system memory. NMI is not maskable internally by software. A
transition from a LOW to HIGH on this pin initiates the interrupt at the end of the current instruction.
This input is internally synchronized.

Reset (I)

Reset causes the processor to immediately terminate its present activity. To be recognised, the signal
must be active high for at least four clock cycles, except after power-on which requires a 50 Micro
Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros. It also initializes
CS to FFFF H. Upon removal of the RESET signal from the RESET pin, the 8086 will fetch its next
instruction from the 20 bit physical address FFFF0H. The reset signal to 8086 can be generated by the
8284. (Clock generation chip). To guarantee reset from power-up, the reset input must remain below
1.5 volts for 50 Micro sec. after Vcc has reached the minimum supply voltage of 4.5V.
Ready (I)

Ready is the acknowledgement from the addressed memory or I/O device that it will complete the
data transfer. The READY signal from memory or I/O is synchronized by the 8284 clock generator to
form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation
is not guaranteed if the setup and hold times are not met.

CLK (I): Clock

Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33% duty
cycle to provide optimized internal timing. Minimum frequency of 2 MHz is required, since the
design of 8086 processors incorporates dynamic cells. The maximum clock frequencies of the 8086-4,
8086 and 8086-2 are4MHz, 5MHz and 8MHz respectively.
Since the 8086 does not have on-chip clock generation circuitry, and 8284 clock generator chip must
be connected to the 8086 clock pin. The crystal connected to 8284 must have a frequency 3 times
the 8086 internal frequency. The 8284 clock generation chip is used to generate READY, RESET and
CLK.

MN/MX (I): Maximum / Minimum

This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself
generates all bus control signals. In maximum mode the three status signals are to be decoded to
generate all the bus control signals.
Minimum Mode Pins The following 8 pins function descriptions are for the 8086 in minimum mode;
MN/ MX = 1. The corresponding 8 pins function descriptions for maximum mode is explained later.
M/IO (O): Status line

This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it accesses
I/O and when high it access memory. M / IO becomes valid in the T4 state preceding a bus cycle and
remains valid until the final T4 of the cycle. M/IO floats to 3 - state OFF during local bus "hold
acknowledge".

WR (O): Write

Indicates that the processor is performing a write memory or write IO cycle, depending on the state
of the M /IOsignal. WR is active for T2, T3 and Tw of any write cycle. It is active LOW, and floats to 3-
state OFF during local bus "hold acknowledge ".

INTA (O): Interrupt Acknowledge

It is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3, and T4 of
each interrupt acknowledge cycle.

ALE (O): Address Latch Enable

ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an active
high pulse during T1 of any bus cycle. ALE signal is never floated.
DT/ R (O): DATA Transmit/Receive

In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the
direction of data flow through the transceiver. This signal floats to tri-state off during local bus "hold
acknowledge".

DEN (O): Data Enable

It is provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver.
DEN is active LOW during each memory and IO access. It will be low beginning with T2 until the
middle of T4, while for a write cycle, it is active from the beginning of T2 until the middle of T4. It
floats to tri-state off during local bus "hold acknowledge".

HOLD & HLDA (I/O): Hold and Hold Acknowledge

Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged, HOLD
must be active HIGH. The processor receiving the "HOLD " request will issue HLDA (HIGH) as an
acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue of HLDA, the
processor will float the local bus and control lines. After "HOLD" is detected as being Low, the
processor will lower the HLDA and when the processor needs to run another cycle, it will again drive
the local bus and control lines.
Maximum Mode The following pins function descriptions are for the 8086/8088 systems in maximum
mode (i.e.. MN/MX = 0). Only the pins which are unique to maximum mode are described below.

S2, S1, S0 (O): Status Pins

These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or
Tw (when ready is inactive). These are used by the 8288 bus controller to generate all memory and
I/O operation) access control signals. Any change by S2, S1, S0 during T4 is used to indicate the
beginning of a bus cycle. These status lines are encoded as shown in table 3.

Table 3

QS0, QS1 (O): Queue – Status

QS1 QS1 Characteristics

0 0 No operation

0 1 First byte of opcode from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

Table 4

LOCK (O)

It indicates to another system bus master, not to gain control of the system bus while LOCK is active
Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active until the
completion of the instruction. This signal is active Low and floats to tri-state OFF during 'hold
acknowledge'. Example:
 LOCK XCHG reg., Memory ; Register is any register and memory GT0
; is the address of the semaphore.

RQ/GT0 and RQ/GT1 (I/O): Request/Grant

Registers

These pins are used by other processors in a multi processor organization. Local bus masters of other
processors force the processor to release the local bus at the end of the processors current bus cycle.
Each pin is bi-directional and has an internal pull up resistors. Hence they may be left un-connected.

Computer registers are high-speed memory storing units. It is an element of the

computer processor. It can carry any type of information including a bit sequence or
single data.
A register should be 32 bits in length for a 32-bit instruction computer. Registers can be
numbered relies upon the processor design and language rules.
The instructions in a computer are saved in memory locations and implemented one
after another at a time. The function of the control unit is to fetch the instruction from
the memory and implement it. The control does the similar for all the instructions in the
memory in sequential order.
A counter is needed to maintain a path of the next instruction to be implemented and
evaluate its address. The figure shows the registers with their memories. The memory
addresses are saved in multiple registers. These requirements certainly state the use
for registers in a computer.
The following table shows the registers and their functions .

Register Number Register Name Function

Symbol of Bits

OUTR 8 Output register OIt holds output character.

INPR 8 Input register It holds input character.

PC 12 Program It holds the address of the instruction.

Counter

AR 12 Address It holds an address for memory.

 Register Number Register Name Function
Symbol of Bits

Register

DR 16 Data Register It holds memory operand.

AC 16 Accumulator It’s a processor register.

IR 16 Instruction It holds an instruction code.

Register

TR 16 Temporary It holds temporary data.

Register
The description for each of the registers determined in the figure is as follows −

 The data register holds the operand read from the memory.
 The accumulator is a general-purpose register need for processing.
 The instruction register holds the read memory.
 The temporary data used while processing is stored in the temporary register.
 The address register holds the address of the instruction that is to be
implemented next from the memory.
 The Program Counter (PC) controls the sequence of instructions to be read. In
case a branch instruction is detected, the sequential execution does not arise. A
branch execution calls for a transfer to an instruction that is not in sequence with
the instructions in the PC.
 The input register (INPR) and output register (OUTPR) are the registers used for
the I/O operations. The INPR receives an 8-bit character from the input device. It
is similar to the OUTPR.

ALU
Inside a computer, there is an Arithmetic Logic Unit (ALU), which is capable of performing
logical operations (e.g. AND, OR, Ex-OR, Invert etc.) in addition to the arithmetic operations (e.g.
Addition, Subtraction etc.). The control unit supplies the data required by the ALU from memory,
or from input devices, and directs the ALU to perform a specific operation based on the
instruction fetched from the memory. ALU is the “calculator” portion of the computer.

An arithmetic logic unit(ALU) is a major component of the central processing unit of the
a computer system. It does all processes related to arithmetic and logic operations that
need to be done on instruction words. In some microprocessor architectures, the ALU
is divided into the arithmetic unit (AU) and the logic unit (LU).
An ALU can be designed by engineers to calculate many different operations. When
the operations become more and more complex, then the ALU will also become more
and more expensive and also takes up more space in the CPU and dissipates more
heat. That is why engineers make the ALU powerful enough to ensure that the CPU is
also powerful and fast, but not so complex as to become prohibitive in terms of cost
and other disadvantages.
ALU is also known as an Integer Unit (IU). The arithmetic logic unit is that part of the
CPU that handles all the calculations the CPU may need. Most of these operations are
logical in nature. Depending on how the ALU is designed, it can make the CPU more
powerful, but it also consumes more energy and creates more heat. Therefore, there
must be a balance between how powerful and complex the ALU is and how expensive
the whole unit becomes. This is why faster CPUs are more expensive, consume more
power and dissipate more heat.
Different operation as carried out by ALU can be categorized as follows –
 logical operations − These include operations like AND, OR, NOT, XOR, NOR,
NAND, etc.
 Bit-Shifting Operations − This pertains to shifting the positions of the bits by a
certain number of places either towards the right or left, which is considered a
multiplication or division operations.
 Arithmetic operations − This refers to bit addition and subtraction. Although
multiplication and division are sometimes used, these operations are more
expensive to make. Multiplication and subtraction can also be done by repetitive
additions and subtractions respectively.
Introduction to Microcontroller
A microcontroller is an electronic device belonging to the microcomputer family. These are
fabricated using the VLSI technology on a single chip. There are microcontrollers available in
the present market with different word length starting from 4 bit, 8 bit, 64 bit to 128 bit. This
chapter is about microcontrollers, their architecture, and various features.

Microcontroller
In a broader sense, the components which constitute a microcontroller are the memory,
peripherals and most crucially a processor. Microcontrollers are present in devices where the
user has to exert a degree of control. They are designed and implemented to execute a specific
function such as displaying integers or characters on an LCD display module of a home
appliance. Application of microcontrollers is myriad. In simpler terms, any gadget or
equipment which has to deal with the functions such as measuring, controlling, displaying and
calculating the values consist of a microcontroller chip inside it. They are present in almost all
the present day home appliances, toys, traffic lights, office instruments and various day-to-day
appliances.

The most important part of a microcontroller is a central processing unit with a word
length ranging from 4-bit to 64-bit and in some modern microcontrollers the word length goes
even beyond the limit of 64-bit. A timer is one other constituent of a microcontroller. There is
a watchdog timer. Memory spaces such as RAM, ROM, EEPROM, EPROM are there to store
data and programs. For data storage, volatile memory RAM is used while for the program and
operating parameter storage ROM and other memory spaces are used.

CPU: Being regarded as the brain of the microcontroller, central processing unit fetches,
decodes and executes the instructions. It coordinates various activities taking place in the
microcontroller.

I/O ports: There are several parallel input/output ports in a microcontroller. They are used to
interface various peripherals such as printers, external memories, LEDs and LCDs to the
microcontroller. Apart from parallel ports, there are serial ports to interface serially connected
peripherals with the microcontroller.

Memory: As in the case of a microprocessor, a microcontroller has spaces for memories

such as RAM, ROM including EEROM and EPROM. It also allocates a certain amount of
flash memory to store program source code.

Timers and counters: These are the fascinating constituent parts of a microcontroller. Timers
and counters are used in operations which include modulation, clock functions, frequency
generation and measuring and pulse generation.

Analog to digital converters (ADCs): Such converters are useful while converting the output
of a sensor which would be in analog form.

Digital to analog converter (DAC): The working of a DAC is just the reverse of an analog to
digital converter. As it is obvious, the output will be an analog signal which can be used to
control the analog peripherals such a motor.

Features of a Microcontroller
 The main advantage of a CISC (complex instruction set computer) architecture, with which the modern
microcontrollers are built, is the macro-type instructions. A macro instruction can be used in a program
replacing a number of instructions.
 Latest microcontrollers are operated at lesser power consumption. Usually, they can support a working
voltage of 1.8-5.5 V.
 Advanced memory is another feature of a microcontroller. Use of ROM memories like EEPROM and
EPROM (flash memory) make it more reliable and user-friendly. While EEPROM is a relatively slow
memory, EPROM is faster. Fact that it allows more erase/write cycles also makes it more usable.

Advantages
The main advantage of a microcontroller is that the low cost with all the integral parts
mounted together on a single chip. The design makes it more compact and easy to use. The
easiness of using a microcontroller and the relatively easy maintenance process also make it
more reliable. Almost all the pins in a microcontroller are programmable and it makes the
microcontroller a lot user-friendly. Simplicity while interfacing ROM, RAM, and I/O ports.
Easiness of troubleshooting and a minimal time requirement for various operations are other
crucial advantages.
Disadvantages
Since it contains all the components on a single chip, microcontrollers are having relatively
complex architecture. Microcontrollers are not suitable to interface high power devices
directly and they can only perform the limited number of operations simultaneously.

What is ROM?
ROM stands for Read-only Memory. It is a type of memory that does not lose its
contents when the power is turned off. For this reason, ROM is also called non-
volatile memory.
Because ROMs are deployed in such a wide variety of applications, there are different
types of ROMs suited to different applications across the industry.
Different Types of ROM
1. PROM (programmable ROM) and OTP
PROM refers to the kind of ROM that the user can burn information into. In other
words, PROM is a user-programmable memory.
2. EPROM (erasable programmable ROM) and UV-EPROM
EPROM was invented to allow making changes in the contents of PROM after it is
burned.
In EPROM, one can program the memory chip and erase it thousands of times. This is
especially necessary during the development of the prototype of a microprocessor-
based project.