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AHB Interview Questions 5 6

vlsi interview

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26 views2 pages

AHB Interview Questions 5 6

vlsi interview

Uploaded by

pravin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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19. Does the address have to be aligned, even for IDLE transfers?

Yes. The address should be aligned according to the transfer size (HSIZE) even for IDLE transfers. This will
prevent spurious warnings from bus monitors used during simulation.

20. What is the difference between a dummy bus master and a default bus master?

The term default bus master is used to describe the master that is granted when none of the masters in
the system are requesting access to the bus. Usually the bus master which is most likely to request the
bus is made the default master.

The dummy bus master is a master which only performs IDLE transfers. It is required in a system so the
arbiter can grant a master which is guaranteed not to perform any real transfers. The two cases when
the arbiter would need to do this are when a SPLIT response is given to a locked transfer and when a
SPLIT response is given and all other masters have already been SPLIT.

21. Is it legal for a master to change HADDR when a transfer is extended?

If a master is indicating that it wants to do a NONSEQ, SEQ or BUSY transfer then it cannot change the
address during an extended transfer (when HREADY is low) unless it receives an ERROR, RETRY or SPLIT
response.

If the master is indicating that it wants to do an IDLE transfer then it may change the address.

22. Can HTRANS change whilst HREADY is low?

In general, an AHB master should not change control signals whilst HREADY is low. However it is
allowable to change HTRANS in the following conditions:

* HTRANS = IDLE

The AHB master is performing internal operations and has not yet committed to a bus transfer. However
during the AHB wait states (HREADY low) the master may determine that a bus transfer is required and
change HTRANS on the next cycle to NONSEQ.

* HTRANS = BUSY

HTRANS is being used to give the master time to complete internal operations, which may be entirely
independent of HREADY (i.e. wait states on the AHB). Therefore HTRANS can change on the next cycle to
any legal value, i.e. SEQ if the burst is to continue, IDLE if the burst has completed, NONSEQ if a separate
burst is to begin.
* HRESP = SPLIT/RETRY

As stated in the AHB specification, a master must assert IDLE on HTRANS during the second cycle of the
two-cycle SPLIT or RETRY slave response so HTRANS will change value from the first cycle to the second
cycle of the response.

* HRESP = ERROR

The master is permitted to change HTRANS in reaction to an ERROR response in the same way as in
reaction to a SPLIT/RETRY response and cancel any further beats in the current burst (even if HBURST is
indicating a defined-length burst). In this case HTRANS changes to IDLE on the second cycle of the
response. Alternatively, the master is permitted to continue with the current transfers.

23. What are the different bursts used for?

Typically a master would use wrapping bursts for cache line fills where the master wants to access the
data it requires first and then it completes the burst to fetch the remaining data it requires for the cache
line fill.

Incrementing bursts are used by masters, such as DMA controllers, that are filling a buffer in memory
which may not be aligned to a particular address boundary.

24. What sequences of transfers types (HTRANS) can occur on the bus?

The following examples show some of the sequences of HTRANS that can occur on the bus:

A normal burst of four transfers followed by an IDLE.

N-S-S-S-I

A normal burst of four transfers which includes BUSY transfers.

N-S-B-S-B-S-I

A burst of four transfers followed by another burst.

N-S-S-S-N-S-S-S-I

A single transfer followed by a burst of four transfers.

N-N-S-S-S-I

A single transfer followed by an IDLE

N-I

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