1.

Explain IC Fabrication Process in detail

The fabrication of integrated circuits consists basically of the following process steps:
 Lithography: The process for pattern definition by applying thin uniform layer of viscous
liquid (photo-resist) on the wafer surface. The photo-resist is hardened by baking and than
selectively removed by projection of light through a reticle containing mask information.
 Etching: Selectively removing unwanted material from the surface of the wafer. The pattern
of the photo-resist is transferred to the wafer by means of etching agents.
 Deposition: Films of the various materials are applied on the wafer. For this purpose mostly
two kind of processes are used, physical vapor deposition (PVD) and chemical vapor
deposition (CVD).
 Chemical Mechanical Polishing: A planarization technique by applying a chemical slurry
with etchant agents to the wafer surface.

 Oxidation: In the oxidation process oxygen (dry oxidation) or H O (wet oxidation)

molecules convert silicon layers on top of the wafer to silicon dioxide.
 Ion Implantation: Most widely used technique to introduce dopant impurities into
semiconductor. The ionized particles are accelerated through an electrical field and targeted at
the semiconductor wafer.
 Diffusion: A diffusion step following ion implantation is used to anneal bombardment-
induced lattice defects.
 CMOS means Complementary Metal Oxide Semiconductor. It is used to fabricate digital
circuits and IC chips. It is a combination of NMOS (N-type Metal Oxide Semiconductor) and
PMOS (P-type Metal Oxide Semiconductor) transistor pairs that are symmetrical. CMOS
fabrication can be carried out in many ways. P-well is one of the processes in which CMOS
circuits are realized.
Making of CMOS using P well Technology
 The CMOS fabrication steps of the p-well process are the same as that of an n-well process
except that instead of an n-well a p-well is implanted. the process starts with an n-type
substrate.
 Step 1: A thin Sio2 layer is deposited on an n-type semiconductor material which acts
insulator to the environment.
 Step 2: Using chemical vapor deposition (CVD) the thick silicon nitride(si3No4) layer is
deposited on the SIO2 layer.
 Step 3: A plasma etching process is used to make trenches for insulating the device from the
external environment.
 Step 4: These trenches are filled with Sio2 which is called the field oxide which insulates the
device.
 Step 5: Using the mechanical planarization process the sacrificial nitride layer and the pad
oxide are removed until the flat surface is on the layer.
 Step 6: To adjust the doping process the p-well areas are exposed with masks and later
annealing and implant are applied. This is followed by a second implant step to adjust the
threshold voltage of the NMOS transistor.
 Step 7: The implant step is performed to adjust the threshold voltage of the PMOS transistor.
 Step 8: The metal contacts are made at the positions and the grounds are connected which
prevents the device from high currents and voltages.
 Step 9: Ion implantation is carried out at the source and drain regions of PMOS (p+) and
NMOS (n+) transistors, this will also form the n+ polysilicon gate and p+ polysilicon gate for
NMOS and PMOS transistors respectively. This process is also known as the self-aligned
method.
 Step 10: Oxide and Nitride spacers are formed by the chemical vapor deposition.
 Step 11: Holes are etched, metal is deposited, and patterned. After the deposition of the last
metal layer final over-glass is deposited for protection.
 Significance of
P well

 Consumes low power: P-well CMOS transistors consume low power and operate efficiently.
 Less sensitive: P-well CMOS devices are low sensitive that is they can withstand high currents and
voltages
 Source to body not possible: Unlike n-well, the source to the body is not possible in p-well devices.
 Flexibility in manufacturing: P-well is mostly used CMOS type due to its flexibility in manufacturing.

2.What is An ASIC(Application Specific Integrated Circuit)?

ASIC full form is Application Specific Integrated Circuit. These circuits are application
specific .i.e. tailored made ICs for a particular application. These are usually designed from root level
based on the requirement of the particular application. Some of the basic application-specific
integrated circuit examples are chips used in toys, the chip used for interfacing of memory and
microprocessor etc…These chips can be used only for that one application for which these are
designed. Presumably, these types of ICs are preferred only for those products which have a large
production run. As ASICs are designed from the root level they have high cost and are recommended
only for high volume productions.
The main advantage of ASIC is reduced chip size as a large number of functional units of a circuit are
constructed over a single chip. Modern ASIC generally includes a 32-bit microprocessor, memory
blocks, network circuits etc…Such type of ASICs is known as System on Chip. With the
development in manufacturing technology and increased research in design methods, ASICs with
different levels of customization are developed.

Types of ASIC

ASICs are categorized based on the amount of customization a programmer is allowed to do on a

chip.

Ty
pes of ASICs

Full Custom

In this type of design all the logic cells are tailored made for specific application .i.e. designer has to
specially make the logic cells for the circuits. All the mask layers for interconnection are customized.
So programmer can’t change interconnections of the chip and while programming he has to be aware
of the circuit layout.

One of the best examples of Full custom ASIC is a microprocessor. This type of customization allows
designers to built various analog circuits, optimized memory cells, or mechanical structures on a
single IC. This ASIC is costly and very time consuming to manufacture and design. The time is taken
to design these ICs is around eight weeks.

These are usually intended for high-level applications. Maximum performance, minimized area and
highest degree of flexibility are major features of Full custom design. Eventually, the risk is high in
design as the logic cells, resistor etc… circuit elements used are not pretested.

Semi-Custom

In this type of design logic cells are taken from standard libraries .i.e. they are not handcrafted as in
Full custom design. Some masks are customized while some are taken from the predesigned library.
Based on the type of logic cells taken from the library and amount of customization allowed for
interconnects these ASICs are divided into two types- Standard cell-based ASIC and Gate Array-
based ASIC.
1). Standard cell-based ASIC

To know these IC first let us understand what a standard cell library stands for. Some of the logic
cells such as AND gates, OR gates, multiplexers, flip-flops are predesigned by designers using
different configurations, standardized and stored in the form of a library. This collection is known as
standard cell library.

Standard Cell-based
ASIC

In standard cell-based, ASIC logic cells from these standard libraries are used. On the ASIC chip
standard cell area or flexible block are made up of standard cells arranged in the form of rows. Along
with these flexible blocks mega cells like microcontrollers or even microprocessors are used on-chip.
These mega cells are also known as Mega functions, system level macros, fixed blocks, Functional
standard blocks.

Above figure represents a standard cell ASIC with a single standard cell area and four fixed blocks.
Mask layers are customized. Here designer can place standard cells anywhere on the die. These are
also known as C-BIC.

2). Gate Array Based ASIC

This type of semi-custom ASIC have predefined transistors on the silicon wafer .i.e. the designer
cannot change the placement of the transistors present on the die. Base array is the predefined pattern
of the gate array and the base cell is the smallest repetitive cell of the base array.

The designer only has liability to change interconnection between transistors using the first few metal
layers of the die. The designer chooses from the gate array library. These are often called as Masked
Gate Array. Gate Array Based ASIC are of three types. They are Channeled Gate Array, Channel less
gate array and a structured gate array.

a).Channeled Gate Array

In this type of gate array, wiring space is left between rows of transistors. These are similar to CBIC
as space is left for interconnection between blocks but in channeled gate array cell rows are fixed in
height whereas in CBIC this space can be adjusted.
Some of the main features of this gate array are- this gate array uses predefined spaces between rows
for interconnection. Manufacturing time is two days to two weeks.

b). Channel Less Gate Array

There is no free space left for routing between rows of cells as seen in the channeled gate array. Here
routing is done from above the gate array cells as we can customize the connection between the metal
1 and transistors. For routing, we leave the transistors lying in the path of routing unused. The
manufacturing lead time is about two weeks.

Channel Less Gate Array

c). Structured Gate Array

This type of gate array has an embedded block along with gate array rows as seen above. Structured
gate array has a higher area efficiency of CBIC. Like Masked gate array these have lower cost and
faster turnaround. Here the fixed size of the embedded function poses a limitation on the structured
gate array. For example, is this gate array contains an area reserved for 32k bit controller but if in an
application we only require an area for 16k bit controller the remaining area gets wasted.All the gate
array have a turnaround time of two days to two weeks and all have customized interconnect.

Structured Gate Array

Programmable ASIC

There are two types of programmable ASICs. They are PLD and FPGA

PLDs (Programmable Logic Devices)

These are the standard cells readily available. We can program a PLD to customized a part of the
application, so they are considered as ASIC. We can use different methods and software to program a
PLD. These contain a regular matrix of logic cells usually programmable array logic along with flip-
flops or latches. Here interconnects are present as a single large block.
PROM is a common example of this IC. EPROM uses MOS transistors as interconnect so by
applying high voltage we can program it. PLDs have no customized logic cells or interconnect. These
have a fast design turnaround.
 Programmable Logic
Devices

FPGAs (Field Programmable Gate Array)

Where PLDs have programmable array logic as logic cells FPGA has gate array-like arrangement.
PLDs are smaller and less complex than FPGAs. Due to its flexibility and characteristics, FPGA is
replacing TTL in microelectronic systems. Design turnaround is only a few hours.

Field Programmable Gate

Array

The core consists of programmable basic logic cells which can perform both combinational and
sequential logic. We can program logic cells and interconnect using some methods. Basic logic cells
are surrounded by the matrix of programmable interconnects and the core is surrounded by
programmable I/O cells.

FPGA usually comprises of configurable logic blocks, configurable I/O blocks, programmable
interconnects, clock circuitry, ALU, memory, decoders.

We have seen the different types of ASIC available. Now let’s understand when all these
customizations and interconnects are done during manufacturing.

Application Specific Integrated Circuit (ASIC) Design Flow

Designing an ASIC is carried out in step by step manner. This order of steps is known as ASIC
Design Flow. Steps of design flow are given in below flow chart.
 ASIC Design Flow

Design Entry: At this step, the microarchitecture of the design is implemented using hardware
description languages such as VHDL, Verilog and System Verilog.
Logic Synthesis: At this step a netlist of logic cells to be used, types of interconnections and all other
parts required for the application is prepared using HDL.
System Partitioning: At this step, we divide the largely sized die into ASIC sized pieces.
Pre-Layout Simulation: At this step, a simulation test is done to check whether the design contains
any errors.
Floor Planning: At this step blocks of netlist are arranged on the chip.
Placement: At this step location of cells inside the block is decided.
Routing: At this step, connections are drawn between blocks and cells. Extraction: At this step, we
determine the electrical properties like resistance value and the capacitance value of interconnect.
Post-Layout Simulation: Before the submission of the model for manufacturing this simulation is
done to check whether the system functions properly along with a load of interconnect.

Examples of ASIC

Having known the different characteristics of ASIC now let us see some examples of ASIC.
Standard cell-based ASIC: LCB 300k, 500k from LSI Logic Company, SIG1, 2, 3 families from
ABB Hafo Inc., GCS90K of GCS Plessey.
Gate Array Products: AUA20K from Harris Semiconductor, SCX6Bxx from National
Semiconductors, TGC/TEC families from Texas Instruments.
PLD Products: PAL family of Advanced Micro Devices, GAL family from Philips Semiconductors,
XC7300 and EPLD from XILINX.
FPGA Products: XC2000, XC3000, XC4000, XC5000 series from XILINX, pASIC1 of
QuickLogic, MAX5000 from Altera.

Applications of ASIC

The uniqueness of ASIC has revolutionized the way electronics are manufactured. These reduced the
die sizes while increasing the density of logic gates per chip. ASICs are usually preferred for high-
level applications. ASIC chip is used as IP cores for satellites, ROM manufacturing, Microcontroller
and various types of applications in the medical and research sectors. One of the trending applications
of ASIC is BITCOIN MINER.

Bitcoin Miner

Mining of cryptocurrency requires larger power and high-speed hardware. A general purpose CPU
cannot provide such a higher computing capacity at high speed. ASIC bitcoin miners are chips built
into specially designed motherboards and power supplies, constructed into a single unit. It is a
purposely designed hardware right down to the chip level for bitcoin mining. These units can execute
the algorithm of only single cryptocurrency. For a different type of cryptocurrency presumably, we
require another miner.

Advantages & Disadvantages of ASIC

The advantages of ASIC include the following.

 The small size of ASIC makes it a high choice for sophisticated larger systems.
o As a large number of circuits built over a single chip, this causes high-speed
applications.
o ASIC has low power consumption.
o As they are the system on the chip, circuits are present side by side. So, very minimal
routing is needed to connect various circuits.
o ASIC has no timing issues and post-production configuration.

The disadvantages of ASIC include the following.

o As these are customized chips they provide low flexibility for programming.
o As these chips have to be designed from the root level they are of high cost per unit.
o ASIC have larger time to market margin.

ASIC vs FPGA

The difference between ASIC and FPGA includes the following.

ASIC FPGA
Not reprogrammable Reprogrammable
Preferred for High volume productions Preferred for low volume productions
These are Application Specific Used as prototypes of a system
Energy Efficient requires less power Less energy efficient requires more power
Highly suitable for applications where the circuit has
These are permanent circuitry that can’t be upgraded
to be upgraded time to time such as cell phone chips,
from time to time.
Base stations etc

3. What is System on Chip?

SoC acronym for system on chip is an IC which integrates all the components into a single chip. It
may contain analog, digital, mixed signal and other radio frequency functions all lying on a single
chip substrate. Today, SoCs are very common in electronics industry due to its low power
consumption. Also, embedded system applications make great use of SoCs.
SoCs consists of:
  Control Unit: In SoCs, the major control units are microprocessors, microcontrollers, digital
signal processors etc.
 Memory Blocks: ROM, RAM. Flash memory and EEPROM are the basic memory units
inside a SoC chip.
 Timing Units: Oscillators and PLLs are the timing units of the System on chip.
 Other peripherals of the SoCs are counter timers, real-time timers and power on reset
generators.
 Analog interfaces, external interfaces, voltage regulators and power management units form
the basic interfaces of the SoCs.

SoC Structure: Design Flow

Design flow of SoC aims in the development of hardware and software of SoC designs. In general,
the design flow of SoCs consists of:

 Hardware and Software Modules: Hardware blocks of SoCs are developed from pre-qualified
hardware elements and software modules integrated using software development environment.
The hardware description languages like Verilog, VHDL and SystemC are being used for
the development of the modules.
 Functional Verification: The SoCs are verified for the logic correctness before it is being
given to the foundry.
 Verify hardware and software designs: For the verification and debug of hardware and
software of SoC designs, engineers have employed FPGA, simulation acceleration, emulation
and other technologies.
  Place and Route: After the debugging of the SoC, the next step is to place and route the entire
design to the integrated circuit before it is being given to the fabrication. In the fabrication
process, full custom, standard cell and FPGA technologies are commonly used.
Advantages of SoC

 Low power.
 Low cost.
 High reliability.
 Small form factor.
 High integration levels.
 Fast operation.
 Greater design.
 Small size.
Disadvantages of SoC
 Fabrication cost.
 Increased complexity.
 Time to market demands.
 More verification.
SoC Design Challenges
The different SoC design challenges are given below:
1. Architecture Strategy
2. Design for Test Strategy
3. Validation Strategy
4. Synthesis Backend Strategy
5. Integration Strategy
6. On chip Isolation
 Architecture Strategy
The kind of processor that we use to design the SoC is really an important factor to be considered.
Also, the kind of bus that has to be implemented is another matter of choice.
 Design for Test Strategy
Most of the common physical defects are modeled as faults here. While the necessary circuits
included in the SoC design help in checking the faults.
 Validation Strategy
Validation Strategy of SoC designs involves two major issues. First issue is that we have to verify the
IP cores. While the second issue is that we need to verify the integration of the system.
 Synthesis and Backend Strategy
There are many physical effects that have to be considered while designing the SoC synthesis and
strategy. Effects like IR drop, cross talk, 3D noise, antenna effects and EMI effects. Inorder to tackle
these issues, chip planning, power planning, DFT planning, clock planning, timing and area
budgeting is required in the early stage of the design.
 Integration Strategy
In the integration strategy, all the above listed facts have to be considered and assembled to bring out
a smooth strategy.
 On chip Isolation
In on chip isolation, many effects like impact of process technology, grounding effects, guard rings,
shielding and on- chip decoupling is to be considered.
Examples of SoCs
Most of the SoCs available in the market today are ARM based. Some examples among SoCs in
smartphone industry are Qualcomm's Snapdragon SoCs, Apple A4, and Nvidia Tegra series.
Raspberry Pi 2 comes with Broadcom BCM2836 SoC. Several SoCs have been developed by the
Open Cores community.
4.Design for Testability
Introduction:

Design for Test ("Design for Testability" or "DFT") is a name for design techniques that add
certain testability features to a microelectronic hardware product design. The premise of the
added features is that they make it easier to develop and apply manufacturing tests for the
designed hardware. In general, DFT is achieved by employing extra H/W.

The keys to designing circuits that are testable are controllability and observability.
 Controllability is the ability to set (to 1) and reset (to 0) every node internal to the
circuit.
 Observability is the ability to observe, either directly or indirectly, the state of any node
in the circuit.

Three main approaches to what is commonly called Design for Testability (DFT). These may be
categorized as follows:
a. Ad hoc testing
b. Scan-based approaches
c. Built-in self-test (BIST)

Ad Hoc Testing
Ad hoc test techniques, as their name suggests, are collections of ideas aimed at reducing the
combinational explosion of testing. They are summarized here for historical reasons. They are
only useful for small designs where scan, ATPG, and BIST are not available. A complete scan-
based testing methodology is recommended for all digital circuits.
The following are common techniques for ad hoc testing:
 Partitioning large sequential circuits
 Adding test points
 Adding multiplexers
 Providing for easy state reset
Partitioning large sequential circuits: Example-Counters

 Long Counters (8-bit) –Partitioned into two 4-bit counter to reduce the length of the
counter.
 This is achieved by having the test signal. This test signal block the data propagation at
every 4-bit boundary.
 16-test vectors exhaustively can test each 4-bit sections
 The data propagation between 4-bit sections may be tested with a few additional vectors.
Adding test points: Example-Bus in a bus-oriented systems

• Bus is used for the test purpose.

• Each register is loadable from the bus and capable of being driven onto the bus.
• Simple Example is Accumulator.
 • Internal logic values that exist on a data bus are enabled onto the bus for testing purposes.
• Inaccessible inputs are set and the outputs are observed via the bus.

Adding multiplexers

Frequently, multiplexers can be used to provide alternative signal paths during testing. In CMOS,
transmission gate multiplexers provide low area and delay overhead.
Design for Autonomous Test:

Providing for easy state reset

Any design should always have a method of resetting the internal state of the chip within a single
cycle or at most a few cycles. Apart from making testing easier, this also makes simulation faster
as a few cycles are required to initialize the chip.
Summary of Ad hoc Testing

• Used in bus in a bus-oriented systems

• Multiplexers are used to provide alternative signal paths during testing
• Have a method of resetting the internal state of the chip within a single cycle.
• Testing is easier and the simulation is faster because few cycles are required to initialize
the chip.
• Represent a bag of tricks to avoid the overhead of a systematic approach to testing.

Scan Design

Serial Scan

The scan-design strategy for testing has evolved to provide observability and controllability at
each register. In designs with scan, the registers operate in one of two modes.
  In normal mode, they behave as expected.
 In scan mode, they are connected to form a giant shift register called a scan chain
spanning the whole chip. By applying N clock pulses in scan mode, all N bits of state in
the system can be shifted out and new N bits of state can be shifted in.

Therefore, scan mode gives easy observability and controllability of every register in the system.
Modern scan is based on the use of scan registers, as shown in Figure 15.16. The scan register is
a D flip-flop preceded by a multiplexer. When the SCAN signal is deasserted, the register
behaves as a conventional register, storing data on the D input. When SCAN is asserted, the data
is loaded from the SI pin, which is connected in shift register fashion to the previous register Q
output in the scan chain.

For the circuit to load the scan chain, SCAN is asserted and CLK is pulsed eight times to load the
first two ranks of 4-bit registers with data. SCAN is deasserted and CLK is asserted for one cycle
to operate the circuit normally with predefined inputs. SCAN is then reasserted and CLK asserted
eight times to read the stored data out. At the same time, the new register contents can be shifted
in for the next test. Testing proceeds in this manner of serially clocking the data through the scan
register to the right point in the circuit, running a single system clock cycle and serially clocking
the data out for observation.

In this scheme, every input to the combinational block can be controlled and every output can be
observed. In addition, running a random pattern of 1s and 0s through the scan chain can test the
chain itself.
Test generation for this type of test architecture can be highly automated. ATPG techniques can
be used for the combinational blocks and, as mentioned, the scan chain is easily tested.
The prime disadvantage is the area and delay impact of the extra multiplexer in the scan
register. Designers (and managers alike) are in widespread agreement that this cost is more than
offset by the savings in debug time and production test cost.

Parallel Scan: Serial scan chains can become quite long, and the loading and unloading can
dominate testing time. A fairly simple idea is to split the chains into smaller segments. This can
be done on a module-by-module basis or completed automatically to some specified scan length.
Extending this to the limit yields an extension to serial scan called random access scan. To some
extent, this is similar to that used inside FPGAs to load and read the control RAM.

The basic idea is shown in Figure 15.17. The figure shows a two-by-two register section.
Each register receives a column (column<m>) and row (row<n>) access signal along with a row
data line (data<n>). A global write signal (write) is connected to all registers. By asserting the
row and column access signals in conjunction with the write signal, any register can be read or
written in exactly the same method as a conventional RAM. The notional logic is shown to the
right of the four registers. Implementing the logic required at the transistor level can reduce the
overhead for each register.

Scannable Register Design: An ordinary flip-flop can be made scannable by adding a

multiplexer on the data input, as shown in Figure 15.18(a). Figure 15.18(b) shows a circuit
design for such a scan register using a transmission-gate multiplexer.
The setup time increases by the delay of the extra transmission gate in series with the D input as
compared to the ordinary static flip-flop. Figure 15.18(c) shows a circuit using clock gating to
obtain nearly the same setup time as the ordinary flip-flop. In either design, if a clock enable is
used to stop the clock to unused portions of the chip, care must be taken that ф always toggles
during scan mode.
Built-In Self-Test (BIST)

Self-test and built-in test techniques, as their names suggest, rely on augmenting circuits to allow
them to perform operations upon themselves that prove correct operation. These techniques add
area to the chip for the test logic, but reduce the test time required and thus can lower the overall
system cost.
One method of testing a module is to use signature analysis or cyclic redundancy checking. This
involves using a pseudo-random sequence generator (PRSG) to produce the input signals for a
section of combinational circuitry and a signature analyzer to observe the output signals.

Pseudo-Random Sequence Generator (PRSG)

A PRSG of length n is constructed from a linear feedback shift register (LFSR), which in turn is
made of n flip-flops connected in a serial fashion, as shown in Figure 15.19(a). The XOR of
particular outputs are fed back to the input of the LFSR. An n-bit LFSR will cycle through 2n–1
states before repeating the sequence.
They are described by a characteristic polynomial indicating which bits are fed back. A
complete feedback shift register (CFSR), shown in Figure 15.19(b), includes the zero state that
may be required in some test situations. An n-bit LFSR is converted to an n-bit CFSR by adding
an n – 1 input NOR gate connected to all but the last bit. When in state 0…01, the next state is
0…00. When in state 0…00, the next state is 10…0. Otherwise, the sequence is the same.
Alternatively, the bottom n bits of an n + 1-bit LFSR can be used to cycle through the all zeros
state without the delay of the NOR gate.
A signature analyzer receives successive outputs of a combinational logic block and produces a
syndrome that is a function of these outputs. The syndrome is reset to 0, and then XORed with
the output on each cycle. The syndrome is swizzled each cycle so that a fault in one bit is
unlikely to cancel itself out. At the end of a test sequence, the LFSR contains the syndrome that
is a function of all previous outputs. This can be compared with the correct syndrome (derived
by running a test program on the good logic) to determine whether the circuit is good or bad. If
the syndrome contains enough bits, it is improbable that a defective circuit will produce the
correct syndrome.

BIST The combination of signature analysis and the scan technique creates a structure known as
BIST—for Built-In Self-Test or BILBO—for Built-In Logic Block Observation. The 3-bit BIST
register shown in Figure 15.20 is a scannable, resettable register that also can serve as a pattern
generator and signature analyzer.
C[1:0] specifies the mode of operation.
 In the reset mode (10), all the flip-flops are synchronously initialized to 0.
 In normal mode (11), the flip-flops behave normally with their D input and Q output.
 In scan mode (00), the flip-flops are configured as a 3-bit shift register between SI and
SO. Note that there is an inversion between each stage.
 In test mode (01), the register behaves as a pseudo-random sequence generator or
signature analyzer.
If all the D inputs are held low, the Q outputs loop through a pseudo-random bit sequence, which
can serve as the input to the combinational logic. If the D inputs are taken from the
combinational logic output, they are swizzled with the existing state to produce the syndrome.

In summary, BIST is performed by first resetting the syndrome in the output register. Then both
registers are placed in the test mode to produce the pseudo-random inputs and calculate the
syndrome. Finally, the syndrome is shifted out through the scan chain.
 Memory BIST On many chips, memories account for the majority of the transistors.
A robust testing methodology must be applied to provide reliable parts. In a typical MBIST
scheme, multiplexers are placed on the address, data, and control inputs for the memory to allow
direct access during test. During testing, a state machine uses these multiplexers to directly write
a checkerboard pattern of alternating 1s and 0s. The data is read back, checked, then the inverse
pattern is also applied and checked. ROM testing is even simpler: The contents are read out to a
signature analyzer to produce a syndrome.

Other On-Chip Test Strategies:

On-chip speeds are usually so high that directly observing internal behavior for testing can be
difficult or impossible. Designers have included on-chip logic analyzers and oscilloscopes to
deal with this problem. Such systems typically require a trigger signal to initiate data collection,
a high speed timing generator, analog or digital sampling, and a buffer to store the results until
they can be off-loaded at lower speed. A drawback is that the nodes to be observed must be
selected at design time, and these may not be the problem circuits. Nevertheless, probing major
busses and critical analog/RF nodes can be helpful.
Also, on-chip scopes have been used to characterize power supply noise and clock jitter.
Analog/digital converter testing requires real-time access to the digital output of the ADC.
Providing parallel digital test ports by reassigning pins on the chip I/O can facilitate this testing.
If this is impossible, a ―capture RAM‖ on chip can be used to capture results in real-time
and then the contents can be transferred off-chip at a slower rate for analysis.
If both ADCs and DACs are present, a loopback strategy can be employed, as shown in Figure
15.21. Both analog and digital signals can loop back. Communication and graphics systems
frequently have I/O systems that can be configured as shown. It is often worthwhile to add a
DAC and an ADC to a system to allow a level of analog self-test.
Providing on-chip debug circuitry involves quite a bit of imagination and forethought in terms of
what might go wrong. It is often called ―defensive design.‖ Today, transistor counts and
routing resources make it possible to include very sophisticated debug tools provided thought is
given to the matter.

2. IDDQ Testing
Bridging faults were introduced in Section 15.5.1.2. A method of testing for bridging faults is
called IDDQ test (VDD supply current Quiescent) or supply current monitoring [Acken83,
Lee92]. This relies on the fact that when a CMOS logic gate is not switching, it draws no DC
current (except for leakage). When a bridging fault occurs, then for some combination of input
conditions, a measurable DC IDD will flow. Testing consists of applying the normal vectors,
allowing the signals to settle, and then measuring IDD. As potentially only one gate is affected,
the IDDQ test has to be very sensitive. In addition, to be effective, any circuits that draw DC
power such as pseudo-nMOS gates or analog circuits have to be disabled. Dynamic gates can
also cause problems. As current measuring is slow, the tests must be run slower (of the order of 1
ms per vector) than normal, which increases the test time.
IDDQ testing can be completed externally to the chip by measuring the current drawn on the
VDD line or internally using specially constructed test circuits. This technique gives a form of
indirect massive observability at little circuit overhead. However, as subthreshold leakage
current increases, IDDQ testing ceases to be effective because variations in subthreshold leakage
exceed currents caused by the faults.

3. Design for Manufacturability

Circuits can be optimized for manufacturability to increase their yield. This can be done in a
number of different ways.
1 Physical At the physical level (i.e., mask level), the yield and hence manufacturability can be
improved by reducing the effect of process defects. The design rules for particular processes will
frequently have guidelines for improving yield. The following list is representative:
 Increase the spacing between wires where possible––this reduces the chance of a defect
causing a short circuit.
 Increase the overlap of layers around contacts and vias––this reduces the chance that a
misalignment will cause an aberration in the contact structure.
 Increase the number of vias at wire intersections beyond one if possible––this reduces the
chance of a defect causing an open circuit.
Increasingly, design tools are dealing with these kinds of optimizations automatically.
2 Redundancy Redundant structures can be used to compensate for defective components on a
chip. For example, memory arrays are commonly built with extra rows. During manufacturing
test, if one of the words is found to be defective, the memory can be reconfigured to access the
spare row instead. Laser-cut wires or electrically programmable fuses can be used for
configuration. Similarly, if the memory has many banks and one or more are found to be
defective, they can be disabled, possibly even under software control.
3 Power Elevated power can cause failure due to excess current in wires, which in turn can cause
metal migration failures. In addition, high-power devices raise the die temperature, degrading
device performance and, over time, causing device parameter shifts.
4 Process Spread Process simulations can be carried out at different process corners. Monte
Carlo analysis can provide better modeling for process spread and can help with centering a
design within the process variations.
5 Yield Analysis When a chip has poor yield or will be manufactured in high volume, dice that
fail manufacturing test can be taken to a laboratory for yield analysis to locate the root cause of
the failure. If particular structures are determined to have caused many of the failures, the layout
of the structures can be redesigned. For example, during volume production ramp-up for the
Pentium microprocessor, the silicide over long thin polysilicon lines was found to crack and raise
the wire resistance. This in turn led to slower-than-expected operation for the cracked chips. The
layout was modified to widen polysilicon wires or strap them with metal wherever possible,
boosting the yield at higher frequencies.

4. Boundary Scan (Board/System level testing)

Up to this point we have concentrated on the methods of testing individual chips. Many system
defects occur at the board level, including open or shorted printed circuit board traces and
incomplete solder joints. At the board level, ―bed-of-nails‖ testers historically were used to
test boards. In this type of a tester, the board-under-test is lowered onto a set of test points (nails)
that probe points of interest on the board. These can be sensed (the observable points) and driven
(the controllable points) to test the complete board. At the chassis level, software programs are
frequently used to test a complete board set. For instance, when a computer boots, it might run a
memory test on the installed memory to detect possible faults.

The increasing complexity of boards and the movement to technologies such as surface mount
technologies (with an absence of throughboard vias) resulted in system designers agreeing on a
unified scan-based methodology called boundary scan for testing chips at the board (and system)
level. Boundary scan was originally developed by the Joint Test Access Group and hence is
commonly referred to as JTAG. Boundary scan has become a popular standard interface for
controlling BIST features as well.
The IEEE 1149 boundary scan architecture is shown in Figure 15.22. All of the I/O pins of
each IC on the board are connected serially in a standardized scan chain accessed through
the Test Access Port (TAP) so that every pin can be observed and controlled remotely
through the scan chain. At the board level, ICs obeying the standard can be connected in
series to form a scan chain spanning the entire board. Connections between ICs are tested by
scanning values into the outputs of each chip and checking that those values are received at
the inputs of the chips they drive. Moreover, chips with internal scan chains and BIST can
access those features through boundary scan to provide a unified testing framework.