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Tuesday - Class Test - Memo

Digits

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13 views4 pages

Tuesday - Class Test - Memo

Digits

Uploaded by

Moalusi Ace
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Page 1 of 4

CLASS TEST

DATE: 27 September 2022 SESSION: 11:00

SUBJECT: CODE:
Digital Systems III EDS125A
STATIONERY:
1. Non-Alphanumeric Calculator
2. Pen and Ruler
3. Datasheet

Signature:
ASSESSOR: T. G. Bihi

STUDENT DETAILS: Question Marked Moderated


Student Number: ....................................................................... 1

Surname and Initials ....................................................................... 2

DECLARATION: I DECLARE THAT I WILL NOT IN ANY Total


WAY INFRINGE ON THE RULES OF ASSESSMENT.
Percentage
Signature: .......................................................................
INSTRUCTIONS:

Duration of paper: 50 minutes Maximum marks: 25

ANSWER ALL THE QUESTIONS.


THIS PAPER CONSISTS OF 6 PAGES.
Page 2 of 4

Question 1 [9]

1.1. Define the following: (4)


1.1.1. Bistable
----------------------------------------------------------------------------------------------------------------
Having two stable states. Latches and flip-flops are bistable multivibrators
----------------------------------------------------------------------------------------------------------------
1.1.2. Setup time
----------------------------------------------------------------------------------------------------------------
The time interval required for the input levels to be on a digital circuit
----------------------------------------------------------------------------------------------------------------
1.1.3. Clock
----------------------------------------------------------------------------------------------------------------
A triggering input of a flip-flop
----------------------------------------------------------------------------------------------------------------
1.1.4. FPGA
----------------------------------------------------------------------------------------------------------------
(Field Programmable Gate Array) are a more flexible arrangement than
CPLDs, with much larger capacity.
----------------------------------------------------------------------------------------------------------------
1.2. Sketch the simplified logic diagram of a positive edge-triggered J-K flip-flop: (5)

1.1. Sketch the simplified logic diagram of a positive edge-triggered J-K


flip-flop: (5)
Page 3 of 4

Question 2 [16]

2.1. Study the following truth table, and use the data, with the aid of Karnaugh Maps to
get a minimum SOP expression then show the expression on a PLA diagram:

A B C X Y
0 0 0 1 0
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 0 0
1 0 1 0 0
1 1 0 1 1
1 1 1 0 1
Karnaugh Map: (10)
X Y

C C
AB 0 1 AB 0 1
00 1 1 00 0 0
01 0 0 01 1 1
11 1 0 11 1 1
10 0 0 10 0 0
Page 4 of 4

----------------------------------------------------------------------------------------------------------------

X = A.B + A.B.C
------------------------------------------------------------------------------------------------------------

Y=B
----------------------------------------------------------------------------------------------------------------

PLA Diagram: (6)

*********************************END OF TEST*****************************

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