Republic of the Philippines

NUEVA VIZCAYA STATE UNIVERSITY

Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023

College of Engineering
Bambang Campus

DEGREE Bachelor of Science in COURSE NO. ECE9

PROGRAM Electronics Engineering
SPECIALIZATION Instrumentation & COURSE TITLE Logic Circuits and Switching Theory
Control
YEAR LEVEL 3rd Year TIME FRAME 18 hrs WK NO. 14-16 IM 04
NO.

I. UNIT TITLE/CHAPTER TITLE

Sequential Logic Circuits

II. LESSON TITLE

1. Introduction
2. Sequential Circuits
3. Synchronous Sequential Circuits
4. Storage Elements
5. Latches
6. Flip-Flops
7. Conversion From One Flip-Flop to Another
8. Analysis of Synchronous Sequential Circuits
9. Design Procedures

III. LESSON OVERVIEW

This lesson involves application of Boolean algebra, its minimization, and its logic gate implementation
into the design of sequential logic circuits.

IV. DESIRED LEARNING OUTCOMES

At the end of this lesson, the student should be able to:

1. Identify the functions of the different Sequential logic circuits

2. Analyze problems with the different logic circuits
3. Implement different sequential logic circuits
4. Design a functioning sequential logic circuit

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reproduced for educational purposes only and not for commercial distribution.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023
V. LESSON CONTENT

4-1 INTRODUCTION
The digital circuits considered thus far have been combinational—their output depends only and
immediately on their inputs—they have no memory, i.e., they are dependent on the current values of
their inputs.

Sequential circuits, however, act as storage elements and have memory. They can store, retain, and
then retrieve information when needed at a later time.

4-2 SEQUENTIAL CIRCUITS

A sequential circuit consists of a combinational circuit to which storage elements are connected to form
a feedback path. The storage elements are devices capable of storing binary information. The binary
information stored in these elements at any given time defines the state of the sequential circuit at that
time. The sequential circuit receives binary information from external inputs that, together with the
present state of the storage elements, determine the binary value of the outputs. These external inputs
also determine the condition for changing the state in the storage elements. The block diagram
demonstrates that the outputs in a sequential circuit are a function not only of the inputs, but also of the
present state of the storage elements. The next state of the storage elements is also a function of
external inputs and the present state. Thus, a sequential circuit is specified by a time sequence of
inputs, outputs, and internal states.

There are two (2) main types of sequential circuits, and their classification is a function of the timing of
their signals. A synchronous sequential circuit is a system whose behavior can be defined from the
knowledge of its signals at discrete instants of time. The behavior of an asynchronous sequential
circuit depends upon the input signals at any instant of time and the order in which the inputs change.

4-3 SYNCHRONOUS SEQUENTIAL CIRCUITS

A synchronous sequential circuit employs signals that affect the storage elements at only discrete
instants of time. Synchronization is achieved by a timing device called a clock generator, which
provides a clock signal having the form of a periodic train of clock pulses. The clock signal is
commonly denoted by the identifiers clock and clk.

- The inputs determine what changes will take place at the output.
- The clock pulse determines when computational activity will occur within the circuit (or when
changes will take place at the output)

Synchronous sequential circuits that use clock pulses to control storage elements are called clocked
sequential circuits and are the type most frequently encountered in practice.

4-4 STORAGE ELEMENTS

A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit), until directed by an input signal to switch states. The major differences among
various types of storage elements are in the number of inputs they possess and in the manner in which
the inputs affect the binary state.

- Storage elements that operate with “signal levels” are referred to as latches; while those
controlled by a “clock transition” are flip-flops.
- Latches are said to be level-sensitive devices; while flip-flops are edge-sensitive devices.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023
- Latches are useful for storing binary information and for the design of asynchronous sequential
circuits; while flip-flops are more practically used as storage elements in synchronous sequential
circuits.

4-5 LATCHES

SR Latch

- Shown above is an SR latch constructed with two (2) cross-coupled NOR gates (the NOR
latch).
- When output Q=1 and Q ' =0 , the latch is said to be in the set state.
- When Q=0 and Q ' =1, it is in the reset state.

Output Q and Q ' are normally the complement of each other. However, when both inputs are equal to
1 at the same time, a condition in which both outputs are equal to 0 (rather than be mutually
complementary) occurs. If both inputs are then switched to 0 simultaneously, the device will enter an
unpredictable or undefined state or a metastable state. Consequently, in practical applications, setting
both inputs to 1 is forbidden.

- Shown above is an SR latch with two (2) cross-coupled NAND gates (the NAND latch).
- It operates with both inputs normally at 1 unless the state of the latch has to be changed.
- The application of 0 to the S input causes output Q to go to 1, putting the latch in the set state.
- When the S input goes back to 1, the circuit remains in the set state.
- The application of 0 to the R input causes the circuit to go to the reset state and stay there even
after both inputs return to 1.

The condition that is forbidden for the NAND latch is both inputs being equal to 0 at the same time, an
input combination that should be avoided.

Because the NAND latch requires a 0 signal to change its state, it is sometimes referred to as an S' R '
latch. The primes (or, sometimes, bars over the letters) designate the fact that the inputs must be in
their complement form to activate the circuit.

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023

- Shown above is an SR latch with a control input.

- The control input En acts as an enable signal for the other two inputs.
- The outputs of the additional NAND gates stay at the logic-1 level as long as the enable signal
remains at 0. This is the quiescent condition for the SR latch.
- When the enable input goes to 1, information from the S or R input is allowed to affect the latch.
- The set state is reached with S=1, R=0, and En=1 (active-high enabled).
- To change to the reset state, the inputs must be S=0, R=1, and En=1.
- In either case, when En returns to 0, the circuit remains in its current state.
- The control input disables the circuit by applying 0 to En, so that the state of the output does not
change regardless of the values of S and R .

An indeterminate condition occurs when all three inputs are equal to 1. This condition places 0’s on
both inputs of the basic SR latch, which puts it in the undefined state.

D Latch (Transparent Latch)

One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure
that inputs S and R are never equal to 1 at the same time.

- Shown above is a D latch.

- This latch has only two (2) inputs: D (data) and En (enable).
- The D input goes directly to the S input, and its complement is applied to the R input.
- As long as the enable input is at 0, the cross-coupled SR latch has both inputs at the 1 level and
the circuit cannot change state regardless of the value of D.
- The D input is sampled when En=1.
- If D=1 , the Q output goes to 1, placing the circuit in the set state.
- If D=0, output Q goes to 0, placing the circuit in the reset state.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023

The graphic symbols for the various latches are shown above. A latch is designated by a rectangular
block with inputs on the left and outputs on the right. One output designates the normal output, and the
other (with the bubble designation) designates the complement output.

- The graphic symbol for the SR latch has inputs S and R indicated inside the block.
- In case of a NAND gate latch, bubbles are added to the inputs to indicate that setting and
resetting occur with a logic-0 signal.
- The graphic symbol for the D latch has inputs D and En indicated inside the block.

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023
4-6 FLIP-FLOPS

D Flip-Flop

The D latch with pulses in its control input is essentially a flip-flop that is triggered every time the pulse
goes to the logic-1 level. As long as the pulse remains at this level, any changes in the data input will
change the output and the state of the latch.

When latches are used for the storage elements, a serious difficulty arises. The state transitions of the
latches start as soon as the clock pulse changes to the logic-1 level. The new state of a latch appears
at the output while the pulse is still active. If the inputs applied to the latches change while the clock
pulse is still at the logic-1 level, the latches will respond to new values and a new output state may
occur. The result is an unpredictable situation since the state of the latches may keep changing for as
long as the clock pulse stays at the active level. Because of this unreliable operation, the output of a
latch cannot be applied directly or through combinational logic to the input of the same or another latch
when all the latches are triggered by a common clock source.

Flip-flop circuits are constructed in such a way as to make them operate properly when they are part of
a sequential circuit that employs a common clock.

The key to the proper operation of a flip-flop is to trigger it only during a signal transition. This can be
accomplished by eliminating the feedback path that is inherent in the operation of the sequential circuit
using latches. A clock pulse goes through two transitions: from 0 to 1 and the return from 1 to 0.

- Shown above is a diagram of the clock response in latch and flip-flop.

- A positive level response in the enable input allows changes in the output when the D input
changes while the clock pulse stays at logic 1.
- A positive-edge response allows changes in the output during the positive (rising) transition
of a clock pulse.
- A negative-edge response allows changes in the output during the negative (falling)
transition of a clock pulse.

There are two (2) ways that a latch can be modified to form a flip-flop.

Shown above is a master-slave flip-flop. It consists of two latches employed in a special configuration
that isolates the output of the flip-flop and prevents it from being affected while the input to the flip-flop
is changing.
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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
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- The first latch is called the master and the second the slave.
- The circuit samples the D input and changes its output Q only at the negative edge of the
synchronizing or controlling clock (designated as Clk).
- When the clock is 0, the output of the inverter is 1. The slave latch is enabled, and its output Q
is equal to the master output Y.
- The master latch is disabled when Clk =0.
- When the input pulse changes to the logic-1 level, the data from the external D input are
transferred to the master.
- The slave is disabled as long as the clock remains at the 1 level, because its enable input is
equal to 0. Any change in the input changes the master output at Y, but cannot affect the slave
output.
- Thus, a change in the output of the flip-flop can be triggered only by and during the transition of
the clock from 1 to 0.

The flip-flop shown above is a negative-edge-triggered D flip-flop because the output changes on the
negative edge of the clock. It is also possible to design the circuit so that the flip-flop output changes
on the positive edge of the clock. This happens in a flip-flop that has an additional inverter between the
Clk terminal and the junction between the other inverter and input En of the master latch. Such a flip-
flop is triggered with a negative pulse, so that the negative edge of the clock affects the master and the
positive edge affects the slave and the output terminal.

Another construction of an edge-triggered D flip-flop uses three SR latches as shown above. Two
latches respond to the external D (data) and Clk (clock) inputs. The third latch provides the outputs for
the flip-flop.

- The S and R inputs of the output latch are maintained at the logic-1 level when Clk =0. This
causes the output to remain in its present state.
- If D=0 when Clk becomes 1, R changes to 0. This causes the flip-flop to go to the reset state,
making Q=0.
- If there is a change in the D input while Clk =1, terminal R remains at 0 because Q is 0.
- When the clock returns to 0, R goes to 1, placing the output latch in the quiescent condition
without changing the output.
- Similarly, if D=1 when Clk goes from 0 to 1, S changes to 0. This causes the circuit to go to
the set state, making Q=1 .
- Any change in D while Clk =1 does not affect the output.

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023

The graphic symbol for the edge-triggered D flip-flop is shown above. It is similar to the symbol used
for the D latch, except for the arrowhead-like symbol in front of the Clk, designating a dynamic input.
The dynamic indicator (>) denotes the fact that the flip-flop responds to the edge transition of the clock.
A bubble outside the block adjacent to the dynamic indicator designates a negative edge for triggering
the circuit. The absence of a bubble designates a positive-edge response.

Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two (2) flip-flops
less widely used in the design of digital systems are the JK and T flip-flops.

The behavior of a D flip-flop is summarized in a characteristic table (or sometimes state or excitation
table) as shown below.

The characteristic equation (or sometimes state equation) of a D flip-flop is

Q ( t+1 ) =D

JK Flip-Flop

- The JK flip-flop constructed with a D flip-flop and gates is shown above, together with the
graphic symbol for the JK flip-flop.
- When J=1 and K=0, D=Q ' +Q=1, so the next clock edge sets the output to 1.
- When J=0 and K=1 , D=0, so the next clock edge resets the output to 0.
- When both J=K =1 and D=Q ', the next clock edge complements the output.
- When both J=K =0 and D=Q , the clock edge leaves the output unchanged.

The characteristic table of a JK flip-flop is shown below.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023

The characteristic equation of a JK flip-flop is

' '
Q ( t+1 ) =J Q + K Q

T Flip-Flop

The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs
J and K are tied together, as shown above (a).

- When T =0 ( J=K =0 ) , a clock edge does not change the output.

- When T =1 ( J =K =1 ), a clock edge complements the output.

The complementing flip-flop is useful for designing binary counters.

The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate as shown above (b). The
expression for the D input is
' '
D=T ⊕ Q=T Q +T Q

- When T =0 , D=Q and there is no change in the output.

- When T =1, D=Q ' and the output complements.

The graphic symbol for a T flip-flop is shown above (c) and the characteristic table of a T flip-flop is
shown below.

The characteristic equation of a T flip-flop is

' '
Q ( t+1 ) =T ⊕ Q=T Q +T Q

4-7 CONVERSION FROM ONE FLIP-FLOP TO ANOTHER

The following are the steps to make a given flip-flop function as another flip-flop:

1. Determine the excitation table of the desired flip-flop function.

Ex: Convert a D flip-flop into a JK flip-flop

Present Next
Inputs
State State

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023
J K Q Q ( t+1 )
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

- The excitation table of a JK flip-flop (the desired flip-flop) is shown above.

- If the present state at the output Q of a JK flip-flop is 0 and the inputs JK are 00 , then
the next state Q ( t+1 ) at the output will be 0 .
- If the present state at the output Q of a JK flip-flop is 1 and the inputs JK are 00 , then
the next state Q ( t+1 ) at the output will be 1.
- If the present state at the output Q of a JK flip-flop is 0 and the inputs JK are 01, then
the next state Q ( t+1 ) at the output will be 0 .
- If the present state at the output Q of a JK flip-flop is 1 and the inputs JK are 01, then
the next state Q ( t+1 ) at the output will be 0 .
- If the present state at the output Q of a JK flip-flop is 0 and the inputs JK are 10, then
the next state Q ( t+1 ) at the output will be 1.
- If the present state at the output Q of a JK flip-flop is 1 and the inputs JK are 10, then
the next state Q ( t+1 ) at the output will be 1.
- If the present state at the output Q of a JK flip-flop is 0 and the inputs JK are 11, then
the next state Q ( t+1 ) at the output will be 1.
- If the present state at the output Q of a JK flip-flop is 1 and the inputs JK are 11, then
the next state Q ( t+1 ) at the output will be 0 .

2. From the excitation table, determine the input of the given flip-flop that will function with the same
behavior as the desired flip-flop (i.e., the input that will convert the present state of the output to the
next state).
- For the excitation table in step 1, the input of a D flip-flop that will give a next state of 0 from
the present state of 0 is 0.
- From present state of 1 to next state of 1, D input should be 1.
- From 1 to 0, input should be 0.
- From 0 to 1, input should be 1.
- Write these inputs for D on an additional column to the right of the excitation table from step
1.

Inputs for Present Next Inputs for

Desired State State Given
Flip-Flop Flip-Flop
J K Q Q ( t+1 ) D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0

3. Extract the Boolean function that should be fed to the input of the given flip-flop using the present
state and the inputs of the desired flip-flop as its literals (or variables).
D KQ
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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
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00 01 11 10
0 0 1 0 0
J
1 1 1 0 1

' '
D=J Q + K Q

4. Connect the circuit. (The circuit connection for this example is shown in the topic for JK flip-flops
above.)

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023
Example 4.1 Convert a JK flip-flop into a D flip-flop.

Solution:
Step 1. Excitation table of D flip-flop (the desired flip-flop).
Present Next
Inputs
State State
D Q Q ( t+1 )
0 0 0
0 1 0
1 0 1
1 1 1

- If the present state at the output Q of a D flip-flop is 0 and the input D is 0 , then the next
state Q ( t+1 ) at the output will be 0 .
- If the present state at the output Q of a D flip-flop is 1 and the input D is 0 , then the next
state Q ( t+1 ) at the output will be 0 .
- If the present state at the output Q of a D flip-flop is 0 and the input D is 1, then the next
state Q ( t+1 ) at the output will be 1.
- If the present state at the output Q of a D flip-flop is 1 and the input D is 1, then the next
state Q ( t+1 ) at the output will be 1.

Step 2. Analyzing input for JK (the given flip-flop).

Present Next Inputs for
Inputs State State Given
Flip-Flop
D Q Q ( t+1 ) JK
0 0 0 0 X
0 1 0 X 1
1 0 1 1 X
1 1 1 X 0

- For a JK flip-flop to produce a next state Q ( t+1 ) of 0 from a present state Q ( t ) of 0 , the
inputs JK must be 00 (no change) or 01 (reset).
- For a JK flip-flop to produce a next state Q ( t+1 ) of 0 from a present state Q ( t ) of 1, the
inputs JK must be 01 (reset) or 11 (complement).
- For a JK flip-flop to produce a next state Q ( t+1 ) of 1 from a present state Q ( t ) of 0 , the
inputs JK must be 10 (set) or 11 (complement).
- For a JK flip-flop to produce a next state Q ( t+1 ) of 1 from a present state Q ( t ) of 1, the
inputs JK must be 00 (no change) or 10 (set).

Step 3. Extract Boolean functions for J and K.

J Q K Q
0 1 0 1

0 0 X 0 X 1
D D
1 1 X 1 X 0

J=D K=D
'

Step 4. Draw the circuit.

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023

4-8 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS

Analysis describes what a given circuit will do under certain operating conditions. The behavior of a
clocked sequential circuit is determined from the inputs, the outputs, and the state of its flip-flops. The
outputs and the next state are both a function of the inputs and the present state. The analysis of a
sequential circuit consists of obtaining a table or a diagram for the time sequence of inputs, outputs,
and internal states.

A logic diagram is recognized as a clocked sequential circuit if it includes flip-flops with clock inputs.
The flip-flops may be of any type, and the logic diagram may or may not include combinational logic
gate.

In analysis of sequential circuits, it is necessary to know how to obtain its state equations, and how to
draw up its state table and also its state diagram.

- A state equation (also called a transition equation) specifies the next state as a function of the
present state and inputs.
- A state table (sometimes called a transition table) includes the time sequence of inputs, outputs,
and flip-flop states.
- A state diagram is the graphical representation of the information available in a state table.

The following example demonstrates how the state equation, table, and diagram are drawn from a
given sequential circuit.

State Equations

Given the circuit below using two (2) D flip-flops, the state equations can be derived by labeling each
logic gate with its Boolean function.

The D input to flip-flop A is

D A =Ax + Bx
and the D input to flip-flop B is
DB = A ' x
From the characteristic equation of a D flip-flop,
Q ( t+1 ) =D
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INSTRUCTIONAL MODULE
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the state equations can be obtained as
A ( t+ 1 )=D A =Ax + BxB ( t+1 )=D B= A ' x
Also, the present-state value of the output can be obtained as
y= ( A +B ) x '

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NUEVA VIZCAYA STATE UNIVERSITY
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State Table

The state table consists of four (4) sections labeled present state, input, next state, and output.

- The present-state section shows the present state of flip-flops A and B.

- The input section gives a value of x for each possible present state.
- The next-state section shows the states of the flip-flops at time t+ 1. This section is the function
of the state equations.
- The output section gives the value of y for each present state and input condition.

Present Next
Input Output
State State
A B x AB y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

Another form of a state table is shown below.

For each present state, there are two possible next states and outputs, depending on the value of the
input. One form may be preferable to the other, depending on the application.

State Diagram

In this type of diagram, a state is represented by a circle, and the (clock-triggered) transitions between
states are indicated by directed lines connecting the circles. The state diagram provides the same
information as the state table and is obtained directly from either of the two (2) forms of state tables
above.

- The binary number inside each circle identifies the state of the flip-flops.
- The directed lines are labeled with two binary numbers separated by a slash.
o The input value during the present state is labeled first.
o The number after the slash gives the output during the present state with the given input.
- From a present state of 00 with an input value of x=0 , the next state is 00 with an output of
y=0. This is drawn on a state diagram by a directed line from circle 00 looped back toward 00
with label 0/0 (i.e., input 0 slash output 0).
- From a present state of 00 with an input value of 1, the next state is 01 with an output of y=0.
This is drawn on the state diagram by a directed line from circle 00 pointed toward circle 01 with
label 1/0 (i.e., input 1 slash output 0).
- From a present state of 01 with input 0, next state is 00 with output 1. A directed line is drawn
from circle 01 pointed toward 00 with label 0/1.

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- From a present state of 01 with input 1, next state is 11 with output 0. A directed line is drawn
from circle 01 pointed toward circle 11 with label 1/0.
- From a present state of 10 with input 0, next state is 00 with output 1. A directed line is draw
from circle 10 pointed toward circle 00 with label 0/1.
- From a present state of 10 with input 1, next state is 10 with output 0. A directed line is drawn
from circle 10 looped back toward 10 with label 1/0.
- From a present state of 11 with input 0, next state is 00 with output 1. A directed line is drawn
from circle 11 pointed toward circle 00 with label 0/1.
- Finally, from a present state of 11 with input 1, next state is 10 with output 0. A directed line is
drawn from circle 11 toward circle 10 with label 1/0.

The state diagram for this example is shown below.

4-9 DESIGN PROCEDURES

The design of a clocked sequential circuit starts from a set of specifications and culminates in a logic
diagram or a list of Boolean functions from which the logic diagram can be obtained. In contrast to a
combinational circuit, which is fully specified by a truth table, a sequential circuit requires a state table
for its specification.

A synchronous sequential circuit is made up of flip-flops and combinational gates. The design of the
circuit consists of choosing the flip-flops and then finding a combinational gate structure that, together
with the flip-flops, produces a circuit which fulfills the stated specifications.

The procedure for designing synchronous sequential circuits can be summarized by a list of
recommended steps:

1. From the word description and specifications of the desired operation, derive a state diagram for the
circuit.
2. Obtain the state table.
3. Choose the type of flip-flops to be used.
4. Determine the inputs for each flip-flop.
5. Derive the simplified flip-flop input equations and output equations.
6. Draw the logic diagram.

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 Republic of the Philippines
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INSTRUCTIONAL MODULE
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Example 4.2 Design a 3-bit binary counter that counts from 000 to 111 with every clock pulse, then
stops when it reaches 111, regardless of further clock pulses. Use three D flip-flops A ,
B and C .

Solution:
The state diagram for the specifications of the desired sequential circuit operation is shown
below.

- From 000 (decimal 0 ), it counts to 001 (decimal 1) after one clock pulse… then
transitions to 010 (decimal 2) after another clock pulse… and so on and so forth.
- When it reaches 111 (decimal 7 ), it remains to 111 despite any further clock pulse,
making it seem like it stopped counting.

The state table for the sequential circuit is as follows:

Present State Next State Flip-Flop Inputs

A B C A ( t+ 1 ) B ( t+1 ) C ( t +1 ) DA DB DC
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1

The state equations and flip-flop-

input equations can be extracted into
A ( t+ 1 )=D A =A + BC
' '
B ( t+1 )=D B=B C+ B C + AC= ( B ⊕ C )+ AC
'
C ( t +1 )=DC =AB+C

The logic diagram for the sequential

circuits is as shown.

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Example 4.3 A sequential circuit has two JK flip-flops A and B and one input x . The circuit is
described by the following flip-flop input equations:
J A =x K A =B J B =x ' K B= A'
(a) Derive the state equations A ( t+ 1 ) and B ( t+1 ) by substituting the input equations for
the J and K variables.
(b) Draw the state diagram of the circuit.

Solution:
The logic diagram for the sequential circuit is as shown below.

Remember that the characteristic equation for a JK flip-flop is

' '
Q ( t+1 ) =J Q + K Q
For flip-flop A , A ( t+ 1 ) will be
' '
A ( t+ 1 )=J A A + K A A ¿ x A ' + B' A¿ x A ' + A B'
For flip-flop B, B ( t+1 ) will be
' ' '
B ( t+1 )=J B B + K B B ¿ x ' B' + ( A ' ) B¿ x ' B' + AB
The state table is derived as follows

Present Next
Input
State State
A B x AB
0 0 0 0 1
0 0 1 1 0
0 1 0 0 0
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 1
1 1 1 0 1

- When the present state of the flip-flops AB is 00 and the input x is 0, the next state will
be A ( t+ 1 )=x A ' + A B' =( 0 ⋅0 ' ) + ( 0 ⋅0' )=( 0⋅1 )+ ( 0⋅1 )=0+0=0 and
B ( t+1 )=x ' B' + AB=( 0 ' ⋅0' ) + ( 0 ⋅0 )=( 1 ⋅1 ) +0=1+ 0=1.
- When the present state of the flip-flops AB is 00 and the input x is 1, the next state will
be 10.
- When the present state of the flip-flops AB is 01 and the input x is 0, the next state will
be 00.
- When the present state of the flip-flops AB is 01 and the input x is 1, the next state will
be 10.
- When the present state of the flip-flops AB is 10 and the input x is 0, the next state will
be 11.
- When the present state of the flip-flops AB is 10 and the input x is 1, the next state will
be 10.
- When the present state of the flip-flops AB is 11 and the input x is 0, the next state will
be 01.
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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023
- When the present state of the flip-flops AB is 11 and the input x is 1, the next state will
be 01.

The state diagram is as shown

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM04-ECE9-1S-2022-2023
VI. REFERENCES

Mano, M. (2016). Digital Design with an Introduction to the Verilog HDL (5th ed.). pp. 17-42
Singapore: Pearson Education South Asia. Retrieved from https://nitsri.ac.in/Department/Computer
%20Science%20&%20Engineering/digital_design-__morris_mano-fifth_edition.pdf
Petriu, E.M. Digital Logic Circuits.
Shannon, C.E. A Symbolic Analysis of Relay and Switching Circuits.

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