XTR115, XTR116

SBOS124B – JANUARY 2000 – REVISED JUNE 2023

XTR11x 4-20 mA Current-Loop Transmitters

1 Features 3 Description
• Low quiescent current: 200 μA The XTR115 and XTR116 (XTR11x) are precision
• 5-V regulator for external circuits current output converters designed to transmit analog
• VREF for sensor excitation: 4-mA-to-20-mA signals over an industry standard
– XTR115: 2.5 V current loop. These devices provide accurate current
– XTR116: 4.096 V scaling and output current limit functions.
• Low span error: 0.05% The on-chip voltage regulator (5 V) can be used
• Low nonlinearity error: 0.003% to power external circuitry. A precision on-chip VREF
• Wide loop supply range: 7.5 V to 36 V (2.5 V for the XTR115 and 4.096 V for the XTR116)
• SO-8 package can be used for offsetting or to excite transducers. A
2 Applications current return pin (IRET) senses any current used in
external circuitry to provide an accurate control of the
• 2-wire, 4-20-mA current loop output current.
• Transmitter
• Smart transmitter The XTR11x are a fundamental building block
• Industrial process control of smart sensors using 4-mA-to-20-mA current
• Test systems transmission.
• Compatible with HART modem The XTR11x are specified for operation over the
• Current amplifier extended industrial temperature range, –40°C to
• Voltage-to-current amplifier +85°C.
Device Information
PART NUMBER ON-CHIP VREF PACKAGE(1)
XTR115 2.5 V
D (SOIC, 8)
XTR116 4.096 V

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

XTR115
XTR116
VREG 5-V V+
5V
8 Regulator 7

XTR115: 2.5 V VREF Voltage

XTR116: 4.096 V 1 Reference

VLOOP
B
RIN
IIN 6
2 RL
+ A1

VIN E
– 5
RLIM
3
IRET 100 VIN
R1 R2 IO =
2.475 k 25
RIN

4
I = 100 • IIN

Typical Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
XTR115, XTR116
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Table of Contents
1 Features............................................................................1 7.3 Feature Description.....................................................8
2 Applications..................................................................... 1 8 Application and Implementation.................................... 9
3 Description.......................................................................1 8.1 Application Information............................................... 9
4 Revision History.............................................................. 2 9 Device and Documentation Support............................13
5 Pin Configuration and Functions...................................3 9.1 Device Support......................................................... 13
6 Specifications.................................................................. 4 9.2 Documentation Support............................................ 13
6.1 Absolute Maximum Ratings........................................ 4 9.3 Receiving Notification of Documentation Updates....13
6.2 Recommended Operating Conditions.........................4 9.4 Support Resources................................................... 13
6.3 Thermal Information....................................................4 9.5 Trademarks............................................................... 13
6.4 Electrical Characteristics.............................................5 9.6 Electrostatic Discharge Caution................................13
6.5 Typical Characteristics................................................ 6 9.7 Glossary....................................................................13
7 Detailed Description........................................................7 10 Mechanical, Packaging, and Orderable
7.1 Overview..................................................................... 7 Information.................................................................... 13
7.2 Functional Block Diagram........................................... 7

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2003) to Revision B (March 2022) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Added Pin Functions, ESD Ratings, Thermal Information, Recommended Operating Conditions, and
Electrical Characteristics tables, and Detailed Description, Overview, Functional Block Diagram, Feature
Description, Application and Implementation, Device and Documentation Support, and Mechanical,
Packaging, and Orderable Information sections.................................................................................................1
• Added Pin Functions table..................................................................................................................................3
• Changed operating temperature minimum value from –55°C to –40°C in Absolute Maximum Ratings ............4
• Deleted thermal resistance, θJA specification of 150 °C/W from Electrical Characteristics; added a Thermal
Information table, with RθJA = 128.2 °C/W and other detailed thermal parameters............................................4
• Changed span error test condition from: IIN = 250 µA to 25 mA to: IOUT = 250 µA to 25 mA in Electrical
Characteristics ................................................................................................................................................... 5
• Changed VREF voltage accuracy vs load typical value from ±100 ppm/mA to ±200 ppm/mA in Electrical
Characteristics ................................................................................................................................................... 5
• Changed bias current vs temperature typical value from 150 pA/°C to 300 pA/°C in Electrical Characteristics .
............................................................................................................................................................................5
• Changed Basic Circuit Connections application diagram................................................................................... 9
• Changed External Transistor applications information section to incorporate additional guidance regarding
transistor power dissipation and thermal concerns...........................................................................................10
• Added Circuit Stability application information section..................................................................................... 12

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5 Pin Configuration and Functions

VREF 1 8 VREG

IIN 2 7 V+

IRET 3 6 B (Base)

IO 4 5 E (Emitter)

Figure 5-1. D Package, SOIC-8 (Top View)

Table 5-1. Pin Functions

PIN
TYPE DESCRIPTION
NO. NAME
1 VREF Output Reference voltage output (2.5 V for XTR115, 4.096 V for XTR116)
2 IIN Input Current input pin
3 IRET Input Local ground return pin for VREG and VREF
4 IO Output Regulated 4-mA to 20-mA current-loop output
5 E (Emitter) Input Emitter connection for external transistor
6 B (Base) Output Base connection for external transistor
7 V+ Power Loop power supply
8 VREG Output 5-V regulator voltage output

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
V+ Power supply (referenced to IO pin) 40 V
Input voltage (referenced to IRET pin) 0 V+ V
Output current limit Continuous
VREG, short-circuit Continuous
VREF, short-circuit Continuous
TA Operating temperature –40 125 °C
TJ Junction temperature 165 °C
Tstg Storage temperature –55 125 °C
Lead temperature (soldering, 10 s) 300 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability.

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V+ Power supply voltage 7.5 24 36 V
TA Specified temperature –40 85 °C

6.3 Thermal Information

XTR11x
THERMAL METRIC(1) D (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 128.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 68.2 °C/W
RθJB Junction-to-board thermal resistance 75.7 °C/W
ψJT Junction-to-top characterization parameter 15.5 °C/W
ψJB Junction-to-board characterization parameter 74.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

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6.4 Electrical Characteristics

at TA = 25°C, V+ = 24 V, RIN = 20 kΩ, and TIP29C external transistor (unless otherwise noted)
XTR115U, XTR116U XTR115UA, XTR116UA
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
OUTPUT
IO Output current equation IO = IIN × 100 IO = IIN × 100
Output current, linear range 0.25 25 0.25 25 mA
ILIM Overscale limit 32 32 mA
IMIN Underscale limit IREG = 0, IREF = 0 0.2 0.25 0.2 0.25 mA
SPAN
S Span (current gain) 100 100 A/A
Error(1) IOUT = 250 mA to 25 mA ±0.05 ±0.2 ±0.05 ±0.4 %
vs Temperature TA = –40°C to +85°C ±3 ±20 ±3 ±20 ppm/°C
Nonlinearity IIN = 250 mA to 25 mA ±0.003 ±0.01 ±0.003 ±0.02 %
INPUT
VOS Offset voltage (op amp) IIN = 40 mA ±100 ±250 ±100 ±500 µV
vs Temperature TA = –40°C to +85°C ±0.7 ±3 ±0.7 ±6 µV/°C
vs Supply voltage, V+ V+ = 7.5 V to 36 V ±0.1 ±2 ±0.1 ±2 µV/V
IB Bias current –35 –35 nA
vs Temperature 300 300 pA/°C
en Noise: 0.1 Hz to 10 Hz 0.6 0.6 µVp-p
DYNAMIC RESPONSE
Small signal bandwidth CLOOP = 0, RL = 0 380 380 kHz
Slew rate 3.2 3.2 mA/µs
VREF (2)
XTR115 2.5 2.5 V
XTR116 4.096 4.096 V
Voltage accuracy IREF = 0 ±0.05 ±0.25 ±0.05 ±0.5 %
vs Temperature TA = –40°C to +85°C ±20 ±35 ±20 ±75 ppm/°C
vs Supply voltage, V+ V+ = 7.5 V to 36 V ±1 ±10 ±1 ±10 ppm/V
vs Load IREF = 0 mA to 2.5 mA ±200 ±200 ppm/mA
Noise 0.1 Hz to 10 Hz 10 10 µVp-p
Short-circuit current 16 16 mA
VREG (2)
Voltage 5 5 V
Voltage accuracy IREG = 0 ±0.05 ±0.1 ±0.05 ±0.1 V
vs Temperature TA = –40°C to +85°C ±0.1 ±0.1 mV/°C
vs Supply voltage, V+ V+ = 7.5 V to 36 V 1 1 mV/V
vs Output current See Typical Characteristics See Typical Characteristics
Short-circuit current 12 12 mA
POWER SUPPLY, V+
200 250 200 250 µA
Quiescent current
TA = –40°C to +85°C 240 300 240 300 µA

(1) Does not include initial error or TCR of RIN.

(2) Voltage measured with respect to IRET pin.

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6.5 Typical Characteristics

At TA = 25°C, V+ = 24 V, RIN = 20 kΩ, and TIP29C external transistor (unless otherwise noted)

260

40
240

Quiescent Current (µA)

(V+) = 36 V
Gain (dB)

30 COUT = 0 nF 220
RL = 0
(V+) = 24 V
200
COUT = 10 nF
RL = 250

20
(V+) = 7.5 V
180

10 160
10k 100k 1M –75 –50 –25 0 25 50 75 100 125
Frequency (Hz) Temperature (°C)

Figure 6-1. Current Gain vs Frequency Figure 6-2. Quiescent Current vs Temperature
0.1 34
With External Transistor
33
Reference Voltage (%)

Overscale Current (mA)

0
32
V+ = 36 V
–0.1 31
V+ = 7.5 V
30
–0.2 V+ = 24 V

29

–0.3 28
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

Figure 6-3. Reference Voltage vs Temperature Figure 6-4. Overscale Current vs Temperature
5.5
125°C

–55°C
VREG Voltage (V)

25°C –55°C
5.0
25°C

Sinking Sourcing
Current Current 125°C

4.5
–1 0 1 2 3 4
IREG Current (mA)

Figure 6-5. VREG Voltage vs VREG Current

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7 Detailed Description
7.1 Overview
The XTR115 and XTR116 are precision current output converters designed to transmit analog 4-mA-to-20-mA
signals over an industry standard current loop. The regulator and reference voltages power a sensor, such as a
bridge as shown in Figure 7-1. The sensor output, as a current signal IIN, is gained up and transmitted over the
loop to be read by a receiver.

EXTERNAL SENSOR XTR11x EXTERNAL RECEIVER

VREF V+ //

VREG

LDO

B C1
+
IIN Q1 VLOAD
– +
ADC VLOOP
E –

RLOAD
IRET IO //

GND
All sensor-side current must XTR11x acts as transmitter For long wire runs RPARASITIC Receiver measures VLOAD
return through IRET IO = 100 • IIN will contribute to RLOAD VLOAD = RLOAD • IOUT

Figure 7-1. Typical Schematic

7.2 Functional Block Diagram

EXTERNAL XTR11x EXTERNAL

RECEIVER & SENSOR
LOOP SUPPLY V+ VREG
5V Regulator
Sensor Local
Power
2.5V Reference (referenced
VREF
+ (XTR115) to IRET)
VLOOP
– 4.096V Reference
(XTR116)

IO IIN RIN

G = 100 Current Gain

+
VLOAD RLOAD Circuit and 4-20 mA Loop VSENSOR
Regulator IRET –

E B

VLOAD = RLOAD • IO External

= RLOAD • IIN • 100 transistor Q1
= RLOAD • VSENSOR / RIN • 100 (recommended)

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7.3 Feature Description

7.3.1 Reverse-Voltage Protection
The XTR11x low compliance voltage rating (7.5 V) permits the use of various voltage protection methods without
compromising the operating range. Figure 7-2 shows a diode bridge circuit that allows normal operation even
when the voltage connection lines are reversed. The bridge causes a two-diode drop (approximately 1.4 V) loss
in loop supply voltage. This loss results in a compliance voltage of approximately 9 V—satisfactory for most
applications. A diode can be inserted in series with the loop supply voltage and the V+ pin to protect against
reverse output connection lines with only a 0.7-V loss in loop supply voltage.

8 V+ Maximum VPS must be

VREG 7 less than minimum voltage
1 rating of Zener diode.
VREF

RIN
2 XTR115 6 0.01 µF
IIN B Q1 (1) 1N4148
XTR116 D1 Diodes

VIN E
5 RL VPS
3
IRET IO The diode bridge causes a
4 1.4-V loss in loop supply voltage.

(1) Zener Diode 36 V: 1N4753A or Motorola P6KE39A. Use lower-voltage Zener diodes with loop power-supply voltages less than 30 V
for increased protection; see Section 7.3.2.

Figure 7-2. Reverse Voltage Operation and Overvoltage Surge Protection

7.3.2 Overvoltage Surge Protection

Remote connections to current transmitters can sometimes be subjected to voltage surges. Best practice is to
limit the maximum surge voltage applied to the XTR11x to as low as practical. Various Zener and surge clamping
diodes are specially designed for this purpose. Select a clamp diode with as low a voltage rating as possible
for best protection. For example, a 36-V protection diode provides proper transmitter operation at normal loop
voltages, and also provides an appropriate level of protection against voltage surges. Characterization tests on
several production lots showed no damage with loop supply voltages up to 65 V.
Most surge protection Zener diodes have a diode characteristic in the forward direction that conducts excessive
current, possibly damaging receiving-side circuitry if the loop connections are reversed. If a surge protection
diode is used, also use a series diode or diode bridge for protection against reversed connections.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The XTR115 and XTR116 are identical devices except for the reference voltage output, pin 1. This voltage is
available for external circuitry and is not used internally. Further discussions that apply to both devices refer to
the XTR11x.
Figure 8-1 shows basic circuit connections with representative simplified input circuitry. The XTR11x is a two-
wire current transmitter. The device input signal (pin 2) controls the output current. A portion of this current flows
into the V+ power supply, pin 7. The remaining current flows in Q1. External input circuitry connected to the
XTR11x can be powered from VREG or VREF. Current drawn from these terminals must be returned to IRET, pin
3. This IRET pin is a local ground for input circuitry driving the XTR11x.
XTR115
IREG XTR116 IO
5V VREG 5-V V+
XTR115: 2.5 V 8 Regulator 7
XTR116: 4.096 V
IREF
VREF(1) Voltage
1 Reference

VLOOP
RIN B
VIN 20 k
IIN
IIN Q1 10 nF
Input 6
Circuitry 2
A1 RL

E
5
3 RLIM

IRET
All return current R1 R2
from IREG and IREF 2.475 k 25 
IO
4
For IO = 4 mA to 20 mA I = 100 × IIN
IIN = 40 µA to 200 µA
Possible choices for Q1(2)
With RIN = 20 k
VIN = 0.8 V to 4 V TYPE PACKAGE
2N4922G TO-126
FCX690BTA SOT-89-3
MMBTA28-7-F SOT-23-3

(1) Also see Figure 8-4.

(2) See Section 8.1.1.

Figure 8-1. Basic Circuit Connections

The XTR11x is a current-input device with a gain of 100. A current flowing into pin 2 produces IO = 100 • IIN.
The input voltage at the IIN pin is zero (referred to the IRET pin). A voltage input is created with an external input
resistor, as shown. Common full-scale input voltages range from 1 V and upward. Full-scale inputs greater than
0.5 V are recommended to minimize the effect of offset voltage and drift of A1.

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8.1.1 External Transistor

The external transistor, Q1, conducts the majority of the full-scale output current. Power dissipation in this
transistor can approach 0.8 W with high loop voltage (40 V) and 20 mA of output current. The XTR11x is
designed to use an external transistor to avoid on-chip, thermal-induced errors. Heat produced by Q1 still
causes ambient temperature changes that can affect the XTR11x. To minimize these effects, locate Q1 away
from sensitive analog circuitry, including the XTR11x. Mount Q1 so that heat is conducted to the outside of the
transducer housing and away from the XTR11x.
The XTR11x is designed to use virtually any NPN transistor with sufficient voltage, current, and power rating.
Case style and thermal mounting considerations often influence the choice for any given application. Several
possible choices are listed in Figure 8-1. A MOSFET transistor does not improve the accuracy of the XTR11x
and is not recommended. Although the XTR11x can be used without an additional external transistor, this
configuration is not always practical at higher loop voltages and currents because of self-heating concerns.
8.1.2 Minimum Scale Current
The quiescent current of the XTR11x (typically 200 μA) is the lower limit of the device output current. Zero input
current (IIN = 0 A) produces an IO equal to the quiescent current. Output current does not begin to increase until
IIN > IQ / 100. Current drawn from VREF or VREG adds to this minimum output current. This means that more than
3.7 mA is available to power external circuitry while still allowing the output current to go below 4 mA.
8.1.3 Offsetting the Input
A low scale of 4 mA is produced by creating a 40-μA input current. This low-scale offset can be created with the
proper value resistor from VREF (as shown in Figure 8-2, or by generating offset in the input drive circuitry.

XTR115

VREG

2.5 V VREF Voltage

40 µA Reference

R0
62.5 k

IIN

A1
0 µA to 160 µA

IRET
R1
2.475 k

Figure 8-2. Creating Low-Scale Offset

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8.1.4 Maximum Output Current

The XTR11x provide accurate, linear output up to 25 mA. Internal circuitry limits the output current to
approximately 32 mA to protect the transmitter and loop power or measurement circuitry.
Extending the output current range of the XTR11x is possible by connecting an external resistor from pin 3 to pin
5 to change the current limit value.

CAUTION
All output current must flow through internal resistors; therefore, damage is possible with excessive
current. Output currents greater than 45 mA can cause permanent damage.

VREG XTR115
XTR116

VREF

RIN
VO
D/A

VREG XTR115
XTR116

VREF

Digital IO IIN
Control D/A
Optical IRET
Isolation

5V VREG XTR115
XTR116

Filter RIN
Digital PWM
Control
µC Out

Optical
Isolation IRET

Figure 8-3. Digital Control Methods

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8.1.5 Radio Frequency Interference

The long wire lengths of current loops invite radio frequency interference (RF). RF can be rectified by the
input circuitry of the XTR11x or preceding circuitry. This RF generally appears as an unstable output current
that varies with the position of loop supply or input wiring. Interference can also enter at the input pins. For
integrated transmitter assemblies with short connection to the sensor, the interference more likely comes from
the current-loop connections.
8.1.6 Circuit Stability
The 4-20 mA control-loop stability must be evaluated for any XTR11x design. A 10‑nF decoupling capacitor
between V+ and IO is recommended for most applications. As this capacitance appears in parallel with the load
resistance RLOAD from a stability perspective, the capacitor and resistor form a filter corner that can limit the
bandwidth of the system. Therefore, for HART applications, use a bypass capacitance of 2 nF to 3 nF instead.
For applications with EMI and EMC concerns, use a bypass capacitor with sufficiently low ESR to decouple
any ripple voltage from the VLOOP supply. Otherwise, the ripple voltage couples onto the 4‑mA to 20‑mA current
source, and appears as noise across RLOAD after the current-to-voltage conversion.
Additionally, stability concerns apply to the VREF reference buffer when driving capacitive loads. Figure 8-4
shows that two filtering capacitors are required, one CHF of 10 pF to 0.5 µF and another CLF of 2.2 µF to 22 µF.
Either a series isolation resistance RISO or a snubber RCOMP is used, depending on application requirements.
If capacitive loading must be placed on the VREF pin, use one of the following compensation schemes to maintain stable operation.
Values of capacitance must remain within the given ranges.

XTR115
RISO(1)
10 XTR116 IO
VREG 5-V V+
8 Regulator 7
ILOAD CHF + CLF
(0 mA to (10 pF to 0.5 µF) (2.2 µF to 22 µF)
2.5 mA) VREF Voltage
1 Reference

VLOOP
OR
B
IIN 6
2 RL
A1

E
+ CLF(1) 5
(2.2 µF to 22 µF) RLIM
3
ILOAD CHF
(10 pF to 0.5 µF) IRET
(0 mA to R1 R2 100 VIN
2.5 mA) RCOMP(1) 2.475 k
25  IO
50  RIN
4
I = 100 × IIN

(1) Required compensation components.

Figure 8-4. Stable Operation With Capacitive Load on VREF

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9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Device Support
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Special Function Amplifiers: TI Precision Labs introduction video on Current Loop
Transmitters
• Texas Instruments, TIPD190 2-wire, 4-20mA Transmitter, EMC/EMI Tested Reference Design with the
XTR116
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

XTR115U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 85 XTR Samples
115U
XTR115UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 XTR Samples
115U
A
XTR116U LIFEBUY SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 XTR
116U
XTR116U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 85 XTR Samples
116U
XTR116UA LIFEBUY SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 XTR
116U
A
XTR116UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 XTR Samples
116U
A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 16-Feb-2024

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Feb-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
XTR115U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
XTR115U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
XTR115UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
XTR115UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
XTR116U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
XTR116U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
XTR116UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
XTR116UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
XTR115U/2K5 SOIC D 8 2500 356.0 356.0 35.0
XTR115U/2K5 SOIC D 8 2500 356.0 356.0 35.0
XTR115UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
XTR115UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
XTR116U/2K5 SOIC D 8 2500 353.0 353.0 32.0
XTR116U/2K5 SOIC D 8 2500 356.0 356.0 35.0
XTR116UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
XTR116UA/2K5 SOIC D 8 2500 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Feb-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
XTR116U D SOIC 8 75 506.6 8 3940 4.32
XTR116UA D SOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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