PCI 2.

3 Update

PCI 2.3 Update Document

This document details the changes between the 2.2 and 2.3 version of the PCI
specification. The 2.3 specification changes fall into the following categories:

• Support added for System Management Bus (SM Bus)

• Removed support for 5volt only Add-In cards.
• The purpose and function of Stepping was clarified in the 2.3 specification
as reflected by the change in name from "Address/Data Stepping" to
"IDSEL stepping."
• New Reset timing parameter added.
• Added new "low profile" PCI Add-In card form factor.
• New bit fields added to registers in configuration address space.

This document is intended to be an addendum to MindShare’s PCI System

Architecture book, 4th edition, based on the 2.2 version of the PCI specification.
The document is organized in order of occurrence of changes that are associated
with the book and the 2.3 specification. The changes described in this document
are incorporated into a 5th edition book available only in electronic form. This
5th edition book is in pdf format and can be purchased at http://www.mind-
share.com/books/books_main.html. This electronic edition of the book also
incorporates the 4th edition errata and ECNs that include:

Table 1: Summary of 2.2 Specification ECNs

ECN Description

SMBus Adds a two wire management interface to the PCI

connector.

Reset Timing Adds a new timing requirement from power valid to

reset deassertion.

Low Profile Add-in Card Adds the Low Profile add-in card form factor.
Add-in Card Trace Extends the low end of the add-in card trace
Impedance impedance.

Add-in Card Keying Deletes 5 volt only keyed add-in card support.

Class Codes Updates specification to include new Class Codes.

Capability IDs Updates specification to include new Capability IDs.

1
PCI System Architecture

About This Book

The section entitled "Designation of Specification Changes" on page 3, is
updated to reflect the new 2.3 specification dated 3/29/02, which includes the
errata from document (file pci2_2_errata102499.pdf).

Chapter 1: Intro To PCI

Table 1-1 is extended to include new features supported by PCI. The new entries
include:.

Table 1-1: New PCI 2.3 Features

Feature Description

SM BUS SUPPORT FOR A SYSTEM MANAGEMENT BUS PROVIDES THE ABILITY TO

MANAGE A VARIETY OF FEATURES.

Add-In Card Size The specification defines three card sizes: long, short and vari-
able-height short cards, AND NEW LOW-PROFILE ADD-IN CARDS.
ADD-IN CARD COM- THE PCI SPEC AND PCI-X ADDENDUM DEFINE CARDS THAT OPERATE
PATIBILITY AT DIFFERENT SPEEDS AND WITH DIFFERENT PROTOCOLS. ALL 3.3 ADD-
IN CARDS AND COMPONENTS INCLUDING PCI 33 MHZ, PCI 66
MHZ, PCI-X 66 MHZ, AND PCI-X 133 MHZ ARE DESIGNED TO
FUNCTION IN A PCI 33 MHZ SYSTEM. NOTE HOWEVER, THAT SOME
CARDS AND COMPONENTS REQUIRE 3.3 VOLTS BUS OPERATION.

The contact information specified at the bottom of Page 13 for obtaining the
specification has changed:

PCI SPECIAL INTEREST GROUP

5440 SW WESTGATE DRIVE
SUITE 217
PORTLAND, OREGON 97221
PHONE: 800-433-5177 (INSIDE THE U.S.)
503-291-2569 (OUTSIDE THE U.S.)
FAX: 303-297-1090
E-MAIL: [email protected]
HTTP://WWW.PCISIG.COM

2
 PCI 2.3 Update

Chapter 3: Reflected-Wave
Switching
The section on RST#/REQ64# Timing on page 29 of the 4th edition has been
rewritten and expanded. A timing diagram has been added to illustrate the tim-
ing relationships between power, clock, and reset. Also, the definition of Tfail
has been added to the discussion and timing diagram.

The only change to this section that is brought about by the 2.3 specification is a
new parameter defined as "power valid to reset high" timing (Tpvrh). The dis-
cussion of this parameter is highlighted in red below and is illustrated in figure
3-5.

RST#/REQ64# Timing
The assertion and deassertion of RST# is asynchronous to the PCI clock signal,
however, the specification also permits synchronous reset. The following list
describes the timing relationships between power, clock, and reset and illus-
trated in Figure 3-5 on page 4.
• The specification requires that RST# be asserted as early as possible during
the power-up sequence. Figure 3-5 on page 4 illustrates RST# going active
following the assertion of PWR_GOOD.
• Once asserted, RST# must remain asserted for a minimum of 1ms after the
power has stabilized (Trst).
• RST# must remain asserted for a minimum of 100 microseconds after the
CLK has stabilized (Trst-clk).
• DURING THE FIRST RESET SEQUENCE (I.E. POWER-UP), RST# MUST REMAIN ASSERTED
FOR 100MS FROM POWER VALID (TPVRH). NOTE THAT IF RST# IS ASSERTED WHILE THE 2.3
POWER SUPPLY VOLTAGES REMAIN WITHIN THEIR SPECIFIED LIMITS (E.G. A SOFTWARE
RESET), THE MINIMUM PULSE WIDTH OF RST# IS TRST.
• When RST# is asserted, all devices must float their output drivers within a
maximum of 40ns. A device is not considered reset until Trst and Trst-clk
have been satisfied.
• During assertion of RST#, the system board reset logic must assert REQ64#
for a minimum of 10 clock cycles (Trrsu). REQ64# may remain asserted for a
maximum of 50ns after RST# is deasserted (Trrh). For a discussion of
REQ64# assertion during reset, refer to “64-bit Cards in 32-bit Add-in Con-
nectors” on page 268.

3
 PCI System Architecture

• If power goes out of specification on either or both power rails, the system
will re-assert RST#. This forces all devices to float their outputs to protect
against possible parasitic currents short circuiting the output drivers. The
time from detecting "power fail" to assertion of RST# (Tfail) depends on the
power fail condition as follows:
- 500ns (max.) if either power rail goes out of tolerance by more than
500mV.
- 100ns (max.) if the 5V rail falls below the 3.3V rail by more than 300mV.

2.3 Figure 3-5: Power, Clock, and Reset Timing

Power
Power Valid Power Fail
Tfail
(See text)

PCI_Clk

Power Stable
PWR_GOOD

Trst
RST# (1ms min.)

Trst-clk
(100µs min.)

REQ64#
Trrsu Trrh
(10*Tcyc min.) (0-50ns)
Tpvrh
(100ms min.)

4
 PCI 2.3 Update

Chapter 4: The Signal Groups

The 2.3 PCI specification adds support for the System Management (SM) Bus.
Two new pins were added for this support. The changes made to the 5th edition
ebook include:

• Figures 4-1 and 4-2 now include the SM Bus interface signals.
• A new section on the SM Bus interface has also been added
• The section on Snoop Support Signals has been removed.
• Table 4-7 now includes the SM Bus signals.

Figure 4-1: PCI-Compliant Master Device Signals

2.3
Required Optional
Signals Signals

Address/Data
and Command
64-Bit
PAR64 Extension
PAR
REQ64#
FRAME# ACK64#
TRDY#
CLKRUN# Clock Control
Interface IRDY#
PME#
Control STOP#
DEVSEL#
3.3Vaux } Power Management
(added in 2.2)

}System Management
SMBDAT
SMBCLK Bus
TDI
REQ# TDO
Arbitration JTAG
GNT# TCK (IEEE
CLK TMS 1149.1)
System RST# TRST#
PERR# INTA#
Error
Reporting SERR# INTB#
INTC# Interrupt
Request
INTD#

5
 PCI System Architecture

2.3 Figure 4-2: PCI-Compliant Target Device Signals

Required Optional
Signals Signals

Address/Data
and Command 64-Bit
Extension
PAR PAR64
REQ64#
FRAME# ACK64#
TRDY# CLKRUN# Clock Control
IRDY#
}
PME# Power Management
Interface STOP#
Control 3.3Vaux (added in 2.2)
DEVSEL#
}System Management
SMBDAT
IDSEL SMBCLK Bus
TDI
TDO
CLK JTAG
TCK
System RST# (IEEE
TMS 1149.1)
TRST#
Error PERR#
Reporting SERR# INTA#
INTB#
Interrupt
INTC# Request
INTD#

6
 PCI 2.3 Update

System Management Bus Interface 2.3

TABLE 4-4 PROVIDES A BRIEF DESCRIPTION OF THE SYSTEM MANAGEMENT BUS INTERFACE
SIGNALS.

TABLE 4-4: SYSTEM MANAGEMENT BUS INTERFACE SIGNALS

SIGNAL DESCRIPTION

SMBCLK. THIS SIGNAL IS AN OPTIONAL SMBUS INTERFACE CLOCK SIGNAL. THIS

SIGNAL IS DRIVEN BY AN SM BUS MASTER WHEN IT WANTS TO SEND DATA TO OR
RECEIVE DATA FROM AN SM BUS SLAVE. THE SM BUS SPECIFICATION ALSO SUP-
PORTS THE POSSIBILITY OF MULTIPLE MASTERS DRIVING THE CLOCK SIMULTA-
SMBCLK
NEOUSLY AND AN ASSOCIATED ARBITRATION MECHANISM THAT EMPLOYS
SMBDAT. THE CLOCK FREQUENCY RANGE PERMITTED IS 10KHZ - 100KHZ. SM
BUS PROVIDES A CLOCK SYNCHRONIZATION THAT ALLOWS DEVICES OPERATING
AT DIFFERENT SPEEDS TO CO-EXIST ON THE BUS.

SMBDAT. THIS SIGNAL IS DRIVEN BY A MASTER WHEN INITIATING A TRANSACTION

TO DELIVER THE SLAVE ADDRESS AND COMMAND. SUBSEQUENTLY, SMBDAT
SMBDAT
CARRIES DATA TO OR FROM A SLAVE DEVICE. SMBDAT IS ALSO USED AS PART OF
THE ARBITRATION MECHANISM

THE SM BUS INTERFACE IS SPECIFIED IN THE 2.0 VERSION OF THE SM BUS SPECIFICATION.
THIS 2.0 SPECIFICATION ADDS HIGH POWER CHARACTERISTICS THAT PERMITS SM DEVICES
TO OPERATE IN THE PCI BUS ENVIRONMENT. EARLIER VERSIONS OF THE SM BUS SPECIFICA-
TION SUPPORTED ONLY LOWER POWER ENVIRONMENTS (E.G. SMART BATTERIES).

Cache Support (Snoop Result) Signals

This section is removed from the 5th edition e-book. Support for the PCI snoop
result signals and all related topics were eliminated in the 2.2 spec. The descrip-
tion of Cache support was left is the 4th edition book as a historical reference.

7
 PCI System Architecture

2.3 Signal Types

TABLE 4-7 HAS BEEN UPDATED TO REFLECT THE SMBCLK AND SMBDAT SIGNALS AS
SHOWN BELOW.

Table 4-7: PCI Signal Types

Signal(s) Type Note

SMBCLK PULLED UP ON SYSTEM BOARD.ADDED IN

O/D
THE 2.3 SPECIFICATION.
SMBDAT

2.3 Chapter11: Fast Back-to-Back &

IDSEL Stepping
IDSEL Stepping
THE 2.3 SPECIFICATION HAS RENAMED ADDRESS/DATA STEPPING TO IDSEL STEPPING.
THE NAME CHANGE DENOTES USE OF STEPPING ONLY FOR TYPE ZERO CONFIGURATION
TRANSACTIONS. SPECIFICALLY, 2.3 PERMITS THE USE OF STEPPING ON IDSEL PINS WHEN
THEY ARE DRIVEN VIA AD SIGNALS THROUGH RESISTIVELY-COUPLED CONNECTIONS.

IDSEL STEPPING PERMITS THE AD BUS, WHICH CARRIES THE IDSEL INFORMATION DURING
TYPE ZERO CONFIGURATION TRANSACTIONS, TO BE DRIVEN PRIOR TO THE ASSERTION OF
FRAME# . THIS ENSURES THAT THE IDSEL# INFORMATION, WHICH MUST TRAVERSE A COU-
PLING RESISTOR, IS VALID WHEN FRAME# IS DRIVEN ACTIVE. THE PROBLEM IS CAUSED BY
A SERIES RESISTOR THAN CONNECTS THE AD IDSEL INPUT OF A TARGET
LINE TO THE
DEVICE, THUS CREATING A SLOW SLEW RATE ON IDSEL. THE NUMBER OF CLOCKS THE
ADDRESS BUS SHOULD BE PRE-DRIVEN IS DETERMINED FROM THE RC TIME CONSTANT ON
IDSEL. ALL PRIOR USES OF STEPPING THAT WERE PERMITTED BY THE 2.2 AND EARLIER SPEC-
IFICATIONS ARE NO LONGER ALLOWED BY THE 2.3 SPECIFICATION.

8
 PCI 2.3 Update

Who Must Support Stepping?

ALL PCI DEVICES MUST BE ABLE TO HANDLE RECEIPT OF AN IDSEL-STEPPED TRANSACTION
PERFORMED BY THE MASTER OF A CONFIGURATION TYPE ZERO TRANSACTION. THE ABILITY
TO GENERATE STEPPING, HOWEVER, IS OPTIONAL. DEVICES NO LONGER INDICATE THEIR
ABILITY TO PERFORM STEPPING VIA THE STEPPING CONTROL BIT (THIS BIT IS NOW RESERVED
IN REV 2.3 OF THE SPEC).

Why Targets Don’t Latch Address During Stepping

Process
BECAUSE THE ASSERTION OF FRAME# QUALIFIES THE ADDRESS (AND COMMAND) AS
BEING VALID, NO TARGETS LATCH AND USE THE ADDRESS (INCLUDING IDSEL) AND COM-
MAND UNTIL FRAME# IS SAMPLED ASSERTED.

Preemption While Stepping in Progress

WHEN THE PCI BUS ARBITER GRANTS THE BUS TO A BUS MASTER, THE MASTER THEN WAITS
FOR BUS IDLE BEFORE INITIATING ITS TRANSACTION. IF, DURING THIS PERIOD OF TIME, THE
ARBITER DETECTS A REQUEST FROM A HIGHER-PRIORITY MASTER, IT CAN REMOVE THE
GRANT FROM THE FIRST MASTER BEFORE IT BEGINS A TRANSACTION (I.E., BEFORE IT ASSERTS
FRAME# ).
ASSUMING THAT THIS DOESN'T OCCUR, THE MASTER RETAINS ITS GRANT AND AWAITS BUS
IDLE. UPON DETECTION OF THE BUS IDLE STATE, THE MASTER DRIVES THE ADDRESS ONTO THE
AD BUS, BUT DELAYS THE ASSERTION OF FRAME# FOR SEVERAL CLOCKS UNTIL A VALID
IDSEL IS PRESENT AT THE TARGET DEVICE. DURING THIS PERIOD OF TIME, THE ARBITER MAY
STILL REMOVE THE GRANT FROM THE MASTER. THE ARBITER HASN'T DETECTED FRAME#
ASSERTED AND MAY THEREFORE ASSUME THAT THE MASTER HASN'T YET STARTED A TRANS-
ACTION. IF THE ARBITER RECEIVES A REQUEST FROM A HIGHER-PRIORITY MASTER, IT MAY
REMOVE THE GRANT FROM THE MASTER THAT IS CURRENTLY ENGAGED IN STEPPING IDSEL
ONTO THE AD BUS. IN RESPONSE TO THE LOSS OF GRANT, THE STEPPING MASTER MUST
IMMEDIATELY TRI-STATE ITS OUTPUT DRIVERS.

IT IS A RULE THAT THE ARBITER CANNOT DEASSERT ONE MASTER’S GRANT AND ASSERT
GRANT TO ANOTHER MASTER DURING THE SAME CLOCK CYCLE IF THE BUS APPEARS TO BE
IDLE. THE BUS MAY NOT, IN FACT, BE IDLE. A MASTER MAY NOT HAVE ASSERTED FRAME#
YET BECAUSE IT IS IN THE ACT OF STEPPING IDSEL ONTO THE AD BUS.

9
PCI System Architecture

IF THE ARBITER WERE TO SIMULTANEOUSLY REMOVE THE STEPPING MASTER’S GNT# AND
ISSUEGNT# TO ANOTHER MASTER, THE FOLLOWING PROBLEM WOULD RESULT. ON THE
NEXT RISING-EDGE OF THE CLOCK, THE STEPPING MASTER DETECTS REMOVAL OF ITS GNT#
AND BEGINS TO TURN OFF ITS ADDRESS DRIVERS (WHICH TAKES TIME). AT THE SAME TIME,
THE OTHER MASTER DETECTS ITS GNT# AND BUS IDLE (BECAUSE THE STEPPING MASTER HAD
NOT YET ASSERTED FRAME# ) AND INITIATES A TRANSACTION. THIS RESULTS IN A COLLI-
SION ON THE AD BUS.

WHEN THE BUS APPEARS TO BE IDLE, THE ARBITER MUST REMOVE THE GRANT FROM ONE
MASTER, WAIT ONE CLOCK CYCLE, AND THEN ASSERT GRANT TO THE OTHER MASTER. THIS
PROVIDES A ONE CLOCK CYCLE BUFFER ZONE FOR THE STEPPING MASTER TO BACK OFF ITS
OUTPUT DRIVERS COMPLETELY BEFORE THE OTHER MASTER DETECTS ITS GRANT ALONG WITH
BUS IDLE AND STARTS ITS TRANSACTION.

IT IS PERMISSIBLE FOR THE ARBITER TO SIMULTANEOUSLY REMOVE ONE MASTER’S GRANT

AND ASSERT ANOTHER’S DURING THE SAME CLOCK CYCLE IF THE BUS ISN’T IDLE (I.E., A
TRANSACTION IS IN PROGRESS). THERE IS NO DANGER OF A COLLISION BECAUSE THE MAS-
TER THAT HAS JUST RECEIVED THE GRANT CANNOT START DRIVING THE BUS UNTIL THE CUR-
RENT MASTER IDLES THE BUS.

Broken Master
THE ARBITER MAY ASSUME THAT A MASTER IS BROKEN IF THE ARBITER HAS ISSUED GNT# TO
THE MASTER, THE BUS HAS BEEN IDLE FOR 16 CLOCKS, AND THE MASTER HAS NOT ASSERTED
FRAME# TO START ITS TRANSACTION. THE ARBITER IS PERMITTED TO IGNORE ALL FURTHER
REQUESTS FOR BUS OWNERSHIP FROM THE BROKEN MASTER AND MAY OPTIONALLY REPORT
THE FAILURE TO THE OS (IN A DEVICE-SPECIFIC FASHION).

Stepping Example
FIGURE 11-3 ON PAGE 11 PROVIDES AN EXAMPLE OF AN INITIATOR USING STEPPING OVER
A PERIOD OF THREE CLOCKS TO DRIVE THE ADDRESS ONTO THE AD BUS.

CLOCK 3. THE INITIATOR CAN START THE TRANSACTION ON CLOCK THREE (GNT# SAM-
PLED ASSERTED AND BUS IDLE—FRAME# AND IRDY# SAMPLED DEASSERTED). IT
THEN BEGINS TO DRIVE THE ADDRESS AND IDSEL ONTO THE AD BUS AND THE COM-
MAND ONTO THE C/BE BUS.
CLOCK 4. DURING CLOCK CYCLE FOUR, IT CONTINUES TO DRIVE THE ADDRESS AND
IDSEL ONTO THE AD BUS; HOWEVER IDSEL HAS NOT YET REACHED VIH AT THE TAR-
GET.
CLOCK 5. DURING THE CLOCK CYCLE FIVE, IDSEL HAS REACHED VIH AND THE MASTER

10
 PCI 2.3 Update

ASSERTS FRAME# , INDICATING THE PRESENCE OF THE ADDRESS, IDSEL, AND COM-
MAND.
CLOCK 6. WHEN THE TARGETS SAMPLE FRAME# ASSERTED ON THE RISING-EDGE OF
CLOCK SIX (THE END OF THE ADDRESS PHASE), THEY LATCH THE ADDRESS, IDSEL, AND
COMMAND AND BEGIN THE ADDRESS DECODE.

Figure 11-3: Example of IDSEL Stepping

Final Step 3 Wait

Step 1 Step 2
Data State
Phase Idle
Address Phase Data Phase
Clock
1 2 3 4 5 6 7 8 9

CLK

GNT#

FRAME#

IRDY#

AD[31:0] Addr Data

Command Byte
C/BE#[3:0] Enables

IDSEL[ADx]

11
 PCI System Architecture

Chapter 14: Interrupts

2.3 Interrupt Disable

THE 2.3 (BIT 10) TO THE CONFIGURA-
SPECIFICATION ADDED AN INTERRUPT DISABLE BIT
TION COMMAND REGISTER. SEE FIGURE 14-4 ON PAGE 12. THE BIT IS CLEARED AT RESET
PERMITTING GENERATION OF INTX SIGNAL GENERATION. SOFTWARE MAY SET THIS BIT
THEREBY INHIBITING GENERATION OF INTERRUPTS VIA THE INTX SIGNALS. NOTE THAT THE
INTERRUPT DISABLE BIT HAS NO EFFECT ON MESSAGE SIGNALLED INTERRUPTS (MSI). THESE
INTERRUPTS ARE ENABLED VIA THE MSI CAPABILITY COMMAND REGISTER.

Figure 14-4: Interrupt Disable Bit Added to Configuration Command Register

15 11 10 9 8 7 6 5 4 3 2 1 0

Reserved 2.3 2.3

Interrupt Enable, was Reserved

Fast Back-to-Back Enable

SERR# Enable
Reserved, was Stepping Control
Parity Error Response
VGA Palette Snoop Enable
Memory Write and Invalidate Enable
Special Cycles
Bus Master
Memory Space
IO Space

12
 PCI 2.3 Update

2.3 Interrupt Status

THE 2.3 SPECIFICATION ADDED AN INTERRUPT STATUS BIT TO THE CONFIGURATION STATUS
REGISTER (PICTURED IN FIGURE14-5 ON PAGE 14). A FUNCTION MUST SET THIS STATUS BIT
WHEN AN INTERRUPT IS PENDING. IN ADDITION, IF THE INTERRUPT DISABLE BIT IN THE CON-
FIGURATION COMMAND REGISTER IS CLEARED (I.E. INTERRUPTS ENABLED), THEN THE FUNC-
TION’S INTX# SIGNAL IS ASSERTED, BUT ONLY AFTER THE STATUS BIT IS SET. THIS BIT IS
UNAFFECTED BY THE STATE OF THE INTERRUPT DISABLE BIT, AND THIS BIT HAS NO AFFECT ON
THE MSI MECHANISM.

The specification does not comment on the intended use of this bit. The tempta-
tion is great to assume that this bit is intended to replace the function-specific
interrupt pending bit that is mapped into memory or IO space. This bit is
accessed by the function’s ISR to determine if it has an interrupt is pending. If
the interrupt pending bit is set the device needs servicing. The ISR clears the
interrupt pending bit and services the interrupt. Clearing the bit causes the
INTx signal to be deasserted, which of course removes the interrupt request.
Because the Interrupt Status bit is read only, it cannot replace the interrupt
pending bit.

Now let’s look at a possible use for the Interrupt Status bit. It could be useful to
the Operating System during the process of handling interrupt sharing between
PCI devices. Because multiple PCI functions can share the same interrupt, soft-
ware must decide which device(s) have actually signalled an interrupt request.
The Operating System (OS) manages this process by maintaining a list of inter-
rupt service routines that share the same interrupt. Prior to the implementation
of the Interrupt Status bit, handling interrupt sharing involved the following
steps:

1. The OS calls the first interrupt service routine (ISR).

2. The first ISR checks its function-specific interrupt pending bit.
3. If the bit is set, the ISR performs the required service and then returns to the
OS.
4. If the bit is cleared, the ISR recognized that it does not have an interrupt
pending and returned to the OS.

This process is repeated until all the ISRs are called. This procedure is necessary
because the OS has no other way of determining which devices have an inter-
rupt pending.

The Interrupt Status bit introduced by the 2.3 version of the PCI specification
provides the OS with a known location to check which devices currently have

13
PCI System Architecture

interrupts pending execution. Rather than calling each ISR to check it’s inter-
rupt pending bit, the OS can simply check the Interrupt Status bit of each func-
tion that shares the interrupt to determine which need servicing. This reduces
the overhead required to handle interrupt sharing, and reduces the associated
latency.

Figure 14-5: Interrupt Status Bit Added to PCI Configuration Status Register

15 14 13 12 11 10 9 8 7 6 5 4 3 0
2.3 Reserved
Interrupt Status
Capabilities List
66MHz-Capable
Reserved
Fast Back-to-Back Capable
Master Data Parity Error
DEVSEL Timing
Signalled Target-Abort
Received Target-Abort
Received Master-Abort
Signalled System Error
Detected Parity Error

Chapter 19: Configuration

Registers
Changes to the Configuration Registers chapter include:

• New Sub Class Codes and definitions

• New Command and Status Register bits
• Removed discussion of UDF

14
 PCI 2.3 Update

Class Code Register Changes

The following table entries have been added by the PCI 2.3 specification.

Table 19-3: Class Code 1: Mass Storage Controllers

Sub-Class Prog. I/F Description

20h ATA CONTROLLER WITH SINGLE DMA

2.3 05h
30h ATA CONTROLLER WITH CHAINED DMA

Table 19-4: Class Code 2: Network Controllers

Sub-Class Prog. I/F Description

2.3 05h 00h WORLDFIP CONTROLLER

2.3 06h xxh PICMG 2.14 MULTI COMPUTING

Table 19-8: Class Code 6: Bridge Devices

Sub-Class Prog. I/F Description

40h SEMI-TRANSPARENT PCI-TO-PCI BRIDGE

WITH THE PRIMARY PCI BUS SIDE FACING THE SYSTEM
HOST PROCESSOR.
2.3 09h
80h SEMI-TRANSPARENT PCI-TO-PCI BRIDGE
WITH THE SECONDARY PCI BUS SIDE
FACING THE SYSTEM HOST PROCESSOR

2.3 0Ah 00h INFINIBAND-TO-PCI HOST BRIDGE

15
 PCI System Architecture

Table 19-9: Class Code 7: Simple Communications Controllers

Sub-Class Prog. I/F Description

2.3 04h 00h GPIB (IEEE 488.1/2) CONTROLLER

2.3 05h 00h SMART CARD

Table 19-14: Class Code C: Serial Bus Controllers

Sub-Class Prog. I/F Description

06h 00h INFINIBAND

2.3 00h IPMI SMIC INTERFACE

2.3 07h 01h IPMI KYBD CONTROLLER STYLE INTERFACE

02h IPMI BLOCK TRANSFER INTERFACE

2.3 08h 00h SERCOS INTERFACE STANDARD (IEC 61491)

2.3 09h 00h CANBUS

Table 19-15: Class Code D: Wireless Controllers

Sub-Class Interface Meaning

2.3 11h 00h BLUETOOTH

2.3 12h 00h BROADBAND

16
 PCI 2.3 Update

Table 19-19: Class Code 11h: Data Acquisition and Signal Processing Controllers

Sub-Class Interface Meaning

2.3 01h 00h PERFORMANCE COUNTERS

10h 00h
2.3 COMMUNICATIONS SYNCHRONIZATION PLUS
TIME AND FREQUENCY TEST/MEASUREMENT

2.3 20h 00h MANAGEMENT CARD

COMMAND REGISTER
Always mandatory. This register provides basic control over the device's ability to
respond to and/or perform PCI accesses. The 2.3 specification has made the fol-
lowing changes to the command register:
• Bit 7, previously defined as Stepping Control is now Reserved.
• Bit 10, previously Reserved is now defined as Interrupt Disable.
Table 19-21 on page 18 pictures the bits that have changed with the introduction
of the PCI 2.3 specification and the register is illustrated in Figure 19-3 on page
17.
Figure 19-3: Command Register Bit Assignment

15 11 10 9 8 7 6 5 4 3 2 1 0

Reserved 2.3 2.3

Interrupt Enable, was Reserved

Fast Back-to-Back Enable

SERR# Enable
Reserved, was Stepping Control
Parity Error Response
VGA Palette Snoop Enable
Memory Write and Invalidate Enable
Special Cycles
Bus Master
Memory Space
IO Space

17
 PCI System Architecture

Table 19-21: Command Register Bit Assignment

Bit Function

2.3 7 RESERVED. THIS BIT WAS STEPPING CONTROL IN PCI VERSION 2.2.

2.3 10 INTERRUPT DISABLE. THE BIT DISABLES THE FUNCTION FROM ASSERTING INTX# . A
VALUE OF 0 ENABLES THE ASSERTION OF ITS INTX# SIGNAL AND A VALUE OF 1 DIS-
ABLES INTX SIGNALLING. REFER TO “INTERRUPT DISABLE” ON PAGE 236 FOR DETAILS
REGARDING THIS BIT. NOTE THAT THIS BIT HAS NO AFFECT ON MSI.
REQUIRED? A FUNCTION THAT IS CAPABLE OF SIGNALLING INTERRUPTS VIA THE INTX
SIGNAL MUST IMPLEMENT THIS BIT.
DEFAULT SETTING: THE DEFAULT STATE AFTER RESET IS ZERO (INTERRUPTS ENABLED). A
VALUE OF 1 DISABLES THE ASSERTION OF ITS INTX# SIGNAL.

15:11 Reserved

Status Register
Figure 19-4 pictures the Status Register and Table 19-22 on page 19 describes the
Status register bit that has been added by the PCI 2.3 spec.

Figure 19-4: Status Register Bit Assignment

15 14 13 12 11 10 9 8 7 6 5 4 3 0
2.3 Reserved
Interrupt Status
Capabilities List
66MHz-Capable
Reserved
Fast Back-to-Back Capable
Master Data Parity Error
DEVSEL Timing
Signalled Target-Abort
Received Target-Abort
Received Master-Abort
Signalled System Error
Detected Parity Error

18
 PCI 2.3 Update

Table 19-22: Status Register Bit Assignment

Bit R/W Function

3:0 R Reserved. Hardwired to zero.

2.3 3 R INTERRUPT STATUS. THIS BIT REFLECTS THE STATE OF THE INTERRUPT WITHIN THE
FUNCTION. THE INTX SIGNAL IS ASSERTED WHEN THE FOLLOWING CONDITIONS
ARE MET:
1. THE INTERRUPT DISABLE BIT IN THE COMMAND REGISTER IS A 0 (INTERRUPTS
ARE ENABLED).
2. THIS INTERRUPT STATUS BIT IS A 1 (AN INTERRUPT IS PENDING)

NOTE THAT SETTING THE INTERRUPT DISABLE BIT TO A 1 HAS NO EFFECT ON THE
STATE OF THIS BIT.
REQUIRED? THIS BIT IS REQUIRED BY FUNCTIONS THAT ARE CAPABLE OF SIGNAL-
LING INTERRUPTS VIA AN INTX SIGNAL.

Chapter 21: Add-In Cards and

Connectors

Add-In Connectors

32- AND 64-BIT CONNECTORS

THE 2.3 SPECIFICATION MADE TWO MAJOR CHANGES TO THE CONNECTOR AND CARD
DEFINITIONS:
2.3
• ELIMINATION OF THE 5 — TO PUSH THE MIGRATION FROM 5V-
VOLT ONLY CARD
ONLY IMPLEMENTATIONS TO OR 3.3V OR UNIVERSAL CARD IMPLEMENTATIONS. NOTE
THAT THIS DOES NOT AFFECT 5V CONNECTORS.
• ADDITION OF TWO NEW PINS TO SUPPORT THE SYSTEM MANAGEMENT BUS IN PCI.

19
 PCI System Architecture

TABLE 21-1 ON PAGE 20 ILLUSTRATES THE 2.3 PINOUT CHANGES. NOTE THAT THE SHADED
COLUMN FOR 5V ONLY CARDS IS NO LONGER DEFINED WITHIN THE 2.3 SPECIFICATION,
BUT IS LEFT HERE FOR BACKWARD REFERENCE.

2.3 THIS TABLE SHOWS THE PINOUT FOR THREE CARD TYPES:

• 5V ONLY CARD — NO LONGER SUPPORTED BY THE 2.3 SPEC.

• 3V only card
• Universal card (the only 2.3 compliant card that will fit into a 5V connector)

2.3 THE FOLLOWING PINOUT CHANGES WERE MADE IN THE 2.3 SPEC:

• PIN B38 WAS GROUND AND IS NOW DEFINED AS PCIXCAP (PCI-X CAPABILITY).
THIS PIN IS DEFINED BY THE PCI-X ADDENDUM TO THE PCI 2.3 SPEC. IT IS ADDED
HERE TO INDICATE ITS USE IN PCI-X AND TO INDICATE THAT THE PCI AND PCI-X
CONNECTORS ARE THE SAME EXCEPT FOR THIS PIN.
• PIN A40 WAS RESERVED AND IS NOW DEFINED AS THE SMBCLK PIN.
• PIN A41 WAS RESERVED AND IS NOW DEFINED AS THE SMBDAT PIN.

2.3 Table 21-1: PCI Add-In Card Pinouts

5V Card Universal Card 3.3V Card

Pin Side B Side A Side B Side A Side B Side A Comment

38 Ground STOP# PCIXCAP STOP# PCIXCAP STOP#

40 PERR# SMBCLK PERR# SMBCLK PERR# SMBCLK

41 +3.3V SMBDAT +3.3V SMBDAT +3.3V SMBDAT

Figure 21-3 on page 21 illustrates the change in support for 5V only cards that
only the Universal card provides 5V connector compatibility.

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 PCI 2.3 Update

Figure 21-3: 3.3V, and Universal Card (5V Only Cards Not Support by Ver. 2.3)

3.3V Card 5V Card

(buffers support 3.3V operation) (buffers support 5V operation)

Universal Card
(buffers support either 3.3V or 5V operation)

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PCI System Architecture

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