J. Inst. Eng. India Ser.

B
DOI 10.1007/s40031-014-0087-y

ORIGINAL CONTRIBUTION

Unit Template Synchronous Reference Frame Theory Based

Control Algorithm for DSTATCOM
J. Bangarraju • V. Rajagopal • A. Jayalaxmi

Received: 30 April 2013 / Accepted: 17 December 2013

Ó The Institution of Engineers (India) 2014

Abstract This article proposes new and simplified unit Introduction

templates instead of standard phase locked loop (PLL) for
Synchronous Reference Frame Theory Control Algorithm In recent years, power electronics devices and equipment
(SRFT). The extraction of synchronizing components (sinh has grown largely because of advances in semiconductor
and cosh) for parks and inverse parks transformation using technology, large voltage and current handling capability
standard PLL takes more execution time. This execution and switching speeds of devices. Power electronic equip-
time in control algorithm delays the extraction of reference ment is more efficient than traditional mechanical equip-
source current generation. The standard PLL not only takes ment in distribution system. Today use of power electronic
more execution time but also increases the reactive power equipments are needed for computer systems, automobiles,
burden on the Distributed Static Compensator (DSTAT- home appliances, furnaces, lightening equipment, pumps
COM). This work proposes a unit template based SRFT and adjustable speed drives. This equipment draws non-
control algorithm for four-leg insulated gate bipolar tran- sinusoidal currents from source and pollutes the grid sup-
sistor based voltage source converter for DSTATCOM in ply. So power quality issues are most severe for industrial
distribution systems. This will reduce the execution time applications especially poor voltage regulation, load
and reactive power burden on the DSTATCOM. The pro- unbalancing, excessive reactive power, current harmonics,
posed DSTATCOM suppress harmonics, regulates the neutral current compensation and voltage sags, voltage
terminal voltage along with neutral current compensation. unbalance and poor power factor which have drawn much
The DSTATCOM in distribution systems with proposed attention in power quality area [1, 2]. An IEEE-519 stan-
control algorithm is modeled and simulated using MAT- dard has proposed to control power quality problems [3].
LAB using SIMULINK and Simpower systems toolboxes. Power quality problems in the distribution system can be
mitigated by using custom power devices. The DSTAT-
Keywords Insulated gate bipolar transistor
COM (distribution static compensator) is a shunt connected
DSTATCOM
Phase locked loop
device to compensate current harmonics, reactive power
Synchronous Reference Frame Theory
Harmonics
compensation and regulates the terminal voltage of the
Power quality
Voltage source converter distribution system.
The main advantages of DSTATCOM is to regulate
current injection and improve the power factor, harmonic
J. Bangarraju (&)
V. Rajagopal content in load current and voltage regulation in distribu-
Department of Electrical and Electronics Engineering, Padmasri
tion system. The neutral current compensation for three-
Dr. B.V. Raju Institute of Technology, Narsapur, Medak 502313,
Andhra Pradesh, India phase four-wire distribution system is achieved by using a
e-mail: rajujbr@gmail.com four-leg VSC for DSTATCOM [4–8].Many control strat-
egies are proposed for estimation of reference currents for
A. Jayalaxmi
DSTATCOM. Akagi et al. proposed instantaneous reactive
Department of Electrical and Electronics Engineering, JNTU
College of Engineering, Hyderabad, Hyderabad 500090, power theory and it is based on the transformation of three-
Andhra Pradesh, India phase quantities to two-phase quantities in a-b frame.

123
 J. Inst. Eng. India Ser. B

Calculation of instantaneous active and reactive power by power is delivered to the system. If it is greater than the
applying Clark’s transformation is explained in [9, 10]. reference terminal voltage, the DSTATCOM injects
Synchronous reference frame theory based control algo- inductive VAR and the terminal voltage is less than the
rithm is proposed for DSTATCOM by transforming the rated terminal voltage than supplied capacitive VAR. The
load currents in synchronously rotating d-q frame by using DSTATCOM can be operated in zero voltage regulation
parks transformation [11–13]. Various control strategies (ZVR) and unity power factor (UPF) mode. The ZVR and
including the instantaneous symmetrical components for UPF mode of operation cannot be achieved simultaneously.
different voltages was proposed by Rao et al [14]. The UPF operation of DSTATCOM is depicted in the
Power balance theory for active filter in distribution phasor diagram of Fig. 3a when the DSTATCOM is
systems was proposed by B. N. Singh et al [15]. Neural operated at UPF, the compensating current is injected in
network technologies for active power filter control was such a manner that the supply voltage and supply current
proposed by Vazquez and Salmeron [16] . Figure 1 shows are exactly in phase.
the single line diagram of DSTATCOM for distribution The ZVR operation of DSTATCOM is depicted in the
system with consumer loads. phasor diagram of Fig. 3b. The DSTATCOM operates in
In this work, a unit template synchronous reference frame such a way that the voltage at the load (Vt) is equal to the
theory algorithm for four-leg IGBT based current controlled source voltage (Vs).
voltage source converter (VSC) is presented for DSTAT-
COM which reduces execution time, harmonic elimination,
terminal voltage control and load balancing along with Control Algorithm for DSTATCOM
neutral current compensation. This also improves the per-
formance of the DSTATCOM than a conventional syn- In synchronous reference frame theory (SRFT) algorithm is
chronous reference frame theory because of standard PLL. shown in Fig. 2 The load currents (iLabc) are sensed and
transformed into direct–quadrature–zero (dqo) using parks
transformation. The transformed currents are filtered by
Basic Principle of DSTATCOM using low pass filters. The sensed dc bus voltage compared
with the reference dc bus voltage and the error dc bus voltage
Figure 2 shows a detailed diagram of DSTATCOM for is given to the dc bus proportional integral (PI) controller.
distribution systems with SRFT control algorithm. The The reference terminal voltage is compared with the sensed
DSTATCOM consisting of four-leg IGBT based VSC is terminal voltage and error terminal voltage is given to the ac
connected to point of common coupling (PCC) through the PI controller. The output of dc bus PI controller is added to
filtering inductors. The nonlinear consumer load is a direct axis component and output of ac PI controller is added
combination of diode bridge rectifier with large inductor to quadrature component of dqo load currents. The direct and
and resistor on dc link. DSTATCOM is a shunt connected quadrature components of load currents are again trans-
custom power device which can control the terminal volt- formed from dqo into three phase abc system using inverse
age and suppresses current harmonics along with load parks transformation. The parks and inverse parks transfor-
balancing. A ripple is also connected at the PCC to mation needs the sinh and cosh components for synchro-
smoothen the voltage ripples. If the sensed terminal voltage nizing the loads currents with the terminal voltages.
is equal to the reference terminal voltage, no reactive The standard PLL generates the sinh and cosh by using
phase detector, loop filter and voltage controlled oscillator
which consumes more execution time. The proposed sinh
and cosh generator shown in Fig. 4 uses a simple unit in-
phase and quadrature templates which reduces and sim-
plifies the execution time.

Simulation Results and Discussion

The performance of unit template based synchronous ref-

erence frame theory control algorithm for four-leg VSC
based DSTATCOM with three-phase four-wire linear/non-
linear loads for neutral current compensation, power factor
correction and voltage regulation along with harmonic
Fig. 1 Single line diagram of distribution system with DSTATCOM reduction is shown in the waveforms. The different

123
J. Inst. Eng. India Ser. B

Fig. 2 Four-leg VSC based DSTATCOM with unit template SRFT control algorithm

Fig. 4 Unit template based sinh and cosh generator

parameters of Fig. 1, considered for this purpose are given

in Appendix.

(a)
Performance of Unit Template Synchronous Reference
Frame Theory for DSTATCOM with Linear Loads
for UPF Operation

The performance of unit template synchronous reference

frame theory for DSTATCOM with linear loads is depicted
in Fig. 5 for balanced / unbalanced condition. At t = 0.7 s,
three-phase load is changed to two-phase load. Again at t =
0.9 s two-phase load is changed to three-phase load. The
source voltages (vsabc), source currents (isabc), load currents
(iLabc), DSTATCOM compensating current (icabc), source
(b) neutral current (isn), load neutral current (iLn),dc bus volt-
Fig. 3 a Phasor diagram for UPF operation. b Phasor diagram for
age (vdc) and terminal voltage (vt) is shown in Fig. 5. The
ZVR operation source currents (isabc), source voltages (vsabc) are balanced

123
 J. Inst. Eng. India Ser. B

Fig. 5 Performance of unit template synchronous reference frame Fig. 6 Performance of unit template synchronous reference frame
theory for DSTATCOM with linear loads in UPF operation theory for DSTATCOM with non-linear loads in UPF operation

and harmonic free at different load variations and power neutral current compensated by four-leg VSC. During
factor is unity at source. As load is changed between 0.7 s unbalanced load condition, load neutral current (iLn) is
to 0.9 s, the load neutral current is compensated by four-leg compensated by the four-leg VSC of DSTATCOM and
VSC. During unbalanced load condition, load neutral cur- source neutral current (isn) is zero. The source current total
rent (iLn) is compensated by the four-leg VSC of harmonic distortion (THD) is 2.44 % whereas load THD is
DSTATCOM and source neutral current (isn) is zero. The 45.04 %. The dc bus voltage (vdc) is regulated to the ref-
dc bus voltage (vdc) is regulated to the reference value of erence value of 700 V at all load disturbances.
700 V at all load disturbances.

Performance of Unit Template Synchronous Reference

Performance of Unit Template Synchronous Reference Frame Theory for DSTATCOM with Linear Loads
Frame Theory for DSTATCOM with Non-Linear for Voltage Regulation Operation
Loads for UPF Operation
The performance of unit template synchronous reference
The performance of unit template synchronous reference frame theory for DSTATCOM with linear loads is depicted
frame theory for DSTATCOM with non-linear loads is in Fig. 7 for balanced/unbalanced condition. At t = 0.7 s,
depicted in Fig. 6 for balanced/unbalanced condition. At Three-phase load is changed to two-phase load. Again at t =
t = 0.7 s, Three-phase load is changed to two-phase load. 0.9 s two-phase load is changed to three-phase load. The
Again at t = 0.9 s two-phase load is changed to three-phase source voltages (vsabc), source currents (isabc), load currents
load. The corresponding source voltages (vsabc), source (iLabc), DSTATCOM compensating current (icabc), source
currents (isabc), load currents (iLabc), DSTATCOM com- neutral current (isn), load neutral current (iLn), dc bus voltage
pensating current (icabc), source neutral current (isn), load (vdc) and terminal voltage (vt) is shown in Fig. 7. The source
neutral current (iLn), dc bus voltage (vdc) and terminal currents (isabc), source voltages (vsabc) are balanced and
voltage (vt) is shown in Fig. 6. The source currents (isabc), harmonic free at different load variations and power factor is
source voltages (vsabc) are balanced and harmonic free at unity at source. Source voltage (vsabc) is regulated by sup-
different load variations and power factor is unity at plying reactive power. As load is changed between 0.7 s to
source. As load is changed between 0.7 s to 0.9 s load 0.9 s load neutral current compensated by four-leg VSC.

123
J. Inst. Eng. India Ser. B

Fig. 9 Phase angle between voltage and current waveforms for

standard PLL

Fig. 7 performance of unit template synchronous reference frame

theory for DSTATCOM with linear loads in voltage regulation
operation

Fig. 10 Phase angle between voltage and current waveforms for unit
template

During unbalanced load condition, load neutral current (iLn)

is compensated by the four-leg VSC of DSTATCOM and
source neutral current (isn) is zero. The dc bus voltage (vdc) is
maintained near to the reference value of 700 V at all load
disturbances. The PCC voltage maintained near to reference
value of 339 V at all load disturbances.

Performance of Unit Template Synchronous Reference

Frame Theory for DSTATCOM with Non-Linear
Loads for Voltage Regulation Operation

The performance of unit template synchronous reference

frame theory for DSTATCOM with non-linear loads
(three-phase diode bridge rectifier with R-L load) is
depicted in Fig. 8 for balanced / unbalanced condition. At
t = 0.7 s, Three-phase load is changed to two-phase load.
Again at t = 0.9 s, two-phase load is changed to three-phase
Fig. 8 Performance of unit template synchronous reference frame
theory for DSTATCOM with non-linear loads in voltage regulation
load. The source voltages (vsabc), source currents (isabc), load
operation currents (iLabc), DSTATCOM compensating current (icabc),

123
 J. Inst. Eng. India Ser. B

Fig. 11 Power quality performance of source voltage, source current and load current

source neutral current (isn),load neutral current (iLn),dc bus voltage and current are having a THD of 3.89 and 2.77 %,
voltage (vdc) and terminal voltage (vt) is shown in Fig. 8. The respectively. These THDs are well within the limits of
source currents (isabc), source voltages (vsabc) are balanced IEEE-519 standards.
and harmonic free at different load variations. Source volt-
ages (vsabc) are regulated by supplying reactive power. As
Conclusion
load is changed between 0.7 s to 0.9 s, load neutral current
compensated by four-leg VSC. During unbalanced load
The performance of unit template based synchronous refer-
condition, load neutral current (iLn) is compensated by the
ence frame theory for four-leg VSC based DSTATCOM is
four-leg VSC of DSTATCOM and source neutral current
found satisfactory with three-phase four-wire consumer loads.
(isn) is zero. The source current THD is 2.77 %, whereas load
The results display harmonic elimination, voltage regulation
THD is 44.88 %. The dc bus voltage (vdc) is maintained near
and neutral current compensation along with power factor
to the reference value of 700 V at all load disturbances. The
correction for frequently varying three-phase four-wire con-
PCC voltage is maintained near to reference value of 339 V at
sumer loads. The proposed unit template sinh and cosh gen-
all load disturbances.
erator is quiet simple and reduces the execution time and time
delay of the algorithm, which decides the extraction of ref-
erence currents and reactive power consumption.
Comparison of Standard PLL with Unit Template
Method
Appendix
Standard PLL takes more time for execution and also phase
angle calculation between voltage and current is not uniform Three-phase ac source line-line voltage : 415 V, 50 Hz
as shown in Fig. 9. These two disadvantages can be eliminated Three-phase source impedance : Rs = 0.01X, Ls = 2 mH
by using unit template method for generation of sinh and cosh Consumer loads : single phase diode bridge rectifier
which reduces both the execution time and phase angle. The with R = 25 X and L = 200 mH
estimation of angle between voltage and current is uniform Ripple filter : Rf = 5 X and Cf = 6 lF
throughout as shown in Fig 10. The wave forms show dif- dc bus capacitor : Cdc = 4000 lF
ference between standard PLL and unit template method. dc voltage PI controller : Kpd = 0.19, Kid = 0.2
PCC voltage PI controller : Kpq = 0.1, Kiq = 0.6
ac inductor : 2.5 mH
Power Quality Performance with Unit Template PWM SWITCHING FREQUENCY : 10 KHZ.
Method

The power quality performance of source voltage, source

References
current and load current are shown in Fig. 11. The con-
sumer load current is drawing a highly non-linear current 1. R.C. Dugan, M.F. McGranaghan, H.W. Beaty, Electrical power
of THD 44.88 % as shown in the figure, but the source systems quality (McGraw-Hill, New York, 1996)

123
J. Inst. Eng. India Ser. B

2. A. Ghosh, G. Ledwich, Power quality enhancement using custom 10. H. Akagi, S. Ogasawara, H. Kim, The theory of instantaneous
power devices (Kluwer Academic Publishers, London, 2002) power in three-phase four-wire systems: a comprehensive
3. IEEE recommended practices and requirements for harmonics approach. Proc. IEEE Ind. Appl. Conf. 1, 431–439 (1999)
control in electrical power systems, IEEE Std. 519, (1992) 11. M.D. Bhattacharya, B. Benerjee, Synchronous reference frame
4. H. Fugita, H. Akagi, Voltage-regulation performance of a shunt harmonic isolator using series active filter. Fourth European
active filter intended for installation on a power distribution Power Electronic Conference, Florence, vol. 3 (1991), pp. 30–35
system. IEEE Trans. Power Electron. 22(1), 1046–1053 (2007) 12. S. Bhattacharya, D. Diwan, Synchronous frame based controller
5. H.-L. Jou, K.D. Wu, Wu J-C, W.J. Chiang, A three-phase four- implementation for a hybrid series active filter system. Proceed-
wire power filter comprising a three-phase three-wire active filter ings of the IEEE Industry Applications Society Meeting (1995),
and a zig–zag transformer. IEEE Trans. Power Electron. 23(1), pp. 2531–2540
252–259 (2008) 13. B. Singh, P. Jayaprakash, D.P. Kothari, A T-connected trans-
6. H.-L. Jou, J.-C. Wu, K.-D. Wu, W.-J. Chiang, Y.-H. Chen, former three-leg VSC based DSTATCOM for power quality
Analysis of zig–zag transformer applying in the three-phase four- improvement. IEEE Trans. Power Electron. 23(6), 2710–2718
wire distribution power system. IEEE Trans. Power Deliv. 20(2), (2008)
1168–1173 (2005) 14. U.K. Rao, M.K. Mishra, A. Ghosh, Control strategies for load
7. E.F. Fuchs, Md A.S. Mausoum, Power quality in power systems compensation using instantaneous symmetrical component theory
and electrical machines (Elsevier Academic Press, London, under different supply voltages. IEEE Trans. Power Delivery
2008) 23(4), 2310–2317 (2008)
8. H.L. Jou, K.D. Wu, J.C. Wu, C.H. Li, M.S. Huang, Novel power 15. B.N. Singh, B. Singh, A. Chandra, K. Al-Haddad, Design and
converter topology for three-phase four-wire hybrid power filter. digital implementation of active power filters with power balance
IET Power Electron 1(1), 164–173 (2008) theory. IEE Proc. 152(5), 1149–1160 (2005)
9. Y.K. Akagi, A. Nabae, Generalized theory of the instantaneous 16. J.R. Vazquez, P. Salmeron, Active power filter control using
reactive power in three-phase circuits. Proc. IEEE IPEC 83, neural network technologies. Proc. Inst. Electr. Eng. Elect. Power
821–827 (1983) Appl. 150(2), 139–145 (2003)

123