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Pre-Lab1 Digital Design

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14 views6 pages

Pre-Lab1 Digital Design

Uploaded by

Gia Bao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Pre Laboratory 1:

ADDERS, SUBTRACTORS AND MULTIPLIERS

OBJECTIVES
➢ The purpose of this lab is to learn how to connect simple input (switches) and output devices
(LEDs and 7-segment) to an FPGA chip and implement a circuit that uses these devices.
➢ Examine arithmetic circuits that add, subtract, and multiply numbers.

PREPARATION FOR LAB 1


➢ Students have to simulate all the exercises in Pre Lab 1 at home. All results (codes, waveform,
RTL viewer, … ) have to be captured and submitted to instructors prior to the lab session.
If not, students will not participate in the lab and be considered absent this session.

REFERENCE
1. Intel FPGA training

Department of Electronics Page | 1


Digital Design Laboratory (Advanced Program)
Pre Laboratory 1:
ADDERS, SUBTRACTORS AND MULTIPLIERS
EXERCISE 1:
Objective: Known how to program an adder using ‘+’ sign in System Verilog.

Requirement: Consider the four-bit ripple-carry adder circuit in Figure 1.

Figure 1: A four-bit ripple carry adder.

This circuit can be implemented using a ’+’ sign in System Verilog. For example, the following
code fragment adds n-bit numbers A and B to produce outputs sum and carry:

...
wire [n-1:0] sum
...
assign sum = A + B;
Modify the code above to implement an 8-bit carry adder.

Using waveform tool, test the functionality of your design by inputting various data values and
observing the generated outputs.

Check: Your report has to show two results:

➢ The waveform to prove the circuit works correctly.

➢ The result of RTL viewer.

Department of Electronics Page | 2


Digital Design Laboratory (Advanced Program)
Pre Laboratory 1:
ADDERS, SUBTRACTORS AND MULTIPLIERS
EXERCISE 2
Objective: Known how to program a multiplier.

Requirement: Figure 2a gives an example of paper-and-pencil multiplication P = A × B, where A


= 11 and B = 12.

(a) Decimal (b) Binary (c) Implementation


Figure 2: Multiplication of binary numbers.

We compute P = A × B as an addition of summands. The first summand is equal to A times the


ones digit of B. The second summand is A times the tens digit of B, shifted one position to the left.
We add the two summands to form the product P = 132.
Part b of the figure shows the same example using four-bit binary numbers. To compute P = A×B,
we first form summands by multiplying A by each digit of B. Since each digit of B is either 1 or 0,
the summands are either shifted versions of A or 0000. Figure 2c shows how each summand can
be formed by using the Boolean AND operation of A with the appropriate bit of B.
A four-bit circuit that implements P = A × B is illustrated in Figure 3. Because of its regular
structure, this type of multiplier circuit is called an array multiplier. The shaded areas correspond
to the shaded columns in Figure 2c. In each row of the multiplier AND gates are used to produce
the summands, and full adder modules are used to generate the required sums.

Department of Electronics Page | 3


Digital Design Laboratory (Advanced Program)
Pre Laboratory 1:
ADDERS, SUBTRACTORS AND MULTIPLIERS

Figure 3: An array multiplier circuit.


At a higher level, a row of full adders functions as an n-bit adder and the array multiplier circuit
can be represented as shown in Figure 4. Each n-bit adder adds a shifted version of A for a given
row and the partial product of the row above. Abstracting the multiplier circuit as a sequence of
additions allows us to build larger multipliers. The multiplier should consist of n-bit adders
arranged in a structure shown in Figure 4.

Department of Electronics Page | 4


Digital Design Laboratory (Advanced Program)
Pre Laboratory 1:
ADDERS, SUBTRACTORS AND MULTIPLIERS

Figure 4: An array multiplier implemented using n-bit adders.


Use this approach, write System Verilog code to implement an 8 x 8 multiplier circuit.

Instruction:

➢ Generate a System Verilog file with the code above and include it in the project.
➢ Compile the code. Use the Quartus RTL Viewer tool to examine the gate-level circuit
produced from the code, then verify that the latch is implemented as shown in Figure 3 and
4.

Department of Electronics Page | 5


Digital Design Laboratory (Advanced Program)
Pre Laboratory 1:
ADDERS, SUBTRACTORS AND MULTIPLIERS
➢ Simulate the behavior of your System Verilog code. Test the functionality of your design
by inputting various data values and observing the generated outputs.

Check: Your report has to show two results:

➢ The waveform to prove the circuit works correctly.

➢ The result of RTL viewer.

Department of Electronics Page | 6


Digital Design Laboratory (Advanced Program)

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