Module 2

Von Neuman Architecture

Von Neuman Architecture is based on stored program concept, i.e, instructions ,
data and program are stored in memory. Most modern computers use this design.
A program is a list of instructions stored in memory.
A computer consists of five functionally independent main parts: input, memory,
arithmetic and logic, output, and control units,
1. Input Unit : Computers accept coded information through input units. The
most common input device is the keyboard. Whenever a key is pressed, the
corresponding letter or digit is automatically translated into its corresponding
binary code and transmitted to the processor.
Von Neuman Architecture
Von Neuman Architecture
2. Memory Unit :The function of the memory unit is to store programs and data.
There are two classes of storage, called primary and secondary.
Primary Memory
Primary memory, also called main memory, is a fast memory that operates at
electronic speeds. Programs must be stored in this memory while they are
being executed. The memory consists of a large number of semiconductor
storage cells, each capable of storing one bit of information. These cells are
handled in groups of fixed size called words.The memory is organized so that
one word can be stored or retrieved in one basic operation.A memory in which
any location can be accessed in a short and fixed amount of time after
specifying its address is called a random-access memory (RAM).
Von Neuman Architecture
Cache Memory
As an adjunct to the main memory, a smaller, faster RAM unit, called a cache, is used
to hold sections of a program that are currently being executed, along with any associated
data. At the start of program execution, the cache is empty. As execution proceeds,
instructions are fetched into the processor chip, and a copy of each is placed in the cache.
Now if this instruction is to be repeatedly executed instead of fetching from main memory
they can be accessed from cache faster.
Secondary Storage
Primary memory is expensive and does not retain information when power is turned
off(volatile). Thus additional, less expensive, permanent secondary storage is used when
large amounts of data and many programs have to be stored, but its access time is slower.
Example: Magnetic tape, magnetic disk, CD, flash memory
Von Neuman Architecture
3. Arithmetic Logic Unit : Any arithmetic or logic operation, such as addition,
subtraction, multiplication, division, or comparison of numbers, is initiated by bringing
the required operands into the processor, where the operation is performed by the
ALU. When operands are brought into the processor, they are stored in high-speed
storage elements called registers. Access times to registers are even shorter than
cache.
4. Output Unit: Its function is to send processed results to the outside world. A familiar
example of such a device is a printer.
5. Control Unit: The operation of other units are coordinated by CU. The control unit
sends control signals to other units and senses their states.Control circuits are
responsible for generating the timing signals that govern the transfers and determine
when a given action is to take place. Data transfers between the processor and the
memory are also managed by the control unit through timing signals.
Von Neuman Architecture
The operation of a computer can be summarized as follows:

1. The computer accepts information in the form of programs and data through
an input unit and stores it in the memory.
2. Information stored in the memory is fetched under program control into an
arithmetic and logic unit, where it is processed.
3. Processed information leaves the computer through an output unit.
4. All activities in the computer are directed by the control unit.
Basic Operational Concepts
Basic Operational Concepts
In addition to the ALU and the control circuitry, the processor contains a number of
registers used for several different purposes. The instruction register (IR) holds the
instruction that is currently being executed.The program counter (PC) contains the
memory address of the next instruction to be fetched and executed. During the
execution of an instruction, the contents of the PC are updated to correspond to
the address of the next instruction to be executed. In addition to the IR and PC,
there are general-purpose registers R0 through Rn−1, often called processor
registers. They serve a variety of functions, including holding operands that have
been loaded from the memory for processing.
Memory Locations and Addresses
The memory consists of many millions of storage cells, each of which can store a
bit of information having the value 0 or 1. The memory is organized so that a group
of n bits can be stored or retrieved in a single, basic operation. Each group of n bits
is referred to as a word of information, and n is called the word length. Modern
computers have word lengths that typically range from 16 to 64 bits. If the word
length of a computer is 32 bits, a single word can store a 32-bit signed number or
four ASCII-encoded characters, each occupying 8 bits, as
Memory Locations and Addresses
Memory Locations and Addresses
We now have three basic information quantities to deal with: bit, byte, and word. A
byte is always 8 bits, but the word length typically ranges from 16 to 64 bits. It is
impractical to assign distinct addresses to individual bit locations in the memory.
The most practical method is to assign addresses to each byte in memory. The term
byte-addressable memory is used for this assignment.
There are two ways that byte addresses can be assigned across words. The name
big-endian is used when lower byte addresses are used for the more significant
bytes (the leftmost bytes) of the word. The name little-endian is used for the
opposite ordering, where the lower byte addresses are used for the less significant
bytes (the rightmost bytes) of the word.
Instruction Set Architecture
Instruction Set Architecture defines the type of instructions supported by the
processor. Based on the type of operation they perform instructions are classified
to 4:

1. Arithmetic / logic instructions

2. Data transfer instruction ( Load, Store, Move)
3. Sequencing and control instructions( Branch, Jump)
4. I/O function instructions

ISA also defines the length and format of each type of instructions.
Some Instructions
● Possible locations that may be involved in transfers are memory locations,
processor registers, or registers in the I/O subsystem.
● For example, names that represent the addresses of memory locations may be
LOC, PLACE, A, or VAR2.
● Predefined names for the processor registers may be R0 or R5.
● R5. Registers in the I/O subsystem may be identified by names such as
DATAIN or OUTSTATUS.
● Load R2, LOC
This instruction reads the contents of a memory location whose address is
represented symbolically by the label LOC and loads them into processor
register R2. The originalcontents of location LOC are preserved, whereas
those of register R2 are overwritten.
Some Instructions
● Add R4, R2, R3
add the contents of registers R2 and R3, then places sum into register R4. The
operands in R2 and R3 are not altered, but R4 is overwritten by the sum.
● Store R4, LOC
copies the operand in register R4 to memory location LOC. The original
contents of location LOC are overwritten, but those of R4 are preserved.
● Add R4, R2
Add contents of registers R4 and R2 and place sum in register R4
● Load A Acc ← [ A ]
● Add R0 Acc ← [ Acc ] +[ R0 ]
● Store C C ← [ Acc ]
One operand will be taken as the accumulator (Special register that store
intermediate value of ALU)
Register Transfer Notation
To describe the transfer of information, the contents of any location are denoted by
placing square brackets around its name.
R2 ← [LOC]
contents of memory location LOC are transferred into processor register R2.
R4 ← [R2]+[R3]
adds the contents of registers R2 and R3, and places their sum into register R4.
This type of notation is known as Register Transfer Notation (RTN). Note that the
right hand side of an RTN expression always denotes a value, and the left-hand
side is the name of a location where the value is to be placed, overwriting the old
contents of that location.
Assembly Language Notation
Load R2, LOC
transfer of data, from memory location LOC to processor register R2
Add R4, R2, R3
adding two numbers contained in processor registers R2 and R3 and placing their
sum in R4
An instruction specifies an operation to be performed and the operands involved.
In the above examples, we used the English words Load and Add to denote the
required operations. In the assembly-language instructions of actual (commercial)
processors, such operations are defined by using mnemonics, which are typically
abbreviations of the words describing the operations.
Example : Load maybe LD, Store maybe ST or STR
RISC and CISC Instruction Sets
There are two fundamentally different approaches in the design of instruction sets
for modern computers.
1. One popular approach is based on the premise that higher performance can
be achieved if each instruction occupies exactly one word in memory, and all
operands required for an arithmetic or logic operation are already in processor
registers. The restriction that each instruction must fit into a single word
reduces the complexity and the number of different types of instructions that
may be included in the instruction set of a computer. Such computers are
called Reduced Instruction Set Computers (RISC).
2. Makes use of more complex instructions that takes more than one word of
memory. Instructions may take more than 1 clock cycle to execute. Required
more data types and more complex addressing modes. These are called called
Complex Instruction Set Computers (CISC).
Instruction Execution and Straight-Line Sequencing
Instruction Execution and Straight-Line Sequencing

● When the execution begins PC (Program Counter) will contain the address of
first instruction to be executed ie, i in fig.
● Next, the processor control circuits use the information in the PC to fetch and
execute instructions, one at a time, in the order of increasing addresses. This is
called straight-line sequencing.
● During the execution of each instruction, the PC is incremented by 4 to point to
the next instruction.
● Thus, after the Store instruction at location i + 12 is executed, the PC contains
the value i + 16, which is the address of the first instruction of the next program
segment.
Instruction Execution and Straight-Line Sequencing

Executing a given instruction is a two-phase procedure.

1. Instruction fetch, the instruction is fetched from the memory location whose address
is in the PC. This instruction is placed in the instruction register (IR) in the processor.
2. Instruction execute, the instruction in IR is examined to determine which operation is
to be performed. The specified operation is then performed by the processor. This
involves a small number of steps such as fetching operands from the memory or
from processor registers, performing an arithmetic or logic operation, and storing the
result in the destination location.
At some point during this two-phase procedure, the contents of the PC are advanced to
point to the next instruction. When the execute phase of an instruction is completed, the
PC contains the address of the next instruction, and a new instruction fetch phase can
begin.
Branching
Consider the task of adding a list of n numbers. The numbers NUM1, NUM2,...,
NUMn, use separate Load and Add instructions to add each number to the
contents of register R2. After all the numbers have been added, the result is placed
in memory location SUM.

Instead of using a long list of Load and Add instructions, it is possible to implement
a program loop using branch statements.

Assume that the number of entries in the list, n, is stored in memory location N and
it is loaded to Register R2 which is used as a counter to determine the number of
times the loop is executed.
Branching
This branch instruction loads a new address into the program counter. As a result, the
processor fetches and executes the instruction at this new address, called the branch
target, instead of the instruction that follows the branch instruction in sequential address
order. A conditional branch instruction causes a branch only if a specified condition is
satisfied. If the condition is not satisfied, the PC is incremented in the normal way.
Branch_if_[R2]>0 LOOP
is a conditional branch instruction that causes a branch to location LOOP if the contents of
register R2 are greater than zero ie,there are more numbers to be added.
In generic assembly language: Branch_greater_than R2, #0, LOOP
Actual mnemonic : BGT R4, #0, LOOP
Addressing Modes
The different ways for specifying the locations of instruction operands are known
as addressing mode
1. Immediate Mode: The operand is given explicitly in the instruction.
Example : Add R4, R6, #200
adds the value 200 to the contents of register R6, and places the result into
register R4.
2. Register Mode : The operand is the contents of a processor register; the name
of the register is given in the instruction.
Example: Add R4, R2, R3
uses the Register mode for all three operands. Registers R2 and R3 hold the
two source operands, while R4 is the destination.
Addressing Modes
3. Absolute( Direct) Mode : The operand is in a memory location; the address of
this location is given explicitly in the instruction.
Example: Integer NUM1, NUM2, SUM
represent declaration of global variables in program
or Load R2, NUM1
which loads the value in the memory location NUM1 into register R2.
4. Indirect Addressing Mode : The effective address of the operand is the
contents of a register that is specified in the instruction. The register acts as a
pointer to the operand and we say the operand is accessed indirectly by using
the address in the register.
To execute the Load instruction in Figure 2.7, the processor uses the value B, which is in
register R5, as the effective address of the operand.
In Figure 2.8, we use register indirect mode to implement program for adding n numbers.
Here Register R4 is used as a pointer to the numbers in the list, and the operands are
accessed indirectly through R4. The initialization section of the program loads the counter
value n from memory location N into R2. Then, it uses the Clear instruction to clear R3 to
0. The next instruction uses the Immediate addressing mode to place the address value
NUM1, which is the address of the first number in the list, into R4.
Addressing Modes
5. Index Addressing Mode: The effective address of the operand is generated by adding a
constant value to the contents of a register. Weindicate the Index mode symbolically as :
X(Ri) EA = X+Ri The register used in this mode is
called the index register.

In Figure 2.9a, the index register, R5, contains the address of a memory location, and the
value X defines an offset. In Figure 2.9b X corresponds to a memory address, and the
contents of the index register R5 define the offset to the operand.

Consider a simple example involving a list of test scores for students taking a given
course.Assume that the list of scores, begin at location LIST. Each record consists of the
student’s identification number (ID), followed by the scores the student earned on three tests.
There are n students in the class, and the value n is stored in location N immediately in front
of the list. The list represents a two-dimensional array having n rows and four columns. Each
row contains the entries for one student, and the columns give the IDs and test scores.
Addressing Modes
Our aim is to compute the sum of all scores obtained on each of the tests and store
these three sums in memory locations SUM1, SUM2, and SUM3. In the program
Register R2 is used as the index register. Before the loop is entered, R2 is set to
point to the ID location of the first student record which is the address LIST.
On the first pass through the loop, test scores of the first student are added to the
sums held in registers R3, R4, and R5, which are initially cleared to 0. These scores
are accessed using the Index addressing modes 4(R2), 8(R2), and 12(R2). The index
register R2 is then incremented by 16 to point to the ID location of the second
student. Register R6, initialized to contain the value n, is decremented by 1 at the
end of each pass through the loop. When the contents of R6 reach 0, all student
records have been accessed, the loop terminates. The last three instructions
transfer the accumulated sums from registers R3, R4, and R5, into memory
locations SUM1, SUM2, and SUM3, respectively.
Addressing Modes
6. Base with index : The effective address is the sum of the contents of registers Ri and
Rj. The second register is usually called the base register. This form of indexed
addressing provides more flexibility in accessing operands, because both
components of the effective address can be changed.
Additional Addressing Modes ( CISC Arch modes)
7. Relative Addressing Mode: The effective address is determined by the Index
mode using the program counter in place of the general-purpose register Ri.
X(PC) EA = X+ PC
8. Auto increment Mode : The effective address of the operand is the contents of
a register specified in the instruction. After accessing the operand, the
contents of this register are automatically incremented to point to the next
operand in memory. ( Similar to R++) . Denoted by (Ri)+
9. Auto decrement Mode : The contents of a register specified in the instruction
are first automatically decremented and are then used as the effective address
of the operand. ( Similar to - -R ). Denoted by −(Ri)
Additional Addressing Modes ( CISC Arch modes)

Program to add N numbers using auto increment addressing mode.

Shift and Rotate Instructions
There are many applications that require the bits of an operand to be shifted right
or left some specified number of bit positions. For a signed number, we use an
arithmetic shift, which preserves the sign of the number.
1. Logical Shift Left : LShiftL R3, R3, #2
Moves each bit of register R3 ‘n’ position to the left one by one. The MSB bit
is discarded and the empty LSB bit is replaced with zero. Logical shift left
instruction with 1 bit shift will multiply the number by 2.
2. Logical Shift Right : LShiftR R3, R3, #2
Moves each bit of register R3 ‘n’ position to the right one by one. The LSB bit is
discarded and the empty MSB bit is replaced with zero. Logical shift right will
result in dividing the number by 2.
Shift and Rotate Instructions
Shift and Rotate Instructions
3. Arithmetic shift Right : AShiftR R3, R3, #3 Arithmetic
shift right operation shifts signed binary number ‘n’ bit to the right. The LSB bit is
discarded and the empty MSB bit is filled with previous MSB value of the R3(or the sign
of the R3). This operation result in the content of R3 being divided by two.
Note: If the MSB is 0 it means the number is positive. If
the MSB is 1 it means the number is negative. To know the actual binary number you
need to take 2’s complement of R3
Shift and Rotate Instructions
4. Arithmetic Shift Left : AShiftL R2, R2, #2
Arithmetic shift left operation shifts signed binary number ‘n’ bit to the right. The MSB
bit is discarded and the empty MLSB bit is filled zero. This operation result in the
content of R2 being multiplied by two. In case of AShiftL an overflow can occur
and the sign of the number may be lost . In case of 8 bit register, it can store
only numbers in range -127 to +127. If AShiftL result in number not in this range,
overflow is said to occur
5. Rotate Right : RotateR R3, R3, #3
For situations where it is desirable to preserve all of the bits, rotate instructions
may be used instead. RotateR shifts all bits ‘n’ position to the right. The LSB bit
instead of being discarded is placed at the MSB.
Shift and Rotate Instructions
Shift and Rotate Instructions
Shift and Rotate Instructions
6. Rotate Left : RotateL R3, R3, #3
RotateL shifts all bits ‘n’ position to the left. The MSB bit instead of being
discarded is placed at the LSB
7. Rotate right through carry : RotateRC R3, R3, #3
Here after shifting the bits, the LSB instead of being discarded is placed in the
carry flag and the value in carry flag(initially 0 ) is placed at MSB.
8. Rotate left through carry : RotateLC R3, R3, #3
Here after shifting the bits, the MSB instead of being discarded is placed in the
carry flag and the value in carry flag(initially 0 ) is placed at LSB.
Stacks
A stack is a list of data elements, usually words, with the accessing restriction that elements can be added
or removed at one end of the list only. This end is called the top of the stack, and the other end is called the
bottom. The structure is sometimes referred to as a pushdown stack or last-in–first-out (LIFO) stack. A stack
pointer (SP), is used to point to a top of stack (ie, address of top element of stack)at any given time. There
are two operation for a stack:

1. Push Operation: insert element to stack

Subtract SP, SP, #4

Store Rj, (SP)

2. Pop Operation: Remove element from stack

Load Rj, (SP)

Add SP, SP, #4

Stacks
Subroutines
It is often necessary to perform a particular task many times on different data values. This task can be done by
executing a block of instruction multiple times. Such a block of instructions is usually called a subroutine.There are two
operations related to subroutines: ( 1 ) Call and ( 2 ) Return

Whenever Call instruction is executed there is jump to memory location where the subroutine is present all instructions
in subroutines are executed. Last instruction of subroutine is the Return instruction which gives back the control to the
calling program. After the subroutine completes execution the calling program must resume execution, continuing
immediately after the instruction that called the subroutine.

The way in which a computer makes it possible to call and return from subroutines is referred to as its subroutine
linkage method. The simplest subroutine linkage method is to save the return address in a specific location, which may
be a register dedicated to this function. Such a register is called the link register.

The Call instruction is just a special branch instruction that performs the following operations:

● Store the contents of the PC in the link register

● Branch to the target address specified by the Call instruction
Subroutines
The Return instruction is a special branch instruction that performs the operation

● Branch to the address contained in the link register

When instruction Call SUB starts execution, the

content of PC is 204. When processor recognizes it
is CALL statement it stores the content of PC to Link
Register and replaces content of PC to point to first
instruction of Subroutine(ie, SUB). When Return
statement is encountered the content of PC is
loaded with the content of Link Register(ie, 204)
Nested Subroutine
A common programming practice, called subroutine nesting, is to have one subroutine call
another. In this case, the return address of the second call is also stored in the link register,
overwriting its previous contents. Hence, it is essential to save the contents of the link register in
some other location.

The return address needed for this first return is the last one generated in the nested call
sequence. That is, return addresses are generated and used in a last-in–first-out order. This
suggests that the return addresses associated with subroutine calls should be pushed onto the
processor stack.

Correct sequencing of nested calls is achieved if a given subroutine SUB1 saves the return
address currently in the link register on the stack, accessed through the stack pointer, SP, before it
calls another subroutine SUB2. Then, prior to executing its own Return instruction, the subroutine
SUB1 has to pop the saved return address from the stack and load it into the link register.
Nested Subroutine
SUB 1
. SUB 2
Return address of SUB
3 ←SP
. . SUB 3
. . .
Return address
. . Return of SUB 2

. Retun
Retun Return address of
SUB 1
Nested Subroutine : Parameter Passing
When calling a subroutine, a program must provide to the subroutine the parameters, that is, the operands or their
addresses, to be used in the computation. Later, the subroutine returns other parameters, which are the results of the
computation. This exchange of information between a calling program and a subroutine is referred to as parameter
passing.The parameters may be placed in registers or alternatively, the parameters may be placed on the processor
stack.

Passing parameters through processor registers is straightforward and efficient. Consider program to add ‘n’ numbers.
LISTADD function is passed through registers. The size of the list, n, contained in memory location N, and the address,
NUM1, of the first number, are passed through registers R2 and R4. The sum computed by the subroutine is passed
back to the calling program through register R3.

The first two instructions load n and NUM1 into R2 and R4. The Call instruction branches to the subroutine starting at
location LISTADD. This instruction also saves the return address (i.e., the address of the Store instruction in the calling
program) in the link register. The subroutine computes the sum and places it in R3. After the Return instruction is
executed by the subroutine, the sum in R3 is stored in memory location SUM by the calling program. In addition to
registers R2, R3, and R4, which are used for parameter passing, the subroutine also uses R5. Since R5 may be used in
the calling program, its contents are saved by pushing them onto the processor stack upon entry to the subroutine and
restored before returning to the calling program.
Parameter Passing (Through Registers)
Parameter Passing ( Through Stack)
If many parameters are involved, there may not be enough general-purpose registers available for passing them to the
subroutine. The processor stack provides a convenient and flexible mechanism for passing an arbitrary number of
parameters.

Here LISTADDuses the processor stack for parameter passing. The address of the first number in the list and the
number of entries are pushed onto the processor stack pointed to by SP. example. Assume that before the subroutine
is called, the top of the stack is at level 1. The calling program pushes the address NUM1 and the value n onto the stack
and calls subroutine LISTADD. The top of the stack is now at level 2.

The subroutine uses four registers while it is being executed. Since these registers may contain valid data that belong
to the calling program, their contents should be saved at the beginning of the subroutine by pushing them onto the
stack. The top of the stack is now at level 3. The subroutine accesses the parameters n and NUM1 from the stack using
indexed addressing with offset values relative to the new top of the stack (level 3).

At the end of the computation, register R3 contains the sum. Before the subroutine returns to the calling program, the
contents of R3 are inserted into the stack, replacing the parameter NUM1, which is no longer needed. Then the
contents of the four registers used by the subroutine are restored from the stack. Also, the stack pointer is incremented
to point to the top of the stack that existed when the subroutine was called, namely the parameter n at level 2.
Parameter Passing ( Through Stack)
Parameter Passing

In above programs the calling program passes the address of the first number in the list
(NUM1 ). This technique is called passing by reference. The second parameter is passed
by value, that is, the actual number of entries, n, is passed to the subroutine.
Condition Codes
Operations performed by the processor typically generate results such as numbers that are positive, negative, or zero. The processor
can maintain the information about these results for use by subsequent conditional branch instructions. This is accomplished by
recording the required information in individual bits, often called condition code flags. These flags are usually grouped together in a
special processor register called the condition code register or status register. Individual condition code flags are set to 1 or cleared to
0, depending on the outcome of the operation performed.

N (negative) Set to 1 if the result is negative; otherwise, cleared to 0

Z (zero) Set to 1 if the result is 0; otherwise, cleared to 0

V (overflow) Set to 1 if arithmetic overflow occurs; otherwise, cleared to 0

C (carry) Set to 1 if a carry-out results from the operation; otherwise, cleared to 0

The N and Z flags record whether the result of an arithmetic or logic operation is negative or zero.This makes it possible for a later
conditional branch instruction to cause a branch based on the sign and value of the operand that was moved. The V flag indicates
whether overflow has taken place. Overflow occurs when the result of an arithmetic operation is outside the range of values that can
be represented by the number of bits available for the operands. The C flag is set to 1 if a carry occurs from the most-significant bit
position during an arithmetic operation. This flag makes it possible to perform arithmetic operations on operands that are longer than
the word length of the processor.
Encoding of Machine Instructions
Deals with how machine instructions are formed.

1. Register operand form: Add Rdst, Rsrc1, Rsrc2

All 3 operands are registers. If the processor has 32 registers, the number of bits required to
represent each register = 5 ( 2^5 = 32). In case of 32 bit instructions,
the opcode can take 17 bits ( 32 - (3*5) )

2. Immediate-operand format: Add Rdst, Rsrc, #Value

Suppose one operand is in immediate addressing mode, 10 bits required by register

operand. So remaining 22 bits will represent opcode and #value. The most useful sizes of
immediate operands are 32, 16, and 8 bits. Since 32 bits are not available, a good choice is
to allocate 16 bits for the immediate operand. This leaves six bits for specifying the OP code
Encoding of Machine Instructions
2. This format can also be used for Load and Store
instructions:

Load R6, X(R5) ,

X can take 16 bit value/address/offset

Or for branch instruction :

BGT R2, R0, LOOP ,

LOOP can take 16 bit address

3. Call format: CALL ImmediateValue

6 bits for opcode and remaining for address of

subroutine