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Syl 5

Syllabus 5 - Computer System and Architecture

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5 views4 pages

Syl 5

Syllabus 5 - Computer System and Architecture

Uploaded by

Kamarul Ariffin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Designing a Processor

Overview

This teaching note covers the fundamentals of processor design, focusing on different
architectural approaches, components of a simple MIPS processor, datapath design, control
design, and advanced concepts such as pipelining and instruction-level parallelism. The goal is
to provide students with a comprehensive understanding of how processors are designed,
including both basic concepts and more advanced features.

Objectives

1. Understand Non-Von Neumann Architectures: Learn about alternative processor


architectures beyond the traditional Von Neumann model.
2. Explore Simple MIPS Processor Components: Understand the basic components and
operation of a MIPS processor.
3. Design a Datapath for a Simple Processor: Learn how to design a datapath that enables
a processor to execute instructions.
4. Examine Alternative Datapath Designs and Control: Explore alternative approaches to
datapath design and how to design control units for processors.
5. Understand Pipelining and Hazards: Learn about the concept of pipelining in processors
and the types of hazards that can occur.
6. Design a Pipelined Processor: Explore how to design a processor with pipelining to
improve performance.
7. Explore Instruction-Level Parallelism: Understand how processors can execute multiple
instructions in parallel to enhance performance.

1. Non-Von Neumann Architectures

 Von Neumann Architecture:


o Definition: A computer architecture where the CPU, memory, and input/output
devices are connected via a shared bus, and instructions and data are stored in
the same memory.
o Limitation: The Von Neumann bottleneck, where the single data path can
become a performance bottleneck.
 Alternative Architectures:
o Harvard Architecture: Uses separate memory storage and data paths for
instructions and data, allowing simultaneous access to both.
o Dataflow Architecture: Focuses on the flow of data between operations rather
than sequential instruction execution.
o Superscalar Architecture: Allows multiple instructions to be processed in parallel
by using multiple execution units.
o Vector Processors: Designed to handle vector operations efficiently by
processing multiple data points in a single instruction.

2. Simple MIPS Processor Components

 MIPS Architecture Overview:


o Registers: Small, fast storage locations within the CPU, including general-purpose
registers and special-purpose registers.
o ALU (Arithmetic Logic Unit): Performs arithmetic and logical operations.
o Control Unit: Directs the operation of the processor by decoding instructions and
generating control signals.
o Instruction Memory: Stores instructions to be executed.
o Data Memory: Stores data used and generated by instructions.
o Program Counter (PC): Keeps track of the address of the next instruction to
execute.
 Instruction Types:
o R-Type: Register-to-register operations (e.g., addition, subtraction).
o I-Type: Immediate operations (e.g., loading constants, branch instructions).
o J-Type: Jump operations (e.g., unconditional jumps).

3. Designing a Datapath for a Simple Processor

 Datapath Components:
o Registers: For holding intermediate data and results.
o ALU: For performing arithmetic and logical operations.
o Muxes (Multiplexers): For selecting between different data inputs.
o Memory Units: For instruction and data storage.
 Datapath Design:
o Data Flow: Design how data moves through the processor components (e.g.,
from registers to ALU and from ALU to memory).
o Control Signals: Generate and manage the signals needed to control data flow
and operations within the datapath.
o Instruction Execution Cycle: Implement the fetch-decode-execute cycle within
the datapath.
 Example: Design a simple MIPS datapath that supports basic instructions like addition,
subtraction, and loading/storing data.
4. Alternative Approaches to Datapath Design and Control

 Alternative Datapath Designs:


o Single-Cycle Datapath: Executes each instruction in a single clock cycle,
simplifying the design but limiting performance.
o Multi-Cycle Datapath: Breaks instruction execution into multiple stages, allowing
more complex instructions and better utilization of hardware.
 Control Unit Design:
o Hardwired Control: Uses combinational logic to generate control signals based
on the opcode of the instruction.
o Microprogrammed Control: Uses a set of microinstructions stored in memory to
control the datapath, allowing more flexibility in control signal generation.
 Example: Compare single-cycle and multi-cycle datapaths in terms of complexity,
performance, and implementation.

5. Pipelining and Hazards

 Pipelining:
o Concept: Divides instruction execution into several stages (e.g., fetch, decode,
execute, memory access, write-back) to allow overlapping of instructions.
o Stages: Common stages include Instruction Fetch (IF), Instruction Decode (ID),
Execution (EX), Memory Access (MEM), and Write Back (WB).
 Hazards:
o Data Hazards: Occur when instructions that are close together in the pipeline
depend on the same data.
 Read After Write (RAW): When an instruction needs data that has not
yet been written back by a previous instruction.
 Write After Read (WAR): When an instruction writes to a register before
a previous instruction reads from it.
 Write After Write (WAW): When two instructions write to the same
register.
o Control Hazards: Arise from branch instructions, which can alter the flow of
instructions.
o Structural Hazards: Occur when hardware resources are not sufficient to handle
all concurrent operations.
 Handling Hazards:
o Stalling: Introducing delay cycles to resolve hazards.
o Forwarding: Passing data directly between pipeline stages to avoid stalls.
o Branch Prediction: Predicting the outcome of branch instructions to reduce
control hazards.
6. Pipelined Processor

 Design:
o Pipeline Stages: Implement the stages of instruction processing in parallel to
increase throughput.
o Pipeline Registers: Store intermediate data between stages to maintain
separation and synchronization.
 Performance:
o Throughput: Increased by overlapping instruction execution, resulting in higher
instruction per cycle (IPC) rates.
o Cycle Time: May be longer due to the need to balance the stages of the pipeline.
 Example: Design a simple pipelined processor and analyze its performance compared to
a non-pipelined design.

7. Instruction-Level Parallelism (ILP)

 Concept:
o Definition: The ability of a processor to execute multiple instructions
simultaneously.
o Types: Includes data-level parallelism, loop-level parallelism, and instruction-
level parallelism.
 Techniques:
o Superscalar Execution: Allows multiple instructions to be executed per clock
cycle by using multiple execution units.
o Out-of-Order Execution: Executes instructions in a different order than they
appear in the program to optimize resource utilization and performance.
o Speculative Execution: Executes instructions before knowing if they are needed,
based on predictions about branch outcomes.
 Example: Examine how ILP techniques can be applied to improve the performance of a
processor and the trade-offs involved.

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