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Digital Electronics Question and

Answers Page |
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Topic 2

Boolean Algebric and Logic Gates

1.) Boolean Logic Operations

2.) Sum of Products and Products of Sum
3.) Karnaugh Map
4.) Quine McCluskey or Tabular Method of Minimization of
Logic Functions
5.) Logic Gates and Networks – 1
6.) Logic Gates and Networks – 2
7.) Digital Integrated Circuits – 1

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Digital Electronics Question & Answers

Page |
Boolean Algebric and Logic Gates 2

1.) Boolean Logic Operations

1. In boolean algebra, the OR operation is performed by which properties?
a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
Answer: d
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C &
A*(B*C) = (A*B)*C.
The expression for Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.

2. The expression for Absorption law is given by _________

a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A
Answer: a
Explanation: The expression for Absorption Law is given by: A+AB = A.
Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as per 1’s Property).

3. According to boolean law: A + 1 = ?

a) 1
b) A
c) 0
d) A’
Answer: a
Explanation: A + 1 = 1, as per 1’s Property.

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4. The involution of A is equal to _________

a) A
b) A’
c) 1
d) 0 Page |
3
Answer: a
Explanation: The involution of A means double inversion of A (i.e. A”) and is equal to A.
Proof: ((A)’)’ = A
5. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
Answer: d
Explanation: A(A + B) = AA + AB (By Distributive Property) = A + AB (A.A = A By
Commutative Property) = A(1 + B) = A*1 (1 + B = 1 by 1’s Property) = A.

6. DeMorgan’s theorem states that _________

a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
Answer: a
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the
Dual Property.

7. (A + B)(A’ * B’) = ?
a) 1
b) 0
c) AB
d) AB’
Answer: b
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the
Dual Property.

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8. Complement of the expression A’B + CD’ is _________

a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’) Page |
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Answer: b
Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By DeMorgan’s Theorem) = (A” + B’)(C’ + D”) (By
DeMorgan’s Theorem) = (A + B’)(C’ + D).
9. Simplify Y = AB’ + (A’ + B)C.
a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
Answer: a
Explanation: Y = AB’ + (A’ + B)C = AB’ + (AB’)’C = (AB’ + C)( AB’ + AB’) = (AB’ + C).1 = (AB’ +
C).

10. The boolean function A + BC is a reduced form of ____________

a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
Answer: b
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC (By Commutative
Property) = A(1 + C + B) + BC = A + BC (1 + B + C =1 By 1’s Property).

2.) Sum of Products and Products of Sum

1. The logical sum of two or more logical product terms is called __________
a) SOP
b) POS
c) OR operation
d) NAND operation
Answer: a
Explanation: The logical sum of two or more logical product terms, is called SOP (i.e. sum
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of product). The logical product of two or more logical sum terms is called POS (i.e.
product of sums).
2. The expression Y=AB+BC+AC shows the _________ operation.
a) EX-OR Page |
b) SOP 5
c) POS
d) NOR
Answer: b
Explanation: The given expression has the operation product as well as the sum of that.
So, it shows SOP operation. POS will be the product of sum terms.

3. The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.

a) AND
b) POS
c) SOP
d) NAND
Answer: b
Explanation: The given expression has the operation sum as well as the product of that.
So, it shows POS(product of sum) operation. SOP will be the sum of product terms.

4. A product term containing all K variables of the function in either complemented or

uncomplemented form is called a __________
a) Minterm
b) Maxterm
c) Midterm
d) ∑ term
Answer: a
Explanation: A product term containing all K variables of the function in either
complemented or uncomplemented form is called a minterm. A sum term containing all K
variables of the function in either complemented or uncomplemented form is called a
maxterm.

5. According to the property of minterm, how many combination will have value equal to 1
for K input variables?
a) 0
b) 1
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c) 2
d) 3
Answer: b
Explanation: The main property of a minterm is that it possesses the value 1 for only one Page |
combination of K input variables and the remaining will have the value 0. 6

6. The canonical sum of product form of the function y(A,B) = A + B is __________

a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’
Answer: b
Explanation: A + B = A.1 + B.1 = A(B + B’) + B(A + A’) = AB + AB’ + BA +BA’ = AB + AB’ + A’B
= AB + AB’ + A’B.

7. A variable on its own or in its complemented form is known as a __________

a) Product Term
b) Literal
c) Sum Term
d) Word
Answer: b
Explanation: A literal is a single logic variable or its complement. For example — X, Y, A’, Z,
X’ etc.

8. Maxterm is the sum of __________ of the corresponding Minterm with its literal
complemented.
a) Terms
b) Words
c) Numbers
d) Nibble
Answer: a
Explanation: Maxterm is the sum of terms of the corresponding Minterm with its literal
complemented.

9. Canonical form is a unique way of representing ____________

a) SOP

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b) Minterm
c) Boolean Expressions
d) POS
View Answer
Page |
Answer: c 7
Explanation: Boolean Expressions are represented through a canonical form. An example
of canonical form is A’B’C’ + AB’C + ABC’.
10. There are _____________ Minterms for 3 variables (a, b, c).
a) 0
b) 2
c) 8
d) 1
Answer: c
Explanation: Minterm is given by 2n. So, 23 = 8 minterms are required.

11. _____________ expressions can be implemented using either (1) 2-level AND-OR logic
circuits or (2) 2-level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS
Answer: c
Explanation: SOP expressions can be implemented using either (1) 2-level AND-OR logic
circuits or (2) 2-level NAND logic circuits.

3.) Karnaugh Map

1. A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a
matrix of squares.
a) Venn Diagram
b) Cycle Diagram
c) Block diagram
d) Triangular Diagram

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Answer: a
Explanation: A Karnaugh map (K-map) is an abstract form of Venn diagram organized as a
matrix of squares, where each square represents a Maxterm or a Minterm.
2. There are ______ cells in a 4-variable K-map. Page |
a) 12 8
b) 16
c) 18
d) 8
Answer: b
Explanation: There are 16 = (24) cells in a 4-variable K-map.

3. The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ =
1.
a) Impact
b) Non Impact
c) Force
d) Complementarity
Answer: b
Explanation: The given expression A +A’ = 1 is based on non-impact unifying theorem.

4. Each product term of a group, w’.x.y’ and w.y, represents the ____________ in that group.
a) Input
b) POS
c) Sum-of-Minterms
d) Sum of Maxterms
Answer: c
Explanation: In a minterm, each variable w, x or y appears once either as the variable
itself or as the inverse. So, the given expression satisfies the property of Sum of Minterm.
5. The prime implicant which has at least one element that is not present in any other
implicant is known as ___________
a) Essential Prime Implicant
b) Implicant
c) Complement
d) Prime Complement

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Answer: a
Explanation: Essential prime implicants are prime implicants that cover an output of the
function that no combination of other prime implicants is able to cover.
6. Product-of-Sums expressions can be implemented using ___________ Page |
a) 2-level OR-AND logic circuits 9
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits
d) Both 2-level OR-AND and NOR logic circuits
Answer: d
Explanation: Product-of-Sums expressions can be implemented using 2-level OR-AND &
NOR logic circuits.

7. Each group of adjacent Minterms (group size in powers of twos) corresponds to a

possible product term of the given ___________
a) Function
b) Value
c) Set
d) Word
Answer: a
Explanation: Each group of adjacent Minterms (group size in powers of twos) corresponds
to a possible product term of the given function.

8. Don’t care conditions can be used for simplifying Boolean expressions in ___________
a) Registers
b) Terms
c) K-maps
d) Latches
Answer: c
Explanation: Don’t care conditions can be used for simplifying Boolean expressions in K-
maps which helps in pairing with 1/0.

9. It should be kept in mind that don’t care terms should be used along with the terms that
are present in ___________
a) Minterms
b) Expressions

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c) K-Map
d) Latches
Answer: a
Explanation: It should be kept in mind that don’t care terms should be used along with Page |
the terms that are present in minterms as well as maxterms which reduces the complexity 10
of the boolean expression.

10. Using the transformation method you can realize any POS realization of OR-AND with
only.
a) XOR
b) NAND
c) AND
d) NOR
Answer: d
Explanation: Using the transformation method we can realize any POS realization of OR-
AND with only NOR.

11. There are many situations in logic design in which simplification of logic expression is
possible in terms of XOR and _________________ operations.
a) X-NOR
b) XOR
c) NOR
d) NAND
Answer: a
Explanation: There are many situations in logic design in which simplification of logic
expression is possible in terms of XOR and XNOR operations.
Expression of XOR : AB’ + A’B
Expression of XNOR : AB + A’B’

12. These logic gates are widely used in _______________ design and therefore are
available in IC form.
a) Sampling
b) Digital
c) Analog
d) Systems

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Answer: b
Explanation: These logic gates(XOR, XNOR, NOR) are widely used in digital design and
therefore are available in IC form as digital circuits deal with data transmission in the form
of binary digits.
Page |
13. In case of XOR/XNOR simplification we have to look for the following _______________ 11
a) Diagonal Adjacencies
b) Offset Adjacencies
c) Straight Adjacencies
d) Both diagonal and offset adjencies
Answer: d
Explanation: In case of XOR/XNOR simplification we have to look for the following
diagonal and offset adjacencies. XOR gives output 1 when odd number of 1s are present
in input while XNOR gives output 1 when even number of 1s or all 0s are present in input.

14. Entries known as _______________ mapping.

a) Diagonal
b) Straight
c) K
d) Boolean
Answer: a
Explanation: Entries known as diagonal mapping. The diagonal mapping holds true when
for any relation, there is a projection of product on the factor.

4.) Quine McCluskey or Tabular Method of Minimization of

Logic Functions
1. The output of an EX-NOR gate is 1. Which input combination is correct?
a) A = 1, B = 0
b) A = 0, B = 1
c) A = 0, B = 0
d) A = 0, B’ = 1
Answer: c
Explanation: The output of EX-NOR gate is given by AB + A’B’. So, for A = 0 and B = 0 the
output will be 1.

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2. In which of the following gates the output is 1 if and only if at least one input is 1?
a) AND
b) NOR
c) NAND
d) OR Page |
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Answer: d
Explanation: In or gate we need at least one bit to be equal to 1 to generate the output as
1 because OR means any of the condition out of two is equal to 1 which means if at least
one input is 1 then it shows output as 1.

3. The time required for a gate or inverter to change its state is called __________
a) Rise time
b) Decay time
c) Propagation time
d) Charging time
Answer: c
Explanation: The time required for a gate or inverter to change its state is called
propagation time.

4. What is the minimum number of two input NAND gates used to perform the function of
two input OR gates?
a) One
b) Two
c) Three
d) Four
Answer: c
Explanation: Y = A + B. This is the equation of OR gate. We require 3 NAND gates to create
OR gate. We can also write,
1st, 2nd and 3rd NAND operations as: Y = ((NOT A) AND (NOT B))’ = A’’ + B’’ = (A+B).

5. Odd parity of word can be conveniently tested by ___________

a) OR gate
b) AND gate
c) NAND gate
d) XOR gate

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Answer: d
Explanation: Odd parity of word can be conveniently tested by XOR gate, since, XOR
outputs 1 only when the input has odd number of 1’s.
6. The number of full and half adders are required to add 16-bit number is __________ Page |
a) 8 half adders, 8 full adders 13
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders
Answer: b
Explanation: Half adder has two inputs and two outputs whereas Full Adder has 3 inputs
and 2 outputs. One half adder can add the least significant bit of the two numbers
whereas full adders are required to add the remaining 15 bits as they all involve adding
carries.

7. Which of the following will give the sum of full adders as output?
a) Three point major circuit
b) Three bit parity checker
c) Three bit comparator
d) Three bit counter
Answer: d
Explanation: Counters are used for counting purposes in ascending or descending order.
Three bit counter will give the sum of full adders as output.

8. Which of the following gate is known as coincidence detector?

a) AND gate
b) OR gate
c) NOR gate
d) NAND gate
Answer: a
Explanation: AND gate is known as coincidence detector due to multiplicity behaviour, as
it outputs 1 only when all the inputs are 1.

9. An OR gate can be imagined as ____________

a) Switches connected in series
b) Switches connected in parallel

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c) MOS transistor connected in series

d) BJT transistor connected in series
Answer: b
Explanation: OR gate means addition of two inputs, which outputs when any of the input Page |
is high. Due to this reason, it is imagined as switches connected in parallel. 14

10. How many full adders are required to construct an m-bit parallel adder?
a) m/2
b) m
c) m-1
d) m+1
Answer: c
Explanation: We need adder for every bit. So we should need m bit adders. A full adder
adds a carry bit to two inputs and produces an output and a carry. But the most
significant bits can use a half adder which differs from the full adder as in that it has no
carry input, so we need m-1 full adders and 1 half adder in m bit parallel adder.

5.) Logic Gates and Networks – 1

1. The output of a logic gate is 1 when all the input are at logic 0 as shown below:

INPUT OUTPUT

A B C

0 0 1

0 1 0

1 0 0

1 1 0

INPUT OUTPUT

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A B C

0 0 1
Page |
0 1 0 15

1 0 0

1 1 1

The gate is either _________

a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
Answer: d
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is NOR.
The output of a logic gate is 1 when all inputs are at logic 0 or all inputs are at logic 1, then
it is EX-NOR. (The truth tables for NOR and EX-NOR Gates are shown in the above table).

2. The code where all successive numbers differ from their preceding number by single bit is
__________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Answer: d
Explanation: The code where all successive numbers differ from their preceding number
by single bit is gray code. It is an unweighted code. The most important characteristic of
this code is that only a single bit change occurs when going from one code number to
next. BCD Code is one in which decimal digits are represented by a group of 4-bits each,
whereas, in Excess-3 Code, the decimal numbers are incremented by 3 and then written in
their BCD format.

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3. The following switching functions are to be implemented using a decoder:

f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line Page |
16
c) 4 to 16 line
d) 5 to 32 line
Answer: c
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

4. How many AND gates are required to realize Y = CD + EF + G?

a) 4
b) 5
c) 3
d) 2
Answer: d
Explanation: To realize Y = CD + EF + G, two AND gates are required and two OR gates are
required.

5. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
Answer: a
Explanation: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option
will be 00.

6. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
Answer: a
Explanation: Y = CD + EF + G

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The number of two input AND gate = 2

The number of two input OR gate = 2.
7. A universal logic gate is one which can be used to generate any logic function. Which of
the following is a universal logic gate? Page |
a) OR 17
b) AND
c) XOR
d) NAND
Answer: d
Explanation: An Universal Logic Gate is one which can generate any logic function and also
the three basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic
function and are thus Universal Logic Gates.
8. A full adder logic circuit will have __________
a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
Answer: d
Explanation: A full adder circuit will add two bits and it will also accounts the carry input
generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are
there. In case of half adder circuit, there are only two inputs bits and two outputs (SUM
and CARRY).

9. How many two input AND gates and two input OR gates are required to realize Y = BD +
CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
Answer: a
Explanation: There are three product terms. So, three AND gates of two inputs are
required. As only two input OR gates are available, so two OR gates are required to get
the logical sum of three product terms.

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10. Which of the following are known as universal gates?

a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR Page |
18
Answer: a
Explanation: The NAND & NOR gates are known as universal gates because any digital
circuit can be realized completely by using either of these two gates, and also they can
generate the 3 basic gates AND, OR and NOT.

11. The gates required to build a half adder are __________

a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
Answer: c
Explanation: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR
outputs the SUM of the two input bits whereas AND outputs the CARRY of the two input
bits.

6.) Logic Gates and Networks – 2

1. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
Answer: c
Explanation: A transistor can be used as a switch. That is when base is low collector is high
(input zero, output one) and base is high collector is low (input 1, output 0).

2. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16

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Answer: d
Explanation: For 4 inputs: 24 = 16 truth table entries are necessary.
3. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH Page |
b) At least one input is LOW 19
c) All inputs are HIGH
d) All inputs are LOW

Answer: c
Explanation: For AND gate, the output is high only when both inputs are high. That’s why
the high output in AND will occurs only when all the inputs are high. However, in case of
OR gate, if atleast one input is high, the output will be high.
4. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates
Answer: c
Explanation: Expression for XOR is: A.(B’)+(A’).B
So in the above expression, the following logic gates are used: AND, OR, NOT.
Thus, 2 AND gates with two-inputs and 1 OR gate with two-inputs will be required for
constructing a XOR gate.

5. The basic logic gate whose output is the complement of the input is the ___________
a) OR gate
b) AND gate
c) INVERTER gate
d) XOR gate
View Answer
Answer: c
Explanation: It is also called NOT gate and it simply inverts the input, such that 1 becomes
0 and 0 becomes 1.
6. The AND function can be used to ___________ and the OR function can be used to
_____________
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a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
Page |
Answer: a 20
Explanation: The AND gate and OR gate are used for enabling and disabling respectively
because of their multiplicity and additivity property. The AND gate outputs 1 when all
inputs are at logic 1, whereas the OR gate outputs 0 when all inputs are at logic 0.
7. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR
Answer: a
Explanation: The dependency notation “>=1” inside a block stands for OR operation.

8. If we use an AND gate to inhibit a signal from passing one of the inputs must be
___________
a) LOW
b) HIGH
c) Inverted
d) Floating
Answer: a
Explanation: AND gate means A*B and OR gate means A+B and to inhibit means to get
low signal, one of the input must be low. It means (0*1=0 or 1*0=0) we will get low
output signal. Thus, AND gate outputs 1 only when all inputs are at logic level 1 else it
outputs 0.

9. Logic gate circuits contain predictable gate functions that open theirs ____________
a) Outputs
b) Inputs
c) Pre-state
d) Impedance state
Answer: b
Explanation: Logic gate circuits contain predictable gate functions that open their inputs
because we are free to give any types of inputs.
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10. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8 Page |
21
Answer: c
Explanation: 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for
+vcc and remaining pins used for connections. For a NAND gate two inputs are required
and one output is obtained means for NAND gate 3 pin connections are required. Thus, a
7400IC contains 4 NAND gates with each having 3 pins. Therefore, total 12 pins dedicated
for the NAND operation. Rest 2 pins for power supply.

7.) Digital Integrated Circuits

1. Which of the following logic families has the highest maximum clock frequency?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS
Answer: b
Explanation: AS-TTL (Advanced Schottky) has a maximum clock frequency of 105 MHz. S-
TTL (Schottky High Speed TTL) has 100 MHz. Found nothing as HS-TTL. There are H and S
separate TTL. HCMOS has 50 MHz clock frequency.
2. Why is the fan-out of CMOS gates frequency dependent?
a) Each CMOS input gate has a specific propagation time and this limits the number of
different gates that can be connected to the output of a CMOS gate
b) When the frequency reaches the critical value the gate will only be capable of delivering
70% of the normal output voltage and consequently the output power will be one-half of
normal and this defines the upper operating frequency
c) The higher number of gates attached to the output the more frequently they will have to
be serviced thus reducing the frequency at which each will be serviced with an input signal
d) The input gates of the FETs are predominantly capacitive and as the signal frequency
increases the capacitive loading also increases thereby limiting the number of loads that
may be attached to the output of the driving gate

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Answer: d
Explanation: Fan out is the measure of maximum number of inputs that a single logic gate
output can drive. Actually power dissipation in CMOS circuits depends on clock frequency.
As the frequency increases Pd also increases so fan-out depends on frequency.
Page |
3. Logic circuits that are designated as buffers, drivers or buffers/drivers are designed to 22
have _______________
a) A greater current/voltage capability than an ordinary logic circuit
b) Greater input current/voltage capability than an ordinary logic circuit
c) A smaller output current/voltage capability than an ordinary logic
d) Greater the input and output current/voltage capability than an ordinary logic circuit
Answer: a
Explanation: Buffer circuits are usually incorporated to isolate the input from the output.
Logic circuits that are designated as buffers, drivers or buffer/drivers are designed to have
a greater current/voltage capability than an ordinary logic circuit

4. Which of the following will not normally be found on a data sheet?

a) Minimum HIGH level output voltage
b) Maximum LOW level output voltage
c) Minimum LOW level output voltage
d) Maximum HIGH level input current
Answer: c
Explanation: Minimum LOW level output voltage will not normally be found on a data
sheet.

5. Which of the following logic families has the shortest propagation delay?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS
Answer: b
Explanation: AS-TTL (Advanced Schottky) has a maximum clock frequency that is 105
MHz. So, the propagation delay will be given by 1/105 sec which is the lowest one. It is
followed by S-TTL and HCMOS in terms of increasing propagation delay.

6. What is the static charge that can be stored by your body as you walk across a carpet?
a) 300 volts
b) 3000 volts
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c) 30000 volts
d) Over 30000 volts
Answer: d
Explanation: When a person walks across a carpeted or tile floor electric charge builds up Page |
in the body due to the friction between shoes and floor material. If the friction static is 23
greater the voltage potential develop in the body will be greater. You start act as a
capacitor. This is called Electrostatic discharge. The potential static charge that can
develop from walking on tile floors is greater than 15000 volts while carpeted floors can
generate in excess of 30000 volts.

7. What must be done to interface TTL to CMOS?

a) A dropping resistor must be used on the CMOS of 12 V supply to reduce it to 5 V for the
TTL
b) As long as the CMOS supply voltage is 5 V they can be interfaced (however, the fan-out of
the TTL is limited to five CMOS gates)
c) A 5 V zener diode must be placed across the inputs of the TTL gates in order to protect
them from the higher output voltages of the CMOS gates
d) A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the
value of RP will depend on the number of CMOS gates connected to the node
Answer: d
Explanation: To interface TTL to CMOS a pull-up resistor must be used between the TTL
output-CMOS input node and Vcc. A pull-up resistor is used to avoid the floating state on
the input node of the CMOS, thus using a small amount of current. The value of RP will
depend on the number of CMOS gates connected to the node.

8. What causes low-power Schottky TTL to use less power than the 74XX series TTL?
a) The Schottky-clamped transistor
b) A larger value resistor
c) The Schottky-clamped MOSFET
d) A small value resistor
Answer: b
Explanation: A larger value resistor causes low power low-power Schottky TTL to use less
power than the 74XX series TTL.

9. What are the major differences between the 5400 and 7400 series of ICs?
a) The 5400 series are military grade and require tighter supply voltages and temperatures
b) The 5400 series are military grade and allow for a wider range of supply voltages and
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temperatures
c) The 7400 series are an improvement over the original 5400s
d) The 7400 series was originally developed by Texas Instruments and the 5400 series was
brought out by National Semiconductors after TI’s patents expired as a second supply
source Page |
24
Answer: b
Explanation: The 5400 series are military grade and allow for a wider range of supply
voltages and temperatures, these are the major differences between the 5400 and 7400
series of ICs. Also, the working temperature range of 5400 series is -50 to 125C while that
for 7400 is 0 to 70C.
10. Which of the following statements apply to CMOS devices?
a) The devices should not be inserted into circuits with the power on
b) All tools, test equipment and metal workbenches should be tied to earth ground
c) The devices should be stored and shipped in antistatic tubes or conductive foam
d) All of the Mentioned
Answer: d
Explanation: For CMOS devices, all the mentioned statements are applicable. The devices
should not be inserted into circuits with the power on. All tools, test equipment and
metal workbenches should be tied to earth ground. Also, the devices should be stored
and shipped in antistatic tubes or conductive foam.

11. SSI refers to ___________

a) Small Scale Integration
b) Short Scale Integration
c) Small Set Integration
d) Short Set Integration
Answer: a
Explanation: SSI refers to Small Scale Integration.

12. Small Scale Integration(SSI) refers to ICs with __________ gates on the same chip.
a) Fewer than 10
b) Greater than 10
c) Equal to 10
d) Greater than 50
Answer: a

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Explanation: Small Scale Integration(SSI) refers to ICs with fewer than 10 gates on the
same chip.
13. MSI means ___________
a) Merged Scale Integration Page |
b) Main Scale Integration 25
c) Medium Scale Integration
d) Main Set Integration
Answer: c
Explanation: MSI means Medium Scale Integration.

14. MSI includes _______ gates per chip.

a) 12 to 100
b) 13 to 50
c) greater than 10
d) greater than 100
Answer: a
Explanation: Medium Scale Integration includes 12 to 100 gates per chip.

15. LSI means ________ and refers to ________ gates per chip.
a) Long Scale Integration, more than 10 upto 10000
b) Large Scale Integration, more than 100 upto 5000
c) Large Short Integration, less than 10 and greater than 5000
d) Long Short Integration, more than 10 upto 10000
Answer: b
Explanation: The full form of LSI is Large Scale Integration and refers to more than 100
upto 5000 gates per chip.

16. Integrated circuits are classified as ___________

a) Large, Small and Medium
b) Very Large, Small and Linear
c) Linear and Digital
d) Non-Linear and Digital
Answer: c
Explanation: Integrated circuits are classified as Linear and Digital. Linear operates with
continuous and digital refers to discrete signals.

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17. According to the IC fabrication process logic families can be divided into two broad
categories as ___________
a) RTL and TTL
b) HTL and MOS
c) ECL and DTL Page |
26
d) Bipolar and MOS
Answer: d
Explanation: According to the IC fabrication process logic families can be divided into two
broad categories as: Bipolar and Metal-oxide semiconductor. The mentioned all others are
part of bipolar. Bipolar IC fabrication refers to TTL logic where MOS refers to CMOS logic.

18. The full form of DIP is ___________

a) Dual-in-Long Package
b) Dual-in-Line Package
c) Double Integrated Package
d) Double-in-Line Package
Answer: b
Explanation: The full form of DIP is Dual-in-Line Package.

19. LCC refers to ___________

a) Longest Chip Carrier
b) Leadless Chip Carrier
c) Leaded Chip Carrier
d) Large Chip Carrier
Answer: b
Explanation: LCC refers to Leadless Chip Carrier.

20. PGA refers to ____________

a) Plastic Grid Array
b) Pin Grid Array
c) Pin Greater Array
d) Plastic Greater Array
Answer: b
Explanation: PGA refers to Pin Grid Array.

21. MOS families includes __________

a) PMOS and NMOS
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b) CMOS and NMOS

c) PMOS, NMOS and CMOS
d) EMOS, NMOS and PMOS
Answer: c
Explanation: Metal Oxide Semiconductor families includes PMOS, NMOS and CMOS. Page |
27
22. CMOS refers to __________
a) Continuous Metal Oxide Semiconductor
b) Complementary Metal Oxide Semiconductor
c) Centred Metal Oxide Semiconductor
d) Concrete Metal Oxide Semiconductor
Answer: b
Explanation: CMOS refers to Complementary Metal Oxide Semiconductor.
23. Propagation delay is defined as __________
a) the time taken for the output of a gate to change after the inputs have changed
b) the time taken for the input of a gate to change after the outputs have changed
c) the time taken for the input of a gate to change after the intermediates have changed
d) the time taken for the output of a gate to change after the intermediates have changed
Answer: a
Explanation: Propagation delay is defined as the time taken for the output of a gate to
change after the inputs have changed.

24. Propagation delay times can be divided as __________

a) t(PLH) and t(LPH)
b) t(LPH) and t(PHL)
c) t(PLH) and t(PHL)
d) t(HPL) and t(LPH)
Answer: c
Explanation: Propagation delay times can be divided as: t(PLH) and t(PHL). t(PLH) stands
for propagation from low to high and t(PHL) stands for propagation from high to low.

25. The delay times are measured between the __________ % voltage levels of the input
and output waveforms.
a) 50
b) 75
c) 25
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d) 100
Answer: a
Explanation: Propagation delay is the time taken by the output to change it’s state when
the input changes. The average of the two propagation delays is given by (t1 + t2)/2,
which gives the intermediate value. So, the delay times are measured between the 50% Page |
28
voltage levels of the input and output waveforms.

26. Power Dissipation in DIC is expressed in __________

a) Watts or kilowatts
b) Milliwatts or nanowatts
c) DB
d) Mdb
Answer: b
Explanation: Power Dissipation in DIC is expressed in milliwatts or nanowatts.

27. Fan-in is defined as __________

a) the number of outputs connected to gate without any degradation in the voltage levels
b) the number of inputs connected to gate without any degradation in the voltage levels
c) the number of outputs connected to gate with degradation in the voltage levels
d) the number of inputs connected to gate with degradation in the voltage levels
Answer: b
Explanation: Fan-in is defined as the maximum number of inputs that can be connected to
the output of a gate without any degradation in the voltage levels. For example, an eight-
input gate requires one Unit Load per input. It’s fan-in is 8.

28. The maximum noise voltage that may appear at the input of a logic gate without
changing the logical state of its output is termed as __________
a) Noise Margin
b) Noise Immunity
c) White Noise
d) Signal to Noise Ratio
Answer: b
Explanation: The maximum noise voltage that may appear at the input of a logic gate
without changing the logical state of its output is termed as noise immunity.

29. Depending upon the flow of current from the output of one logic circuit to the input of
another the logic families can be divides into _________ categories.
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a) 2
b) 3
c) 4
d) 5
Answer: a Page |
29
Explanation: Depending upon the flow of current from the output of one logic circuit to
the input of another the logic families can be divides into two categories and they are
current sourcing and current sinking. Source means from where the current originates or
exits while Sink means where the current enters or is accepted.

30. Fan-in and Fan-out are the characteristics of ___________

a) Registers
b) Logic families
c) Sequential Circuits
d) Combinational Circuits
Answer: b
Explanation: Fan-in and Fan-out are the characteristics of logic families. Fan-in is the
measure of maximum number of inputs that a single gate output can drive or accept.
Whereas, Fan-out means the maximum number of inputs that can be fed by a single
output.

1) Write the POS from for a 3-input XNOR gate? Is it canonical?

Answer:

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30

2. Why do we write 00 01 11 10 in that order while Drawing K-maps?

Answer:
In K-Map, the Boolean simplification is done by grouping the adjacent cells that have 1. To
get the simplified expression, the adjacent cells must have 1 bit change. So gray code is
used.

3. How many cells will a n-input variable have in K-Map?

Answer:
2n. E.g.: 3 variables, 8 cells. Similarly..4 variables 16 cells.

4. Y = A'C + AC'B' and you are given that A=C=1 will never occur. Simplify Y?
Answer:
Y = A'C + AC'B' and the output will be don’t care for A = C = 1. So the K-map will be as
follows:

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31

Thus the simplified expression for Y is AB’ + C

5. If F(A,B,C,D,E) = B’E, how many terms will be there in the standard or canonical SOP
representation of F?
Answer:
8 terms, F = B’E (A + A’) (C+C’) (D+D’)
Q14) In a 6 variable K-map, how many literals will the grouping of 4 adjacent cells give in the
term
Answer:
6 – log24 = 6-2 = 4

6. In the simplification of a Boolean function, F = ∑ (0,1,2,6,7,8,9,10,14,15) using QM

method the following table is obtained: Q1) Define: SOP from and POS form?

Answer:
Checkout for the columns which has only one entry (X), that term must be included in the
simplified expression. So, that term will be essential.
(a) So the essential prime implicants are: BC and B’C’

(b) The simplified expression F = BC + B’C’ + CD’ = BC + B’C’ + B’D’

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