Interrupts:

 Interrupt is signals send by an external device to the processor, to request the

processor to perform a particular task or work.
 Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.
 The processor will check the interrupts always at the 2nd T-state of last machine
cycle.
 If there is any interrupt it accept the interrupt and send the INTA (active low) signal to
the peripheral.
 The vectored address of particular interrupt is stored in program counter.
 The processor executes an interrupt service routine (ISR) addressed in program
counter.
 It returned to main program by RET (Return) instruction.

Types of Interrupts:
It supports two types of interrupts.
1. Hardware
2. Software

1. Software interrupts:
 The software interrupts are program instructions. These instructions are inserted at
desired locations in a program.
 The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for
these interrupts can be calculated as follows.
 Interrupt number * 8 = vector address
 For RST 5,5 * 8 = 40 = 28H
 Vector address for interrupt RST 5 is 0028H

Table - Vector addresses of all interrupts.

 2. Hardware interrupts:
 An external device initiates the hardware interrupts and placing an appropriate signal
at the interrupt pin of the processor.
 If the interrupt is accepted then the processor executes an interrupt service routine.

The 8085 has five hardware interrupts

(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR

(1)TRAP:
 This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt
enable.
 TRAP bas the highest priority and vectored interrupt.
 TRAP interrupt is edge and level triggered. This means that the TRAP must go high
and remain high until it is acknowledged.
 In sudden power failure, it executes a ISR and send the data from main memory to
backup memory.
 The signal, which overrides the TRAP, is HOLD signal. (i.e., if the processor receives
HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is
recognized).
 There are two ways to clear TRAP interrupt.
1. By resetting microprocessor (External signal)
2. By giving a high TRAP ACKNOWLEDGE (Internal signal)
(2)RST 7.5:
 The RST 7.5 interrupt is a maskable interrupt.
 It has the second highest priority.
 It is edge sensitive. i.e. Input goes to high and no need to maintain high state until it
recognized.
 Maskable interrupt.
 It is disabled by,
1. DI (Disable Interrupt System) instruction
2. System or processor reset.
3. After reorganization of interrupt.
 Enabled by EI (Enable Interrupt System) instruction.

(3)RST 6.5 and 5.5:

 The RST 6.5 and RST 5.5 both are level triggered. . ie. input goes to high and stay
high until it recognized.
 Maskable interrupt. It is disabled by,
1. DI, SIM instruction
2. System or processor reset.

3. After reorganization of interrupt.

4. Enabled by EI instruction.

5. The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

(4)INTR:
 INTR is a maskable interrupt. It is disabled by,
1. DI, SIM instruction
 2. System or processor reset.
3. After reorganization of interrupt
 Enabled by EI instruction.
 Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the
address of ISR.
 It has lowest priority.
 It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain
high state until it recognized.

The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active
low interrupt acknowledge signal, if the interrupt is enabled.
3. In response to acknowledge signal, external logic places an instruction OPCODE
on the data bus. In the case of multi byte instruction, additional interrupt
acknowledge machine cycles are generated by the 8085 to transfer the additional
bytes into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on stack
and execute received instruction.

SIM and RIM for interrupts:

 The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using
SIM instruction.
 The status of these interrupts can be read by executing RIM instruction.
 The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be
performed by moving an 8-bit data to accumulator and then executing SIM
instruction.

Fig - 8 bit data to be loaded into the Accumulator

 The status of pending interrupts can be read from accumulator after executing RIM
instruction.
 When RIM instruction is executed an 8-bit data is loaded in accumulator, which can
be interpreted as shown in fig.

Fig - Format of 8 bit data in Accumulator after executing RIM Instruction

 Microprocessor - 8086 Pin Configuration

8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip.

8086 Pin Diagram

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.

Clock signal

Clock signal is provided through Pin-19. It provides timing to the processor for operations.
Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order
byte data and AD8AD15 carries higher order byte data. During the first clock cycle, it
carries 16-bit address and after that it carries 16-bit data.

Address/status bus A16-A19/S3-S6. These are the 4 address/status buses. During the first
clock cycle, it carries 4-bit address and later it carries status signals.

S7/BHE

BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of
data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.
Read($\overline{RD}$)

It is available at pin 32 and is used to read signal for Read operation.

Ready

It is available at pin 32. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.

RESET

It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.

INTR

It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt
or not.

NMI

It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.

$\overline{TEST}$

This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.

MN/$\overline{MX}$

It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-aversa.

INTA

It is an interrupt acknowledgement signal and id available at pin 24. When the

microprocessor receives this signal, it acknowledges the interrupt.
ALE

It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.

DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286.
The transreceiver is a device used to separate data from the address/data bus.

DT/R

It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction
of data flow through the transreceiver. When it is high, data is transmitted out and vice-a-
versa.

M/IO

This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at
pin 28.

WR

It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.

HLDA

It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.

HOLD

This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide the
status of instruction queue. Their conditions are shown in the following table −
 QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2

These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27,
and 28. Following is the table showing their status −

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive
LOCK

When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin
29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends acknowledgment.
RQ/GT0 has a higher priority than RQ/GT1.