Digital Design
(ECE/EEE/INSTR F215 )
Verilog sequential
Prof. Anita Agrawal
BITS-Pilani, K.K.Birla Goa campus
16-11-23
Classes of signals
◉ Each signal in verilog belongs to one of the two
classes,
- net
-register
◉ Nets represent physical connection between
hardware elements.
◉ They do not have any storage capacity and their
values are either determined by the values of the
drivers (signal sources) or by high impedance
(when the net is not connected to any driver).
16-Nov-23 Prof.Anita Agrawal 2
ECE/EEE/INSTR F215
◉ Registers, on the other hand, are able to
store values even when disconnected.
◉ Formerly assigned values are kept until a
new value is assigned.
16-Nov-23 Prof.Anita Agrawal 3
registers play the same role as variable in programming languages. ECE/EEE/INSTR F215
◉Nets or registers can be declared as vectors
(multiple bit widths)
◉If the bit width is not specified, the default is scalar
(1-bit)
Vectors
◉Vectors can be declared as:
[ high#:low# ] or
[ low#:high# ]
reg [255:0] data1;
reg [0:255] data2;
Behavioral modeling
Behavioral modeling
◉ The designers do not unnecessarily think in terms
of logic gates or data flow, but in terms of the
algorithm that they wish to implement in the
hardware.
◉They are more concerned about the behavior of
the algorithm and its performance
It’s the highest level of abstraction………
Behavioral modeling
◉ Uses two structured procedure statements:
- initial
- always
◉The statements initial and always cannot be
nested
◉It is a concurrent programming language .
◉Each activity flow starts at simulation time 0.
It’s a procedural language. . Similar to C language constructs
initial
◉All statements inside an initial statement constitute
an initial block
◉Executes exactly once during simulation.
◉Starts at time 0.
◉Multiple initial blocks: All start executing
concurrently at time 0
◉Each block finishes execution independently of
another
◉If more than one statement, should be grouped
using ‘begin’ and ‘end’ keywords
If only one statement grouping is not necessary
module example_initial;
reg a,b,c,x,y;
initial
x= 1’b0; //single statement does not need to be grouped
initial
begin
#5 a=1’b1; // multiple statements need to be grouped
#20 b=2’b01;
end
initial
begin
#10 x=1’b1;
#20 y=1’b0;
end 16-Nov-23
Initial…..contd
initial
#50 $finish;
endmodule
16-Nov-23
always statement
◉All behavioral statements inside an always
statement constitute an always block.
◉It starts at time 0 and executes all the statements
continuously in a looping fashion
always contd…..
◉Two operators:
delay control
event control
◉ Delay control waits for certain time
◉ Event control waits for certain event
◉ General form of event control is:
always@ (event control expression)
begin
//procedural statements
end
Event control expression is also called sensitivity list
Refer section 5.6 DD fourth edition
◉A procedural statement is an assignment of a
logic value to a variable within an initial or always
statement.
◉Statements within an always block execute
sequentially from top to bottom
◉ always @ (A or B or C)
will initiate execution if a change appears in A or
B or C.
◉In Procedural assignments, the value placed on a
variable will remain unchanged until another
procedural assignment updates the variable with a
different value.
◉In Data flow, one assignment statement can cause
the value of the right hand expression to be
continuously placed onto the left-hand side net.
◉always@ (posedge clock)
◉ always@ (negedge clock)
Types of procedural statements
◉Blocking (=)
◉Non-Blocking (<=)
◉Blocking: executed sequentially in the order in
which they are listed in a block of statements
◉Non-Blocking: executed concurrently by
evaluating the set of expressions on the RHS of the
list of assignments.
◉They do not make assignments to their LHS until
all the expressions are evaluated
Examples
◉B=A
◉ C = B+1
◉B<= A
◉C<=B+1
Blocking used in combinational (level sensitive) usually and non-blocking in edge triggering (concurrent)
Port declarations
◉All port declarations are implicitly declared as wire
in Verilog.
◉Three types of ports: input, output, inout
◉Input or inout port is normally declared as wire.
◉But if output ports hold their value, they must be
declared as reg.
◉For ex. In case of d –ff, we want the output q to
retain its value till the next positive edge of the
clock.
◉ so the declaration is as follows:
◉ output q;
◉ reg q;
◉Ports of the type input or inout cannot be declared
as reg, because they are not suppose to store the
values but only reflect the changes in the external
signals they are connected to.
◉Verilog allows constants to be defined by using
the keyword ’parameter’
◉ Parameter cannot be used as variable
D-FF
module dff(q,d,clk,reset);
input d,clk,reset;
output q;
reg q;
always@(negedge clk)
if(reset)
q <=1'b0;
else
q <=d;
endmodule
module ringcounter(q,clk,clr);
input clk,clr;
output [3:0]q;
reg [3:0]q;
always @(negedge clk)
if(clr==1)
q<=4'b1000;
else
begin
q[3]<=q[0];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule
