Scribd
Upload
5 views12 pages

Lab 1 Adder

Uploaded by

pranil shah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
5 views12 pages

Lab 1 Adder

Uploaded by

pranil shah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 12

B.E.

Electronics and Communication Semester V


VLSI Design (BTEC13404)
VLSI Design (3151105)
Adder in Verilog

Enrolment Number - Pranil Shah

Name of Student - ET22BTEC046

Aim - Write VERILOG code for Full adder. Use the VERILOG code of full adder as a
component. Using Structural methodology, write VERILOG code for 4-bit adder and 8-bit adder.
Show output with at least four combinations of input in single waveform for 8-bit adder.
Implement 8-bit adder subtractor with mode control using a behavioral method.
Measure synthesis delay and resource utilization for 4 bit as well as 8 bit adder.

Note: For output node, use notation as Y_initials of your name. i.e. Y_NNS ,Y_KCP, Y_CHP
=====================================================================

Draw and paste Circuit of Full Adder Here (Draw on paper, write enrolment number and paste)
Code of Full Adder

module Adder(A,B,Cin,Sum_ps,Cout);

input A,B,Cin;

output Sum_ps,Cout;

wire c1,c2,c3;

xor(Sum_ps, A, B, Cin);

and(c1,A,B);

and(c2,B, Cin);

and(c3,A,Cin);

or(Cout,c1,c2,c3);

Endmodule

Output of Full adder (all combinations of input in single waveform)


RTL Schematic

Draw and paste diagram of 4bit Adder Here (Draw on paper, write enrolment number and paste)
Code of 4bit Full Adder using RCA or any other method

module FA_RCA4bit(

input [3:0] A,

input [3:0] B,

input c0,

output [3:0] Sum_PS,

output Cout_PS

);

wire c1,c2,c3;

FA_PS fa1(A[0],B[0],c0,Sum_PS[0],c1);

FA_PS fa2(A[1],B[1],c1,Sum_PS[1],c2);

FA_PS fa3(A[2],B[2],c2,Sum_PS[2],c3);

FA_PS fa4(A[3],B[3],c3,Sum_PS[3],Cout_PS);

endmodule
Output of 4bit Full adder (at least four combinations of input in single waveform)

RTL Schematic

Draw and paste Circuit of 8bit Adder Here (Draw on paper, write enrolment number and paste)
Code of 8bit Full Adder using RCA or any other method

module FA_RCA8bit(

input [7:0] A,

input [7:0] B,

input c0,

output [7:0] Sum_PS,

output Cout_PS

);

wire c1;

FA_RCA4bit fa1(A[3:0],B[3:0],c0,Sum_PS[3:0],c1);

FA_RCA4bit fa2(A[7:4],B[7:4],c1,Sum_PS[7:4],Cout_PS);

endmodule
Output of 8bit Full adder (at least four combinations of input in single waveform)

RTL Schematic

Draw and paste Circuit of Adder subtractor with mode control Here (Draw on paper, write
enrolment number and paste)
Code - 8-bit adder subtractor with mode control using a behavioral modeling

module FAS_8bit(
input [7:0] A,
input [7:0] B,
input M,
output [7:0] S_PS,
output C_PS
);
wire c0,c1,c2,c3,c4,c5,c6,c7;
wire z0,z1,z2,z3,z4,z5,z6,Z7;
xor(z0,B[0],M);
xor(z1,B[1],M);
xor(z2,B[2],M);
xor(z3,B[3],M);
xor(z4,B[4],M);
xor(z5,B[5],M);
xor(z6,B[6],M);
xor(z7,B[7],M);

FA_PS fas1(A[0],z0,M,S_PS[0],c1);
FA_PS fas2(A[1],z1,c1,S_PS[1],c2);
FA_PS fas3(A[2],z2,c2,S_PS[2],c3);
FA_PS fas4(A[3],z3,c3,S_PS[3],c4);
FA_PS fas5(A[4],z4,c4,S_PS[4],c5);
FA_PS fas6(A[5],z5,c5,S_PS[5],c6);
FA_PS fas7(A[6],z6,c6,S_PS[6],c7);
FA_PS fas8(A[7],z7,c7,S_PS[7],C_PS);
endmodule

Output - 8-bit adder subtractor with mode control (at least four combinations of input in single
waveform)

RTL Schematic
Synthesis delay

4-bit RCA 6.313 I/O= 5% and LUT=1%

8-bit RCA 7.933 I/O= 13% and LUT=1%

8-bit Adder Subtractor using 5.460 I/O= 25% and LUT=1%


Mode control

Write answers to the following Questions in short. (Write on paper and submit scan copy here)

(1) Write difference between ripple carry adder and carry look ahead adder.
(2) Why is hardware description language used in circuit design?
(3) Why are languages like C, C++ or JAVA not used in circuit design?
(4) Define Synthesis.
Comment/conclusion:-

VERILOG code for Full adder is verified.

Using Structural methodology, VERILOG code for 4-bit adder and 8-bit adder is verified and

output is also implemented. Synthesis delay and resource utilization are described in the table.

Using a behavioral methodology, 8-bit adder subtractor with mode control is verified and output

is also implemented. Synthesis delay and resource utilization are described in the table.

You might also like