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Lab 7 - Memory

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15 views5 pages

Lab 7 - Memory

Uploaded by

pranil shah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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B.E.

Electronics and Communication Semester V


VLSI Design (BTEC13404)
VLSI Design (3151105)
Lab Memory

Enrolment Number - ET22BTEC046

Name of Student - Pranil Shah

Aim: Write VERILOG code for 8×8-bit ROM with predefined data. Demonstrate reading of data
with random/sequential address.

Write VERILOG code for 16x8bit RAM. Demonstrate writing as well as reading of data with
random address.

For ROM
(1) Paste Verilog Code here
module LAB_ROM(
input clk,
input en,
input read,
input [3:0] addr,
output [15:0] out_data_ps
);
reg [15:0] rom [15:0];
reg [15:0] data;
initial begin
rom[0]=16'h5601;
rom[1]=16'h3401;
rom[2]=16'h1801;
rom[3]=16'h0ac1;
rom[4]=16'h0521;
rom[5]=16'h0221;
rom[6]=16'h5601;
rom[7]=16'h5401;
rom[8]=16'h4801;
rom[9]=16'h3801;
rom[10]=16'h3001;
rom[11]=16'h2401;
rom[12]=16'h1c01;
rom[13]=16'h1601;
rom[14]=16'h5601;
rom[15]=16'h5401;
end
always@(posedge clk)
begin
if(!en)
data <=16'h0000;
else if(read)
data <= rom[addr];
end
assign out_data_ps = data;
endmodule

(2) Paste RTL Diagram here

(3) Output Waveform showing all data read using a random address in a single snapshot.
For RAM
(4) Paste Verilog Code here
module LAB_RAM(
input clk,
input en,
input rw,
input [2:0] addr,
input [7:0] in_data,
output [7:0] out_data_ps
);
reg [7:0] RAM [7:0];
reg [7:0] ram_data;
initial begin ram_data = 8'b00000000; end
always @(posedge clk)
begin
if (en) begin
if (rw)
RAM[addr] <= in_data;
else
ram_data <= RAM[addr];
end
end
assign out_data_ps = ram_data;
endmodule

(5) Paste RTL Diagram here


(6) Paste TCL Script here
add_force {/LAB_RAM/clk} -radix bin {1 0ns} {0 5000ps} -repeat_every 10000ps
add_force {/LAB_RAM/en} -radix bin {1 0ns}
add_force {/LAB_RAM/rw} -radix bin {0 0ns}
add_force {/LAB_RAM/addr} -radix bin {000 0ns}
add_force {/LAB_RAM/in_data} -radix bin {10001111 0ns}
run 10 ns
add_force {/LAB_RAM/clk} -radix bin {1 0ns} {0 5000ps} -repeat_every 10000ps
add_force {/LAB_RAM/en} -radix bin {1 0ns}
add_force {/LAB_RAM/rw} -radix bin {0 0ns}
add_force {/LAB_RAM/addr} -radix bin {001 0ns}
add_force {/LAB_RAM/in_data} -radix bin {01001111 0ns}
run 10 ns
add_force {/LAB_RAM/clk} -radix bin {1 0ns} {0 5000ps} -repeat_every 10000ps
add_force {/LAB_RAM/en} -radix bin {1 0ns}
add_force {/LAB_RAM/rw} -radix bin {0 0ns}
add_force {/LAB_RAM/addr} -radix bin {010 0ns}
add_force {/LAB_RAM/in_data} -radix bin {00101111 0ns}
run 10 ns
add_force {/LAB_RAM/clk} -radix bin {1 0ns} {0 5000ps} -repeat_every 10000ps
add_force {/LAB_RAM/en} -radix bin {1 0ns}
add_force {/LAB_RAM/rw} -radix bin {0 0ns}
add_force {/LAB_RAM/addr} -radix bin {011 0ns}
add_force {/LAB_RAM/in_data} -radix bin {00011111 0ns}
run 10 ns
add_force {/LAB_RAM/clk} -radix bin {1 0ns} {0 5000ps} -repeat_every 10000ps
add_force {/LAB_RAM/en} -radix bin {1 0ns}
add_force {/LAB_RAM/rw} -radix bin {0 0ns}
add_force {/LAB_RAM/addr} -radix bin {100 0ns}
add_force {/LAB_RAM/in_data} -radix bin {00000111 0ns}
run 10 ns
add_force {/LAB_RAM/clk} -radix bin {1 0ns} {0 5000ps} -repeat_every 10000ps
add_force {/LAB_RAM/en} -radix bin {1 0ns}
add_force {/LAB_RAM/rw} -radix bin {0 0ns}
add_force {/LAB_RAM/addr} -radix bin {101 0ns}
add_force {/LAB_RAM/in_data} -radix bin {00001011 0ns}
run 10 ns
add_force {/LAB_RAM/clk} -radix bin {1 0ns} {0 5000ps} -repeat_every 10000ps
add_force {/LAB_RAM/en} -radix bin {1 0ns}
add_force {/LAB_RAM/rw} -radix bin {0 0ns}
add_force {/LAB_RAM/addr} -radix bin {110 0ns}
add_force {/LAB_RAM/in_data} -radix bin {00001101 0ns}
run 10 ns
add_force {/LAB_RAM/clk} -radix bin {1 0ns} {0 5000ps} -repeat_every 10000ps
add_force {/LAB_RAM/en} -radix bin {1 0ns}
add_force {/LAB_RAM/rw} -radix bin {0 0ns}
add_force {/LAB_RAM/addr} -radix bin {111 0ns}
add_force {/LAB_RAM/in_data} -radix bin {00001110 0ns}
run 10 ns

(7) Output Waveform showing data write using a sequential address and data read with
random address.

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