Obsolete Product(s) - Obsolete Product(s) : FET Driver For 3 Phase BLDC Motor
Obsolete Product(s) - Obsolete Product(s) : FET Driver For 3 Phase BLDC Motor
Obsolete Product(s) - Obsolete Product(s) : FET Driver For 3 Phase BLDC Motor
Data brief
Programmable parameters:
Cross conduction dead time with a fixed
minimum value;
s )
t(
4 current steps driving the PowerMOS
u c
gates (25%, 50%, 75%, 100%);
Phase or ground selection of current
TQFP64 (exposed pad down)
sense amplifier;
o d
GAPGPS00129
amplifiers; r
Gain values for the current sense
P
Features t e
Zero current output voltage (offset) for
the current sense amplifiers;
Supply voltage from 6 V to 36 V for working
o le
Over voltage threshold selection for
single or double battery operation;
in 12 V and 24 V systems
The device can withstand -7 V to 75 V at the
b s
Short circuit detection thresholds for the
low-side and the high-side MOSFETs
FET high-side Driver pins
Low standby current consumption
- O (drain to source voltage monitor).
( s )
3.3 V internal regulator supplied by Vcc pin
Protection and diagnostic:
and over voltage protection t
Boost regulator for full Rdson down to 6 V
c FET driver:
d u
3 low-side + 3 high-side drivers:
PWM operation up to 20 kHz
FET driver supply Undervoltage (UV)
r o
Gate driver current adjustable via SPI in
diagnostic;
Gate to source output voltage limit;
e P
4 steps. Range set via external resistor.
Maximum gate controlled current 600
Gate to source passive switch off.
l
mA
e t
Source connection to each MOSFET
Power supply pins VB and VCC
Overvoltage (OV), Undervoltage (UV)
bs
Input pin for each gate driver All logic pins withstand 35 V
2-differential current sense amplifiers: Power MOSFET drain to source voltage
1 Description
L9907A is a smart power device realized in STMicroelectronics advanced BCD-6s
technology. It is able to drive all PowerMOS transistors for 3-phase BLDC motor
applications. The circuit is suitable to operate in environments with high supply voltage
such as double battery. Supply related pins are capable of withstanding up to 75 V.
Moreover, the device is able to control the six pre-driver channels independently. In this
way it is possible to implement all kind of electric motor control strategies. The integrated
boost regulator provides sufficient gate charge for all PowerMOS down to a battery voltage
of 6 V. All pre-drivers have dedicated connections with the MOSFET sources. The device
offers programmability for a base gate output current via an external resistor. Moreover, via
SPI, it is possible to select among 4 gate output current levels even while the application is
)
running. All channels are protected against short circuit and the device is protected against
s
t(
overtemperature condition. Moreover, the boost converter implements an over voltage
u c
protection to allow safe functionality of pre-drivers in all battery voltage condition. During
over voltage condition, BST_C voltage is limited by temporarily switching off the boost
d
regulator and pre-drivers are allowed to operate. Boost will be self reenabled as soon as
o
P r
the output voltage decreases to an acceptable value. The device is equipped with 2 current
sense amplifiers. Both have SPI selectable amplifier gain (10, 30, 50 and 100) and output
offset voltage level in order to allow max flexibility for phase or ground current sense
t e
strategy. All I/O pins are 35 V compatible. Full diagnostic is available through SPI. The
o
device is protected against Shoot Through events. le
device is available in TQFP64 and bare die, according to the application requirements. The
b s
- O
( s )
c t
d u
r o
e P
l e t
s o
O b
Vcc
(5V or 3.3V) VC BST_C BST_L
VB
3.3V Boost
Vdd Vreg regulator
VDH
s )
t(
(3.3V)
BGND
u c
CBS1
PWM H1
o d
PWM L1
PWM H2
P r GHS1
PWM L2
t e
le
Logic SHS1
PWM H3
PWM L3
s o
EN1
b
-O
GLS1
EN2
(s)
BST_DIS
SLS1
ct
Half bridge driver 1
CBS2
du
FS FLAG GHS2
H bridge driver 2
Half SHS2
SDI
r o CBS3
GLS2
SLS2
CS
e P SPI
GHS3
SCK
ol
SDO SLS3
bs
Gat charge current set
Gate
GCR
TM 100 / 75 / 50 / 25%
O TO3 Overvolt.
Undervolt.
Overtemp.
IS1+
IS1-
IB1 IS2+
IB2 IS2-
BST_DI
BST_C
BST_L
DGND
BGND
VCAP
GCR
VDH
VDD
VCC
NC
NC
NC
NC
NC
VB
64
62
59
56
54
53
51
63
61
60
58
57
55
52
50
49
NC 1 48 SGND1
GLS_3 2 47 PWM_L3
SLS_3 3 46 PWM_L2
NC 4 45 PWM_L1
GLS_2 5 44 EN1
SLS_2 6 43 EN2
NC 7 42 TO3
GLS_1 8 41 SDO
s )
t(
SLS_1 9 40 SDI
AGND 10 39 SCK
IS1+
IS1-
11
12
38
37
CS
u
FS_FLAGc
NC 13 36
od
PWM_H3
IB1
IB2
SGND2
14
15
16
35
34
33
P r
PWM_H2
PWM_H1
TM
19
20
22
23
27
31
32
18
21
24
25
26
28
29
30
e
17
le t
IS2-
IS2+
NC
NC
NC
NC
NC
GHS_3
SHS_3
GHS_2
SHS_2
GHS_1
SHS_1
CBS_3
CBS_2
CBS_1
s o
O b
Table 2: Pin function
GAPGPS00834
u c
Gate connection for low-side MOSFET, phase 3 O
3 SLS_3
Pr
4 NC NC -
5 GLS_2 Gate connection for low-side MOSFET, phase 2 O
e
6
t e SLS_2 Source connection for low-side MOSFET, phase 2 I
l
so
7 NC NC -
Ob
8 GLS_1 Gate connection for low-side MOSFET, phase 1 O
9 SLS_1 Source connection for low-side MOSFET, phase 1 I
10 AGND Analog ground GND
11 IS1+ Positive input for current sense amplifier 1 I
12 IS1- Negative input for current sense amplifier 1 I
13 NC NC -
14 IB1 Output for current sense amplifier 1 (Test mode digital output #1) O
15 IB2 Output for current sense amplifier 2 (Test mode digital output #2) O
16 SGND2 Substrate (and ESD_GND) connection 2 GND
17 IS2- Negative input for current sense amplifier 2 I
18 IS2+ Positive input for current sense amplifier 2 i
( s )
-
ct
28 CBS_1 Bootstrap capacitor for high-side MOSFET, phase 1 I
29
30
GHS_1
SHS_1
Gate connection for high-side MOSFET, phase 1
Source connection for high-side MOSFET, phase 1
d u O
I
o
Pr
31 NC NC -
32
33
NC
TM (1)
NC
Test mode enable input
e t e -
I
34 PWM_H1
o l
PWM command input for high-side phase 1 I
s
Ob
35 PWM_H2 PWM command input for high-side phase 2 I
36 PWM_H3 PWM command input for high-side phase 3 I
37 FS_FLAG
) -
Fault status flag output O
38 CS
ct (s
SPI chip select input I
39
40
SCK
SDI
d u SPI serial clock input
SPI Serial data input
I
I
o
Pr
41 SDO SPI serial data output O
e t e
42
43
TO3
EN2
Test output
Enable Input 2 (ANDed with EN1 to enable any gate drive output).
O
I
s ol 44 EN1 Enable Input 1 (ANDed with EN2 to enable any gate drive output). I
O b 45
46
PWM_L1
PWM_L2
PWM command input for low-side phase 1
PWM command input for low-side phase 2
I
I
47 PWM_L3 PWM command input for low-side phase 3 I
48 SGND1 Substrate (and ESD_GND) connection 1 GND
49 Vcc 5 V / 3.3 V power supply input I
50 NC NC -
51 GCR Connection to resistor for current selection of gate driver O
52 Vdd 3.3 V power supply output (for IC internal purpose only) O
53 DGND Digital ground GND
54 VB Protected battery monitor I
55 NC NC -
( s )I
Notes:
c t
u
(1)
TM pin has to be connected to ground in the application.
o d
P r
et e
o l
b s
- O
( s )
u ct
o d
P r
e t e
o l
b s
O
3 Electrical specifications
3.1 Absolute maximum ratings
Maximum ratings are absolute ratings; exceeding any one of these values may cause
permanent damage to the integrated circuit.
Table 3: Absolute maximum ratings
Parameter Condition Min Max Unit
-0.3 75 V
Monitor supply pin Pin VB
-10 10 mA
-0.3 75
s )
V
BST_C
t(
uc
-100 100 mA
od
-0.3 75 V
(1)
Pr
Pin: BST_L -2.5 75 V
-100 100 mA
Power supply pins
t e -0.3 35 V
Pin Vcc
o le -10 25 mA
Pin Vdd
b s -0.3 4.6 V
-O
-10 15 mA
-0.3 20 V
( s ) Pin VCAP
-100 100 mA
t
uc
(2)
PWM_H1 to 3, PWM_L1 to 3, IB1, -0.3 35 V
Miscellaneous Analog/Digital I/O IB2, EN1, EN2, FS_FLAG,
od
pins BST_DIS,TM, CS, SCK, SDI, -10 10 mA
SDO, TO3
P r
Gate current selection pin
Pin GCR -0.3 4.6 V
e
let
-10 10 mA
IS1+,IS1-,IS2+,IS2- -7 75 V
Pin VDH -4 75 V
High-side drain sense
-10 10 mA
HS Bootstrap Cap pins: CBS_1 to
-0.3 75 V
3
Differential gate to source HS pins:
-0.3 20 V
V(GHS_x) - V(SHS_x), x = 1 to 3
FET driver pins
Source HS pins: SHS_1 to 3 -7 75 V
Source LS pins: SLS_1 to 3 -7 10 V
Differential gate to source LS pins:
-0.3 20 V
V(GLS_x) - V(SLS_x), x = 1 to 3
Notes:
(1)
-2.5 V for t < 1 μs.
(2)
In standard battery level application (12 V systems) the I/O pins and Vcc pin can stand a short to battery up
to 35 V. A short to 35 V battery on any I/O pin also forces the Vcc to approximately 35 V. Care must be taken
in order to avoid that under such condition the Vcc pin is strongly pulled down to 5 V (or 3.3 V) with a current
exceeding the absolute maximum ratings level.
s )
3.2 ESD protection
c t(
d u
Table 4: ESD protection
r o
Parameter Condition
le t(1)
-2 2 kV
so
FET driver pins Human body model -2 2 kV
All pins but corner pins Charge device model -250 250 V
Corner pins
O b
Charge device model -750 750 V
Notes:
) -
(1)
( s
ct
HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114_A. HBM with all unzapped pins grounded.
d u
3.3
o
Temperature ranges and thermal data
r
Symbol
e P Table 5: Temperature ranges and thermal data
Parameter Min Max Unit
s o Tj
100 hours over lifetime temperature (1)
- 175 °C
O b Tstg
Tot
Storage temperature
Thermal shutdown temperature
-55
175
150
205
°C
°C
(2)
Thys Thermal shudown temperature hysteresis 10 - °C
(3)
Rth j-amb Thermal resistance junction-to-ambient - 23 °C/W
Rth j-case Thermal resistance junction-to-case - 3 °C/W
Notes:
(1)
Functionality is guaranteed, the specified limits may be exceeded.
(2)
Guaranteed by design.
(3)
IC soldered on 2s2p PCB thermally enhanced.
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
s )
c t(
d u
E2
r o
P
D1/4
t e
le
E1/4
4x N/4 TIPS
SECTION A-A
so
aaa C A-B D θ2 θ1
bbb H A-B D 4x
Ob
(N-4) x e
R1
C
A H R2
)-
A2 A1 b ccc C
ddd M A D
─ 0.05 GAUGE PLANE
s
0.25
D
c
D1
t ( θ3
S
L
θ
u
D (L1)
o d SECTION B-B
Pr
1
E1/4 (b)
2
3
WITH PLATING
ete
A B
D1/4 c c1
E1 E
ol
b1 BASE METAL
bs
A A
(see SECTION A-A)
O TOP VIEW
N
7278840_G_9I GAPGPS03451
( s ) -
ct
D1 - 10.00 BSC - - 0.3937 BSC -
D2
e - 0.50 BSC -
VARIATION
-
d u
0.0197 BSC -
o
Pr
E - 12.00 BSC - - 0.4724 BSC -
E1(2)
e
- 10.00 BSC - - 0.3937 BSC -
E2
e t
VARIATION
l
L 0.45 0.6 0.75
s o 0.0177 0.0236 0.0295
Ob
L1 - 1.00 REF - - 0.0394 REF -
N - 64 - - 2.5197 -
R1 0.08
)-- - 0.0031 - -
R2 0.08
d u
0.2 - -
TOLERANCE OF FORM AND POSITION
0.0079 - -
o
Pr
aaa - 0.2 - - 0.0079 -
e t e bbb
ccc
-
-
0.2
0.08
-
-
-
-
0.0079
0.0031
-
-
O b Option A
VARIATIONS
D2 - 4.5 - - 0.1772 -
E2 - 4.5 - - 0.1772 -
Option B
D2 - 6 - - 0.2362 -
E2 - 6 - - 0.2362 -
Notes:
(1)
Values in inches are converted from mm and rounded to 4 decimal digits.
(2)
Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusion is “0.25 mm”
per side.
5 Revision history
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STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
e
le t
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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© 2015 STMicroelectronics – All rights reserved
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