Department of Computer Science and Engineering(Data Science)

Course Name : Computer Organization

Course Number : 22DS304PC

Course Designation : Core

Credits :3

Prerequisites : Digital Logic Design and Microprocessors

II B Tech – I Semester
(2023-24)

P.MOUNIKA
Assistant Professor
Academic Calendar:
Syllabus

Digital Computers: Introduction, Block diagram of Digital Computer, Definition of

Computer Organization, Computer Design and Computer Architecture.
Data Representation: Data types, Complements, Fixed Point Representation,
Floating Point Representation.
Unit –I
Register Transfer Language and Micro operations: Register Transfer language,
Register Transfer, Bus and memory transfers, Arithmetic Micro operations, logic
micro operations, shift micro operations, Arithmetic logic shift unit.

Basic Computer Organization and Design: Instruction codes, Computer Registers

Computer instructions, Timing and Control, Instruction cycle, Memory Reference
Instructions, Input – Output and Interrupt.
Unit – II
Micro programmed Control: Control memory, Address sequencing, micro
program example, design of control unit.

Central Processing Unit: General Register Organization, Instruction Formats,

Addressing modes, Data Transfer and Manipulation, Program Control.
Unit -III Computer Arithmetic: Addition and subtraction, multiplication Algorithms,
Division Algorithms, Floating – point Arithmetic operations.

Memory Organization: Memory Hierarchy, Main Memory, Auxiliary memory,

Associate Memory, Cache Memory.
Unit –IV Input-Output Organization: Input-Output Interface, Asynchronous data transfer,
Modes of Transfer, Priority Interrupt Direct memory Access.

Reduced Instruction Set Computer: CISC Characteristics, RISC

Characteristics. Pipeline and Vector Processing: Parallel Processing,
Pipelining, Arithmetic Pipeline, Instruction Pipeline, RISC Pipeline,
Unit –V Vector Processing, Array Processor.
Multi Processors: Characteristics of Multiprocessors, Interconnection
Structures, CacheCoherence.

Text Books & Reference Books

Text Books
Computer System Architecture – M. Moris Mano, Third Edition, Pearson/PHI.
1

Suggested / Reference Books

Computer Organization – Car Hamacher, ZvonksVranesic, SafeaZaky, Vth
1 Edition,McGrawHill.

ComputerOrganizationandArchitecture–WilliamStallingsSixthEdition, Pearson/PHI.
2
StructuredComputerOrganization–AndrewS.Tanenbaum, 4thEdition, PHI/Pearson.
3
 Time Table

Room No: 029 W.E.F: 18/09/23

TO: 20/01/24

Class 1 2 3 4 5 6
Hour
9:20 – 10.20 – 11:20– 1:00 – 2:00 – 3:00 –
Time
10:20 11:20 12:20 2:00 3:00 4:00

MON
COA DE JAVA DM ASSOCIATION

TUE
PP DM JAVA SDC LAB

LUNCH BREAK
12:20 – 1:00
WED
JAVA DM DE DM DE COA

THU JAVA
DM COA
PP LAB

FRI PP
JAVA LAB COA JAVA

SAT PP JAVA DM COA

GS LAB
Programme Educational Objectives (PEO’s)

1. Excel in a professional career and/or higher education by acquiring in-depth knowledge of

computer-based technologies.

2. Apply design and development principles in the construction of software systems of

varying complexity.

3. Practice the profession with ethics and make them responsible citizens to promote
Industrial progress growth and societal transformation.

Programme Specific Outcomes (PSOs)

1. Apply the fundamental knowledge for problem analysis and conduct investigations in
computer science engineering for sustainable development

2. Design and development of solutions by using modern software for the execution of the
projects in specialized areas.

3. Inculcate effective communication and ethics for lifelong learning with social awareness

Programme Outcomes (PO’s)

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization for the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for public health and safety, and cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools, including prediction and modelling to complex
engineering activities, with an understanding of the limitations.
6. The engineer and society: Apply to reason informed by the contextual knowledge to
assess societal, health, safety, legal, and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and teamwork: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with the society at large, such as being able to comprehend
 and write effective reports and design documentation, make effective presentations, and
give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change.

Co-requisite: A Course on “Digital Logic Design and Microprocessors”.

Course Objectives:

Students will learn:

1. Introduce principles of computer organization and the basic architectural concepts.
2. Explore the basic organization, design, and programming of a simple digital computer.
3. Introducessimple register transfer language to specify various computer operations.
4. Describingmemoryorganization and I/O systems.
5. Introduce pipelining and vector processing.

Course Outcomes:

Students will be able to:

1. Identityof computer organization architecture.

2. Analyze the basics of instruction sets and their functionality.
3. Evaluate arithmetical operations by using data.
4. Demonstrate the functional units of the computer.
5. Design a pipeline for consistent execution of instructions.
Mapping of Course outcomes with PO’s, PSO’s & PEO’s

Course Outcomes PO’s PSOs PEO’s

1, 2, 3, 4, 7, 11, 12 1, 2, 1, 2, 3
CO1
1, 2, 3, 4, 7, 11, 12 1, 2 1, 2
CO2
1, 2, 3, 4, 6, 7, 11, 12 1, 2 1, 2, 3
CO3
1, 2, 3, 4, 6, 7, 11, 12
CO4 1, 2, 1, 2, 3
1, 2, 3, 4, 5, 7, 11, 12
CO5 1, 2, 1, 2, 3

Articulation matrix of Course outcomes with PO’s

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 2 2 1 1 1 2 1
CO2 2 2 1 1 1 2 1
CO3 2 2 1 1 1 1 2 1
CO4 2 2 1 1 1 1 2 1
CO5 3 3 3 2 2 1 2 1
Course Schedule

Distribution of Hours in Unit – Wise

Unit Topic Chapters Total No. of

Hours
Book1 Book2

Digital Computers, Data

I Representation, Register Transfer Ch1, Ch2 11
Language and Micro operations
Basic Computer Organization and
II Design, Micro programmed Ch3, Ch4 10
Control
Central Processing Unit,
III Ch5, Ch19 13
Computer Arithmetic
Memory Organization, Input-
IV Ch16, Ch17, Ch18 10
Output Organization
Reduced Instruction Set
V Computer, Pipeline and Vector Ch8, Ch9, Ch10 10
Processing, Multi Processors
Total contact classes for Syllabus coverage 54

Assignment Tests : 02 (Before Mid1 & Mid2 Examinations)

Number of hours/lectures available in Semester / Year: 64

The number of topics in each unit is not the same – because of the variation, all the units have
unequal distribution of hours
Lecture Plan

Expected Actual Date Teaching-Learning

S.
Topic Date of of Process
No.
Completion Completion
Unit-I
1 Digital Computers: 18.09.2023 18.09.2023 PPT & Digital Board
Introduction, Block diagram of
Digital Computer.
2 Definition of Computer 20.09.2023 20.09.2023 PPT & Digital Board
Organization.
3 Computer Design and 21.09.2023 21.09.2023 PPT & Digital Board
Computer Architecture.

4 Data Representation: Data 22.09.2023 22.09.2023 PPT & Digital Board

types, Complements
5 Fixed Point Representation 23.09.2023 23.09.2023 PPT & Digital Board
6 Floating Point Representation 25.09.2023 25.09.2023 PPT & Digital Board
7 Register Transfer Language and 27.09.2023 27.09.2023 PPT & Digital Board
Micro operations: Register
Transfer language.
8 Register Transfer, Bus and 29.09.2023 29.09.2023 PPT & Digital Board
memory transfers, Tutorial -1
9 Arithmetic Micro operations 04.10.2023 04.10.2023 PPT & Digital Board
Tutorial -1
10 Logic micro operations, shift 05.10.2023 05.10.2023 PPT & Digital Board
micro operations.
11 Arithmetic logic shift unit. 06.10.2023 06.10.2023 PPT & Digital Board

Unit-II
1 Basic Computer Organization 07.10.2023 07.10.2023 PPT & Digital Board
and Design:
2 Instruction codes 09.10.2023 09.10.2023 PPT & Digital Board
3 Computer Registers Computer 11.10.2023 11.10.2023 PPT & Digital Board,
instructions,
4 Timing and Control 12.10.2023 12.10.2023 PPT & Digital Board
Tutorial -2
5 Instruction cycle, 13.10.2023 13.10.2023 PPT & Digital Board
6 Memory Reference Instructions, 16.10.2023 18.10.2023 PPT & Digital Board
7 Micro programmed 19.10.2023 20.10.2023 PPT & Digital Board
Control: Control memory
8 Address sequencing 21.10.2023 21.10.2023 PPT & Digital Board
9 micro program example 30.10.2023 30.10.2023 PPT & Digital Board
10 Design of control unit. 01.11.2023 01.11.2023 PPT & Digital Board
 Unit-III
1 Central Processing Unit : 02.11.2023 02.11.2023 PPT & Digital Board,

2 General Register Organization. 03.11.2023 03.11.2023 PPT & Digital Board

3 Instruction Formats. 04.11.2023 04.11.2023 PPT & Digital Board

4 Addressing modes. 06.11.2023 06.11.2023 PPT & Digital Board

5 Data Transfer and Manipulation 08.11.2023 08.11.2023 PPT & Digital Board

6 Program Control. 09.11.2023 09.11.2023 PPT & Digital Board,

7 Computer Arithmetic: 10.11.2023 10.11.2023 PPT & Digital Board,

8 Addition and subtraction 11.11.2023 11.11.2023 PPT & Digital Board

9 multiplication Algorithms 13.11.2023 13.11.2023 PPT & Digital Board

10 Division Algorithms. 15.11.2023 15.11.2023 PPT & Digital Board

Floating – point Arithmetic 16.11.2023 18.11.2023 PPT & Digital Board
11
operations.
12 General Register Organization. 29.11.2023 30.11.2023 PPT & Digital Board
Instruction Formats. 01.12.2023 01.12.2023 PPT & Digital Board,
13
Tutorial-3a
Unit-IV
Memory Organization: 02.12.2023 02.12.2023 PPT & Digital Board
1
Memory Hierarchy
2 Main Memory 04.12.2023 04.12.2023 PPT & Digital Board

3 Auxiliary memory 06.12.2023 07.12.2023 PPT & Digital Board

4 Associate Memory 08.12.2023 08.12.2023 PPT & Digital Board

Cache Memory. 09.12.2023 09.12.2023 PPT & Digital Board,
5
Tutorial-4
Input-Output Organization: 11.12.2023 13.12.2023 PPT & Digital Board
6
Input-Output Interface
7 Asynchronous data transfer 14.12.2023 16.12.2023 PPT & Digital Board

8 Modes of Transfer 18.12.2023 18.12.2023 PPT & Digital Board

Priority Interrupt Direct memory 20.12.2023 21.12.2023 PPT & Digital Board
9
Access.
Unit-V
Reduced Instruction Set 22.12.2023 26.12.2023 PPT & Digital Board
1
Computer: CISC Characteristics
2 RISC Characteristics. 27.12.2023 29.12.2023 PPT & Digital Board
Pipeline and Vector 30.12.2023 01.01.2024 PPT & Digital Board
3
Processing: Parallel Processing
4 Pipelining, Arithmetic Pipeline 01.01.2024 01.01.2024 PPT & Digital Board
 Instruction Pipeline, RISC 03.01.2024 04.01.2024 PPT & Digital Board
5
Pipeline,
Vector Processing, Array 05.01.2024 06.01.2024 PPT & Digital Board
6
Processor.
7 Array Processor. 08.01.2024 09.01.2024 PPT & Digital Board
Multi Processors: Characteristics 10.01.2024 11.01.2024 PPT & Digital Board
8
of Multiprocessors
Interconnection 15.01.2024 17.01.2024 PPT & Digital Board
9
Structures
CacheCoherence. 18.01.2024 20.01.2024 PPT & Digital Board,
10
Tutorial-5
Total No of classes: 54

Date of Unit completion & Remarks

Unit – I
Date: 06.10.2023
Remarks:

Unit – II
Date: 01.11.2023
Remarks:

Unit – III
Date: 01.12.2023
Remarks:

Unit – IV
Date: 21.12.2023
Remarks:

Unit – V
Date: 20.01.2024
Remarks:
Unit Wise Questions (With different Levels of thinking – Blooms Taxonomy and Course
Outcomes)

Unit-I

Short Answer Questions:

1. What is a computer? [CO1, L1]

2. Define Control Word and its parts. [CO1, L1]
3. i. Arithmetic Addition ii. Arithmetic Subtraction. [CO1, L2]
3. Draw the RAM and ROM Chip Diagrams. [CO1, L2]
4.Explain Number Systems and its types briefly? [CO1, L2]
(a) Convert (45.6875)10 = ( )2

Long Answer Questions:

1. Define Digital Computer? Draw the Picture of Block Diagram of CPU? Define [CO1, L1]

2. Digital Computer and Draw the Block-Diagram of Computer Organization. [CO1, L1]
(a) Define Digital Computer and Draw the Block-Diagram of Computer [CO1, L2]
3. Explain 16-Line Common BUS System how the registers areconnected. [CO1, L2]
4. Explain 4-bit Bus & memory Transfer Using Multiplexer and 3state Bus buffer with
diagram? [CO2, L2]

5. List out the Names of Different Number Systems with example?[CO1, L2]

6. What is the use of Complements in Computer Organization? [CO2, L2]

7. (a) Explain Basic Register Transfer Operations? [CO2, L2]
8. (b) Explain 4-bit Bus & memory Transfer Using Multiplexer and 3state Bus buffer with
diagram? [CO2, L2]
9. Explain Basic Register Transfer Operations? [CO2, L2]

Unit-II
Short Answer Questions:

1. Define Instruction codes and its formats? [CO2, L2]

2. Define Instruction Cycle its phases? [CO2, L2]
3. Explain Memory Reference Instructions? [CO2, L3]

Long Answer Questions:

1. Explain Basic Computer Registers and their functionality? [CO2, L2]
2. Write Short note on three address Instructions. [CO2, L2]
3. Explain the Instruction Cycle and its phases briefly? [CO2, L3]
Unit-III
Short Answer Questions:

1. Define Instruction codes and its formats?

2. Explain Basic Register Transfer Operations?
3. Explain Basic Register Transfer Operations?
4. Define Instruction Cycle its phases?
5. Explain Memory Reference Instructions?

Long Answer Questions:

1. Mention the Names of Computer Registers? [CO3, L2]

2. Explain Booths multiplication algorithm with example.
3. Explain Basic Register Transfer Operations? [CO3, L3]
4. Explain floating point representation of decimal numbers.
5. Explain Booths multiplication algorithm with example. [CO3, L3]
6. Explain Instruction Cycle & Memory Reference Instructions Briefly? [CO3, L2]
8. Explain how addition and subtraction performed in singed magnitude notation. [CO3, L3]
9. Draw the block diagram of a typical DMA controller and explain.[CO3, L3]
10. Explain the Timing Signals with Control Unit connectivity Diagram with an example?[CO3, L2]
11. Explain in detail various types of addressing modes with example. [CO2, L2]
12. Write the difference between Direct and Indirect address modes. [CO3, L2]
14. Explain 4-bit Binary Arithmetic addition & Subtracted with diagram? [CO3, L2]
Unit-IV
Short Answer Questions:

1. Write a short note on Cache memory.[CO4, L3]

2. Explain Micro-operations and types? [CO4, L3]

Long Answer Questions:

1. (a) Explain Micro-operations and types? [CO4, L3]

(b) Explain Arithmetic Micro-operations briefly? [CO3, L3]
2. (a) Explain Micro-operations and types? [CO4, L4]
(b) Explain Arithmetic Micro-operations briefly? [CO3, L4]
3. Explain Arithmetic Logic Shift Operations with Diagram? [CO2, L4]
4. Explain Associative Memory in Memory Organization. [CO3, L5]
5. Explain Cache Memory in Memory Organization. [CO4, L5]

Unit-V
Short Answer Questions:

1. Array processors. [CO5, L3]

2. Explain Vector Processing
3. Discuss the characteristics of multi-processors. [CO5, L4]
4. Explain the following a) Control Memory b) Address Sequencing [CO4, L3]
5. What are CISC characteristics? [CO5, L5]
6. Write the major characteristics of RISC processors. [CO5, L5]

Long Answer Questions:

1. Write short note on RISC Characteristics.[CO4, L5]

2. Write short note on CISC Characteristics.[CO5, L4]
3. Explain floating point representation of decimal numbers.[CO4, L3]
4. a) Explain the parallel processing architecture and its uses.[CO4, L4]
5. Explain the parallel processing architecture and its uses. [CO6, L6]
6. Wrte a short note on Parallel Processing. [CO5, L5]

Assignment Questions for Mid -1

1. Define Digital Computer? Draw the Picture of Block Diagram of CPU? Define.
2. Digital Computer and Draw the Block-Diagram of Computer Organization.
3. List out the Names of Different Number Systems with example?
4. Explain Number Systems and its types briefly.
5. Convert (45.6875)10 = ( )2
6. What is the use of Complements in Computer Organization?
7. Define Instruction codes and its formats?
8. Define Instruction Cycle its phases?
9. Mention the Names of Computer Registers?
10. Explain Basic Register Transfer Operations?
11. Explain Micro-operations and types?
12. Comparethe following
(a. Arithmetic Addition (B. Arithmetic Subtraction
13. Explain 4-bit Binary Arithmetic addition & Subtracter with diagram?
14. Explain Arithmetic Logic Shift Operations with Diagram?
15. Explain Binary Complements and Decimal Complements with Example?
16. Explain Basic Computer Registers and their functionality?
17. Explain 16-Line Common BUS System how the registers areconnected.
18. Explain the Instruction Cycle and its phases briefly?
19. Explain the Timing Signals with Control Unit connectivity Diagram with an example?
20. Explain Memory Reference Instructions?
21. Briefly Explain Number System and its types?
22. (a) Explain Basic Register Transfer Operations?
(b) Explain 4-bit Bus & memory Transfer Using Multiplexer and 3state Bus buffer with diagram?
23. (a) Explain Micro-operations and types?
(b) Explain Arithmetic Micro-operations briefly?

Computer Organization Assignment Mid– II

1. Write a short note on Cache memory.

2. Explain Array Processing
3. Explain Vector Processing
4. Define Control Word and its parts
5. Write Short note on three address Instructions.
7. Write the difference between Direct and Indirect address modes.
8. Draw the RAM and ROM Chip Diagrams.
9. Write the Difference between Strobe Control and Handshaking
10. Write the Advantage of Handshaking Method.
11. Write a short note on Parallel Processing
12. Write short note on RISC Characteristics
13. Write short note on CISC Characteristics
14. Write short note on Characteristics of Multiprocessor.
15. Explain in detail various types of addressing modes with examples.
16. Explain how Data Transfer and Manipulation classified into Categories?
17. Explain how addition and subtraction performed in singed magnitude notation
18. Explain Cache Memory in Memory Organization
19. Explain Associative Memory in Memory Organization
20. What are Various Modes of Transfer explain.
21. Perform the arithmetic operation (+42) + (-13) and (-42)-(-13) in binary using signed 2’s
complement representation for negative numbers
22. a) Differentiate between Isolated I/O and memory-mapped I/O.
b) Explain programmed- I/O in details.
23. Explain Booths multiplication algorithm with example.
24. Derive an algorithm in flowchart form for adding and subtracting two fixed point binary
numbers when negative numbers are in the signed-2’s complement representation.
25. Draw the block diagram of a typical DMA controller and explain.
26. Explain floating point representation of decimal numbers.
27. Explain the parallel processing architecture and its uses

Case Studies (With Higher Levels of thinking – Blooms Taxonomy) for the academic year 2022-
23- II B Tech II semester

# 1 Designing Conceptual Schema for Real Time Applications

FACEBOOK, OLA CABS, Twitter, etc

# 2 (Covering Entire Syllabus)

Neo Co lab Case Studies
Previous Question papers:

Code No: 153AG R18

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
B. Tech II Year II Semester Examinations, April/May - 2023
COMPUTER ORGANIZATION
(Common to CSE, CSBS, CSIT, CE(SE), CSE(CS), CSE(DS), CSE(N), AI&DS, AI&ML,
CSD)
Time: 3 Hours Max. Marks: 75

Note: i) Question paper consists of Part A, Part B.

ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions.
iii) In Part B, Answer any one question from each unit. Each question carries 10 marks
and may have a, b as sub questions.

PART – A
(25 Marks)

1.a) What is a computer? [2]

b) Explain functionalities of CPU. [3]
c) What are different addressing modes? [2]
d) Discuss about any two types of instruction formats. [3]
e) Give an example of decimal representation. [2]
f) Explain about BCD adder. [3]
g) What is magnetic tape? [2]
h) Describe parallel priority interrupt. [3]
i) What are conditions for incoherence? [2]
j) What are CISC characteristics? [3]

PART – B
(50 Marks)

2. a) Explain about computer design and architecture.

b) What are computer registers? Explain. [5+5]
OR
3.a) Discuss about shift micro operations in detail.
b) List and explain about memory-reference instructions. [5+5]

4.a) What are shift instructions? Explain with suitable examples.

b) Define control memory. Explain. [5+5]
OR
5.a) Explain about microinstruction format in detail.
b) What are RISC instructions? Explain. [5+5]

6.a) Discuss about complements in data representation.

b) Explain decimal arithmetic operations with examples. [5+5]
OR
7. a) Describe fixed-point representation in detail.
b) Discuss about division algorithms with examples. [5+5]

8. a) Explain hardware organization and match logic of associative memory.

 b) What are various modes of transfer? Explain. [5+5]
OR
9. Discuss about direct mapping and set associative mapping. [10]

10. Explain the following:

a) Inter processor arbitration
b) Four-segment instruction pipeline. [5+5]
OR
11. Explain the following:
a) Inter process communication and synchronization
b) Array processors. [5+5]

---ooOoo---
 Code No: 153AG
R18
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
B.Tech II Year II Semester Examinations, March - 2022
COMPUTER ORGANIZATION
(Common to CSE, CSBS, CSIT, CSE(SE), CSE(CS), CSE(AIML), CSE(DS),
CSE(N))
Time: 3 Hours Max. Marks: 75
Answer any five questions
All questions carry equal marks
---

1.a) Explain in detail computer design and computer architecture.

b) Explain in detail life cycle of instruction. [9+6]

2. Explain the following.

a) Register transfer.
b) Input-Output and interrupt. [7+8]

3. Explain in detail various types of addressing modes with examples. [15]

4.a) Explain in detail about data transfer instructions.

b) Discuss the various types of instruction formats. [7+8]

5.a) Explain floating point representation of decimal numbers.

[7+8]
b) Explain the decimal addition operation with a neat diagram.

6.a) Explain the subtraction operation with signed 2’s complement data.
[6+9]
b) Explain in brief fixed point data representation.

7.a) Explain the working process of DMA.

[9+6]
b) Compare cache and main memory.

8.a) Explain in brief inter-processor communication.

[8+7]
b) Discuss the characteristics of multi-processors.

---ooOoo---
Tutorial Sheet

Unit-I Topics Revised

Topic Name Date
Introduction, Block diagram of Digital Computer 21.09.2023

Arithmetic Micro operations

23.09.2023
Unit-II Topics Revised
Topic Name Date
Timing and Control, Instruction cycle 13.10.2023

Design of control unit. 14.10.2023

Unit-III Topics Revised

Topic Name Date
Addressing modes 08.11.2023

Program Control. 10.11.2023

Unit-IV Topics Revised

Topic Name Date
Cache Memory. 11.12.2023

Priority Interrupt Direct memory Access 14.12.2023

Unit-V Topics Revised

Topic Name Date
Parallel Processing, Pipelining 03.01.2024

CacheCoherence. 08.01.2024

Topics beyond Syllabus

S. No Name of the Topic

1 Dealing with Un structured Data Using MANGO DB

2 Data Base Performance Optimizing Activities
 Course Assessment Sheet

Batch: 2022

Academic Year/Sem: 2023-2024

Course Name: Computer Organization

Course Number: 22DS304PC

Course Attainment (75% of Direct + 25% of Indirect) on a scale of 1 to 3.

Remarks and suggestions:

Course Coordinator
 Blooms Taxonomy Direct

Level 1 Remembering Exhibit memory of previously learned material by

recalling facts, terms, basic concepts, and answers.
Level 2 Understanding Demonstrate understanding of facts and ideas by
organizing, comparing, translating, interpreting,
giving descriptions, and stating main ideas.
Level 3 Applying Solve problems to new situations by applying
acquired knowledge, facts, techniques and rules
differently.
Level 4 Analyzing Examine and break information into parts by
identifying motives or causes. Make inferences and
find evidence to support generalizations.
Level 5 Evaluating Present and defend opinions by making judgments
about information, the validity of ideas, or quality of
work based on a set of criteria.
Level 6 Creating Compile information together in a different way by
combining elements in a new pattern or proposing
alternative solutions.

Direct Course Assessment Sheet

a) Internal Examination

Course assessment sheet Mid1

Subjective (30 Marks)

S.NO ROLL NO Assignment 5 Marks Part-A (10Marks) Part-B (20Marks) Total
Marks
Q1A 1B 1C 1D 1E Q2 Q3 Q4 Q5 Q6 Q7
1 217R1A6724 5 2 2 2 2 2 8 8 4 30

2 227R1A6701 5 1 1 1 1 4 4 12

3 227R1A6702 5 1 1 1 1 1 4 8 2 19

4 227R1A6703 5 1 1 1 1 1 5 8 4 22

5 227R1A6704 5 1 1 1 1 2 8 14

6 227R1A6705 5 2 2 2 2 2 7 8 4 29
7 227R1A6706 5 2 2 2 2 2 6 5 4 25

8 227R1A6707 5 2 2 2 2 2 8 7 4 29

9 227R1A6708 5 2 2 1 3 5 3 16

10 227R1A6709 5 2 2 2 7 7 3 23

11 227R1A6710 5 2 2 2 7 6 1 20

12 227R1A6711 5 2 1 2 2 7 6 4 24

13 227R1A6712 AB Absent 0

14 227R1A6713 5 2 1 2 5 5 3 18

15 227R1A6714 5 2 2 6 1 11

16 227R1A6715 5 1 2 1 6 6 2 18

17 227R1A6716 5 2 2 1 1 7 7 3 23

18 227R1A6717 5 2 2 2 2 2 6 4 20

19 227R1A6718 5 2 1 2 2 2 8 7 4 28

20 227R1A6719 5 2 2 2 2 2 8 8 4 30

21 227R1A6720 5 1 1 2 8 6 4 22

22 227R1A6721 5 2 2 2 7 5 3 21

23 227R1A6722 5 2 2 2 2 1 8 7 4 28

24 227R1A6723 5 2 1 1 1 7 3 3 18

25 227R1A6724 5 2 2 2 2 8 6 4 26

26 227R1A6725 5 2 2 2 2 6 6 4 24

27 227R1A6726 5 1 1 1 2 1 6 5 4 21

28 227R1A6727 5 1 1 1 2 2 5 3 2 17

29 227R1A6728 5 2 2 2 2 2 7 7 4 28

30 227R1A6729 5 2 2 2 2 2 6 6 3 25

31 227R1A6730 5 2 1 2 2 7 5 19

32 227R1A6731 5 2 2 2 2 8 7 3 26

33 227R1A6732 5 2 2 2 2 2 7 6 4 27

34 227R1A6733 5 1 1 2 2 5 2 1 14

35 227R1A6734 5 2 2 2 1 6 6 4 23

36 227R1A6735 5 2 2 1 2 2 5 5 19

37 227R1A6736 5 2 2 2 2 2 6 6 4 26

38 227R1A6737 5 1 2 2 1 4 1 11

39 227R1A6738 5 2 1 2 1 2 6 7 4 25

40 227R1A6739 5 2 2 2 1 2 6 6 4 25

41 227R1A6740 5 1 1 2 2 2 5 6 3 22

42 227R1A6741 5 2 2 2 2 2 7 7 24
43 227R1A6742 5 2 1 2 2 2 8 7 4 28

44 227R1A6743 5 1 1 1 1 6 4 14

45 227R1A6744 5 2 2 2 2 2 8 7 4 29

46 227R1A6745 5 2 2 2 2 2 8 7 4 29

47 227R1A6746 5 2 2 2 2 2 7 5 4 26

48 227R1A6747 5 2 2 2 2 6 7 3 24

49 227R1A6748 5 2 2 2 1 8 7 3 25

50 227R1A6749 5 2 2 2 2 7 8 3 26

51 227R1A6750 5 1 2 3 6 12

52 227R1A6751 5 2 2 2 2 6 7 4 25

53 227R1A6752 5 2 2 2 2 6 7 2 23

54 227R1A6753 5 2 2 2 2 2 8 6 4 28

55 227R1A6754 5 2 2 2 2 2 8 7 4 29

56 227R1A6755 5 2 2 2 2 1 4 4 1 18

57 227R1A6756 5 2 2 2 2 2 8 8 4 30

58 227R1A6757 5 2 2 2 2 2 8 8 3 29

59 227R1A6758 5 2 1 6 8 3 20

60 227R1A6759 5 2 2 2 2 8 7 4 27

61 227R1A6760 5 2 2 2 2 2 6 5 21

62 227R1A6761 5 2 2 2 2 7 8 4 27

63 227R1A6762 5 2 2 2 2 6 4 4 22

64 227R1A6763 5 2 2 2 2 7 7 4 26

65 227R1A6764 5 2 2 2 2 2 8 8 4 30

66 237R5A6701 5 2 1 2 2 6 7 4 24

67 237R5A6702 5 2 2 2 2 8 7 4 27

68 237R5A6703 5 2 2 2 2 2 8 7 4 29

69 237R5A6704 5 2 1 2 2 1 8 7 3 26

70 237R5A6705 5 2 2 2 2 6 6 20

71 237R5A6706 5 2 1 7 5 15
 Course assessment sheet Mid2

Subjective (30 Marks)

Assignment 5 PPT(5)
S.NO ROLL NO Marks Part-A (10Marks) Part-B (20Marks)
Total Marks Marks
Q1A 1B 1C 1D 1E Q2 Q3 Q4 Q5 Q6 Q7
1 217R1A6724 5 2 2 2 2 2 4 8 8 30 5

2 227R1A6701 5 1 1 1 1 2 4 4 14 5

3 227R1A6702 5 2 2 2 2 2 2 4 8 24 5

4 227R1A6703 5 2 2 2 2 2 3 8 8 29 5

5 227R1A6704 5 2 2 1 1 2 4 8 8 28 5

6 227R1A6705 5 2 2 2 2 2 4 8 7 29 5

7 227R1A6706 5 2 1 2 2 2 3 6 8 26 5

8 227R1A6707 5 2 2 2 2 2 4 8 8 30 5

9 227R1A6708 5 2 2 1 1 2 1 6 7 22 5

10 227R1A6709 5 2 1 2 2 2 3 8 8 28 5

11 227R1A6710 5 2 1 2 2 2 3 8 7 27 5

12 227R1A6711 5 2 1 2 2 2 3 7 8 27 5

13 227R1A6712 2 2 1 1 2 1 1 6 6 20 5

14 227R1A6713 5 2 2 2 2 2 2 7 7 26 5

15 227R1A6714 5 2 1 2 2 2 2 4 4 19 5

16 227R1A6715 3 2 1 2 2 1 4 7 7 26 5

17 227R1A6716 5 2 1 2 1 1 4 8 6 25 5

18 227R1A6717 5 2 1 2 1 2 3 5 7 23 5

19 227R1A6718 5 2 2 2 1 1 4 8 6 26 5

20 227R1A6719 5 2 2 2 2 2 4 8 8 30 5

21 227R1A6720 5 2 2 2 2 1 3 5 8 25 5

22 227R1A6721 3 1 1 2 1 2 3 4 6 20 5

23 227R1A6722 5 2 2 2 1 2 4 8 8 29 5

24 227R1A6723 5 2 1 2 1 2 3 8 7 26 5

25 227R1A6724 5 2 2 2 2 2 3 7 8 28 5

26 227R1A6725 5 1 2 2 2 2 3 7 7 26 5

27 227R1A6726 4 1 1 1 2 2 4 8 7 26 5
28 227R1A6727 5 2 1 2 2 2 3 6 8 26 5

29 227R1A6728 5 2 2 1 2 2 4 8 8 29 5

30 227R1A6729 4 2 1 2 2 1 4 8 7 27 5

31 227R1A6730 5 2 1 2 1 2 2 7 8 25 5

32 227R1A6731 5 2 1 2 1 2 4 8 7 27 5

33 227R1A6732 5 2 1 2 2 2 4 8 8 29 5

34 227R1A6733 5 2 2 1 1 2 1 6 8 23 5

35 227R1A6734 5 2 2 2 1 2 4 7 8 28 5

36 227R1A6735 5 2 2 2 2 1 3 8 7 27 5

37 227R1A6736 5 2 2 2 2 2 4 4 8 26 5

38 227R1A6737 3 1 1 2 2 2 4 6 18 5

39 227R1A6738 5 2 2 2 2 3 7 8 26 5

40 227R1A6739 5 2 2 2 2 2 4 8 8 30 5

41 227R1A6740 5 1 2 2 1 2 3 3 8 22 5

42 227R1A6741 4 1 2 2 2 1 4 4 8 24 5

43 227R1A6742 5 2 1 2 1 1 3 7 8 25 5

44 227R1A6743 3 1 2 2 1 2 3 6 4 21 5

45 227R1A6744 5 2 2 2 2 2 4 7 8 29 5

46 227R1A6745 5 2 2 2 2 2 4 8 8 30 5

47 227R1A6746 5 2 2 2 1 2 4 8 8 29 5

48 227R1A6747 3 2 1 1 1 1 3 7 7 23 5

49 227R1A6748 5 2 2 2 2 2 3 5 8 26 5

50 227R1A6749 5 2 2 2 2 2 2 8 8 28 5

51 227R1A6750 5 2 2 2 4 4 7 21 5

52 227R1A6751 3 2 2 2 1 2 2 5 8 24 5

53 227R1A6752 5 2 2 2 2 2 4 7 7 28 5

54 227R1A6753 5 2 2 2 1 1 4 8 8 28 5

55 227R1A6754 5 2 2 2 2 2 4 8 8 30 5

56 227R1A6755 3 1 1 2 1 1 4 7 17 5

57 227R1A6756 5 2 2 2 2 2 4 8 8 30 5

58 227R1A6757 4 2 2 2 2 2 4 7 8 29 5

59 227R1A6758 5 2 1 2 2 2 4 6 7 26 5

60 227R1A6759 5 2 2 1 2 2 3 4 8 24 5

61 227R1A6760 5 2 2 2 2 2 2 4 4 20 5

62 227R1A6761 5 2 1 2 1 2 3 7 6 24 5

63 227R1A6762 5 2 1 2 1 2 4 8 20 5
64 227R1A6763 5 2 2 2 1 2 4 6 7 26 5

65 227R1A6764 5 2 1 2 2 2 4 8 8 29 5

66 237R5A6701 5 2 1 1 2 2 4 8 8 28 5

67 237R5A6702 5 2 2 1 2 2 2 8 7 26 5

68 237R5A6703 5 2 2 2 2 2 4 8 8 30 5

69 237R5A6704 5 2 2 2 2 2 3 6 8 27 5

70 237R5A6705 5 2 2 2 2 1 4 6 6 25 5

71 237R5A6706 5 2 2 2 2 3 4 5 20 5

b) External Examination

Hall Ticket No Total Marks

CSP Rubric Name & Number

CSP Rubric

S.No. Criteria LEVEL (Level: 3-Excellent Level: 2-Good Level: 1-Poor)

The student speaks in phase with the given topic confidently
3
Communication

using Audio-Visual aids. Vocabulary is good

Student speaking without proper planning, fair usage of Audio-
Oral

1 2
Visual aids. Vocabulary is not good
The student speaks vaguely not in phase with the given topic. No
1
synchronization among the talk and Visual Aids
Proper structuring of the document with relevant subtitles,
3 readability of a document is high with the correct use of grammar.
Writing Skills

Work is genuine and not published anywhere else

Information is gathered without continuity of topic, sentences
2 2 were not framed properly. Few topics are copied from other
documents
Information gathered was not relevant to the given task, a vague
1
collection of sentences. Content is copied from other documents
The student identifies most potential ethical or societal issues and
Social and Ethical

3
tries to provide solutions for them discussing with peers
Awareness

The student identifies the societal and ethical issues but fails to
3 2
provide any solutions discussing with peers
The student does not attempt to identify the societal and ethical
1
issues
3 The student uses appropriate methods, techniques to model and
Knowledge

solve the problem accurately

Content

2 The student tries to model the problem but fails to solve the
4
problem
1 The student fails to model the problem and also fails to solve the
problem
Listens carefully to the class and tries to answer questions
3
Participation

confidently
Student

Listens carefully to the lecture but doesn’t attempt to answer the

5 2
questions
The student neither listens to the class nor attempts to answer the
1
questions
The program structure is well organized with the appropriate use
analytica
Technic
al and

of technologies and methodology. Code is easy to read and well

6 3
documented. The student can implement the algorithm to produce
accurate results
 The program structure is well organized with the appropriate use
of technologies and methodology. Code is quite difficult to read
2
and not properly documented. The student can implement the
algorithm providing accurate results.
The program structure is not well organized with mistakes in the
1 usage of appropriate technologies and methodology. Code is
difficult to read and the student is not able to execute the program
Independently able to write programs to strengthen the concepts
3
covered in theory
Knowledge
Practical

Independently able to write programs but not able to strengthen

7 2
the concepts learned in theory
Not able to write programs and not able to strengthen the
1
concepts learned in theory
The student uses appropriate methods, techniques to model and
Understanding of
Engineering core

3 solve the problem accurately in the context of multidisciplinary

projects
8 The student tries to model the problem but fails to solve the
2
problem in the context of multidisciplinary projects
The student fails to model the problem and also fails to solve the
1 problem in the context of multidisciplinary projects

Indirect Course Assessment Sheet

Tools:
a) Case Study

S.No. Hall Ticket Number Rubric Assessment Remarks

1
2
3

b) Course End Survey Rep

Add-on Programmes (Guest Lecture/Video Lecture/Poster Presentation)

Unit Wise PPT’s & Lecture Notes:

Detailed Notes

Unit-I
Introduction, Register Transfer Language and Micro operations and Basic Structure
Of Computers

Digital Computer:

The digital computer is a digital system that performs various computational tasks.
Digital computers use the binary number system, which has two digits: 0 and 1. A binary digit
is called a bit. Information is represented in digital computers in groups of bits. By using
various coding techniques, groups of bits can be made to represent not only binary numbers
but also other discrete symbols, such as decimal digits or letters of the alphabet. By judicious
use of binary arrangements and by using various coding techniques, the groups of bits are used
to develop complete sets of instructions for performing various types of computations.
A computer system is sometimes subdivided into two functional entities
1- The hardware of the computer consists of all the electronic components and
electromechanical devices that comprise the physical entity of the device.
2- Computer software consists of the instructions and data that the computer
manipulatesto perform various data-processing tasks.
The system software of a computer consists of a collection of programs whose purpose is
tomake more effective use of the computer. The programs included in a systems software
package are referred to as the operating system.

Computer Hardware
The hardware of the computer is usually divided into three major parts, as shown in
Fig(1)

The central processing unit (CPU) contains arithmetic and logic unit for manipulating
data, a number of registers for storing data, and control circuits for fetching and executing
instructions. The memory of a computer contains storage for instructions and data. It is called
a random- access memory (RAM) because the CPU can access any location in memory at
random and retrieve the binary information within a fixed interval of time. The input and
output processor (IOP) contains electronic circuits for communicating and controlling the
transfer of information between the computer and the outside world. The input and output
devices connected to the computer include keyboards, printers, terminals, magnetic disk
drives, and other communication devices.

Computer Organization
Computer organization is concerned with the way the hardware components operate
andthe way they are connected together to form the computer system. The various components
areassumed to be in place and the task is to investigate the organizational structure to verify
that the computer parts operate as intended.

Computer Design
Computer design is concerned with the hardware design of the computer. Once the
computer specifications are formulated, it is the task of the designer to develop hardware for
the system. Computer design is concerned with the determination of what hardware should be
used and how the parts should be connected. This aspect of computer hardware is sometimes
referred to as computer implementation.

Computer Architecture
Computer architecture is concerned with the structure and behavior of the computer as
seen by the user. It includes the information formats, the instruction set, and techniques for
addressing memory. The architectural design of a computer system is concerned with the
specifications of the various functional modules, such as processors and memories, and
structuring them together into a computer system.

Register Transfer Language

Digital systems vary in size and complexity from a few integrated circuits to a complex
of interconnected and interacting digital computers. Digital system design invariably uses a
modular approach. The modules are constructed from such digital components as registers,
decoders, arithmetic elements, and control logic. The various modules are interconnected
with common data and control paths to form a digital computer system. Digital modules are
best defined by the registers they contain and the operations that are performed on the data
stored in them. The operations executed on data stored in registers are called micro
operations. A micro operation is an elementary operation performed on the information
stored in one or more registers. The result of the operation may replace the previous binary
information of a register or may be transferred to another
register. Examples of mcirooperations are shift, count, dear, and load.
The internal hardware organization of a digital computer is best defined by
specifying:
1- The set of registers it contains and their function.
2- The sequence of micro operations performed on the binary information stored in
theregisters.
 3- The control that initiates the sequence of micro operations.
The symbolic notation used to describe the micro operation transfers among registers is
called a register transfer language.
The term "register transfer" implies the availability of hardware logic circuits that can
perform a stated micro operation and transfer the result of the operation to the same or
another register.
The word "language" is borrowed from programmers, who apply this term to
programming languages.
A register transfer language is a system for expressing in symbolic form the micro operation
sequences among the registers of a digital module.
Register Transfer
Computer registers are designated by capital letters (sometimes followed by numerals)
to denote the function of the register.
The representation of registers in block diagram form is shown in Fig(2):

a- Rectangular box with the name of the register inside.

b- The individual bits.
c- The numbering of bits in a 16-bit register can be marked on top of the box.
d- 16-bit register is partitioned into two parts. Bits 0 through 7 are assigned the symbol
L(for low byte) and bits 8 through 15 are assigned the symbol H (for high byte).
The name of the 16-bit register is PC. The symbol PC(0-7) or PC(L) refers to the
low-orderbyte and PC(8-15) or PC(H) to the high-order byte.

Information transfer from one register to another is designated in symbolic form by means
of a replacement operator. The statement:
𝑅2 ← 𝑅1
Denotes a transfer of the content of register Rl into register R2. It designates a
replacement of the content of R2 by the content of Rl. By definition, the content of the source
register Rl does not change after the transfer.

If we want the transfer to occur only under a predetermined control condition. This can
be shown by means of an if-then statement.
(𝑃 = 1)𝑡ℎ𝑒𝑛(𝑅2 ← 𝑅1)
where P is a control signal generated in the control section. It is sometimes convenient
to separate the control variables from the register transfer operation control function by
specifying a control function.
 𝑃: 𝑅2 ← 𝑅1
The control condition is terminated with a colon. It symbolizes the requirement that the
transfer operation be executed by the hardware only if P = 1.

To separate two or more operations that is executed at the same time by using the comma as
the statement:
𝑇: 𝑅2 ← 𝑅1, 𝑅5 ← 𝑅3

The basic symbols of the register transfer notation are listed in Table (1) Registers are
denoted by capital letters, and numerals may follow the letters. Parentheses are used to denote
a part of a register by specifying the range of bits or by giving a symbol name to a portion of a
register.

Bus and Memory Transfers

A typical digital computer has many registers, and paths must be provided to transfer
information from one register to another. The number of wires will be excessive if separate
lines are used between each register and all other registers in the system. A bus
structureconsists of a set of common lines, one for each bit of a register, through
which binaryinformation is transferred one at a time. Control signals determine which register
is selected bythe bus during each particular register transfer. The multiplexers select the
source registerwhose binary information is then placed on the bus. For example, the
construction of a bussystem for four registers is shown in Fig(3) Each register has four bits,
numbered 0 through 3.The bus consists of four 4x1 multiplexers each having four data
inputs, 0 through 3, and twoselection inputs, S1 and S0.
The table(2) shows the register that is selected by the bus for each of the four possible
binary values of the selection lines.

The symbolic statement for a bus transfer may mention the bus or its presence may be
implied in the statement. When the bus is includes in the statement, the register transfer is
symbolized as follows:
𝐵𝑢𝑠 ← , 𝑅1 ← 𝐵𝑢𝑠
The content of register C is placed on the bus, and the content of the bus is loaded into
register Rl by activating its load control input. If the bus is known to exist in the system,
itmay be convenient just to show the direct transfer.
𝑅1 ← 𝐶
A bus system can be constructed with three-state gates. The graphic symbol of a three-
state buffer gate is shown:

To construct a common bus for four registers of n bits each using three-state buffers, we need
n circuits with four buffers in each as shown in Fig(4). Each group of four buffers receives one
significant bit from the four registers.
 The transfer of information from a memory word to the outside environment is called a
read operation. The transfer of new information to be stored into the memory is called a write
operation. Consider a memory unit that receives the address from a register, called the address
register, symbolized by AR. The data are transferred to another register, called the data
register, symbolized by DR.
𝑅𝑒𝑎𝑑: 𝐷𝑅 ← 𝑀[𝐴𝑅]
The write operation transfers the content of a data register to a memory word M selected by
the address.
𝑊𝑟𝑖𝑡𝑒: 𝑀[𝐴𝑅] ← 𝐷𝑅

Arithmetic Microoperations
The arithmetic operations are listed in the Table(3):

The multiply and divide are not listed in Table(3), these two operations are valid
arithmetic operations but are not included in the basic set of micro operations. In most
computers, the multiplication operation is implemented with a sequence of add and shift micro
operations. Division is implemented with a sequence of subtract and shift micro operations.
The digital circuit that generates the arithmetic sum of two binary numbers of any length is
called a binary adder as shown in Fig(5).
The addition and subtraction operations can be combined into one common circuit by
including an exclusive-OR gate with each full-adder as shown in Fig(6).

The increment micro operation adds one to a number in a register. For example, if a 4-bit
register has a binary value 0110, it will go to 0111 after it is incremented. The diagram of a 4-
bit combinational circuit incrementer is shown in Fig(7):
The arithmetic micro operations listed in the Table above can be implemented in one
composite arithmetic circuit. The basic component of an arithmetic circuit is the parallel adder.
By controlling the data inputs to the adder, it is possible to obtain different types of arithmetic
operations as shown in Fig(8).

It is possible to generate the eight arithmetic micro operations listed in Table(4):

 Logic Micro operations
Logic micro operations specify binary operations for strings of bits stored in registers.
These operations consider each bit of the register separately and treat them as binary variables.
For example, the exclusive-OR micro operation with the contents of two registers Rl and R2 is
symbolized by the statement:
𝑃: 𝑅1 ← 𝑅1 ⊕ 𝑅2
It specifies a logic micro operation to be executed on the individual bits of the registers
provided that the control variable P = 1. As a numerical example, assume that each register has
four bits. Let the content of Rl be 1010 and the content of R2 be 1100. The exclusive-OR
micro operation stated above symbolizes the following logic computation:

There are 16 different logic operations that can be performed with two binary variables. They
can be determined from all possible truth tables obtained with two binary variables as shown
in Table(5):

The 16 Boolean functions of two variables x and y are expressed in algebraic form in the first
column of Table(6):
The diagram shows (Fig 9-a) one typical stage with subscript i. For a logic circuit with n bits,
the diagram must be repeated n times for i = 0,1, 2,..., n - 1. The selection variables are applied
to all stages. The function table in Fig.(9-b) lists the logic micro operations obtained for each
combination of the selection variables.

Shift Microoperations
Shift micro operations are used for serial transfer of data. The contents of a register can
be shifted to the left or the right. There are three types of shifts: logical, circular, and
arithmetic. The symbolic notation for the shift micro operations is shown in Table (7):
 An arithmetic shift is a micro operation that shifts a signed binary number to the left or
right. The arithmetic shift-left inserts a 0 into R0, and shifts all other bits to the left. The initial
bit of Rn-1 is lost and replaced by the bit from R n-2 . A sign reversal occurs if the bit in R n-1
changes in value after the shift and caused an overflow.
The arithmetic shift-right leaves the sign bit unchanged and shifts the number (including the
sign bit) to the right.

Ex: If the content of 8 bits register is (10100011). What is the result of the operation after
executing to the register:
a. shl R: shift left register by 3. b. cil R : circular shift left register by 3.
c. ashl R: arithmetic shift left register by 3. d. ashr R: arithmetic shift right
register by 3.Ans:
(a) 00011000. (b) 00011101. (c) 00011000. Overflow (d) 11110100
 A combinational circuit shifter can be constructed with multiplexers as shown in
Fig(10). The 4-bit shifter has four data inputs, A0 through A3, and four data outputs,
H0through H3. There are two serial inputs, one for shift left (IL) and the other for shift right (IR).
 Arithmetic Logic Shift Unit
Computer systems employ a number of storage registers connected to a common
operational unit called an arithmetic logic unit, aONLINE/BBreviated ALU. The arithmetic,
logic, and shift circuits introduced in previous sections can be combined into one ALU with
common selection variables. One stage of an arithmetic logic shift unit is shown in Fig(11)
with the functional table(8):
Basic Structure of Computers
Computer Architecture in general covers three aspects of computer design namely: Computer
Hardware, Instruction set Architecture and Computer Organization.

Computer hardware consists of electronic circuits, displays, magnetic and optical storage media
and communication facilities.

Instruction set Architecture is programmer visible machine interface such as instruction set,
registers, memory organization and exception handling. Two main approaches are mainly CISC
(Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer)

Computer Organization includes the high level aspects of a design, such as memory
system, the bus structure and the design of the internal CPU.

Instruction Codes
A computer instruction is a binary code that specifies a sequence of micro operations
forthe computer. Instruction codes together with data are stored in memory. The computer
reads each instruction from memory and places it in a control register. The control then
interprets thebinary code of the instruction and proceeds to execute it by issuing a sequence of
micro operations. Every computer has its own unique instruction set. The ability to store and
execute instructions, the stored program concept, is the most important property of a general-
purpose computer. An instruction code is a group of bits that instruct the computer to perform
a specific operation. It is usually divided into parts, each having its own particular
interpretation. The most basic part of an instruction code is its operation part. The operation
code of an instruction is a group of bits that define such operations as add, subtract, multiply,
shift, and complement. The number of bits required for the operation code of an instruction
depends on the total number of operations available in the computer.
The simplest way to organize a computer is to have one processor register and an
instruction code format with two parts. The first part specifies the operation to be performed
and the second specifies an address. The memory address tells the control where to find an
operand in memory. This operand is read from memory and used as the data to be operated on
together with the data stored in the processor register.
For a memory unit with 4096 words we need 12 bits to specify an address
12
since2 = 4096. If we store each instruction code in one 16-bit memory word, we have
available four bits for the operation code (aONLINE/BBreviated opcode) to specify one out of
16 possibleoperations, and 12 bits to specify the address of an operand. The control reads a 16-
bit instruction from the program portion of memory. It uses the 12-bit address part of the
instruction to read a 16-bit operand from the data portion of memory. Fig(12) depicts this type
of organization.

Computers that have a single-processor register usually assign to it the name accumulator and
label it AC.

For example, operations such as clear AC, complement AC, and increment AC operate on data
stored in the AC register.
When the second part of an instruction immediate code specifies an operand, this type is
called immediate operand. When the second part specifies the address of an operand, the
instruction is said to have a direct address. The third possibility called indirect address,
where the bits in the second part of the instruction designate an address of a memory word in
which the address of the operand is found. One bit of the instruction code can be used to
distinguish between a direct and an indirect address.
As an illustration of this configuration, consider the instruction code format shown in Fig(13).

Computer Registers
Computer instructions are normally stored in consecutive memory locations and are
executed sequentially one at a time. The control reads an instruction from a specific address in
memory and executes it. It then continues by reading the next instruction in sequence and
executes it, and so on. This type of instruction sequencing needs a counter to calculate the
address of the next instruction after execution of the current instruction is completed. The
computer needs processor registers for manipulating data and a register for holding a memory
address. These requirements dictate the register configuration are listed in Table(9) and
shown in Fig(14).

The basic computer has eight registers, a memory unit, and a control unit. The
connection of the registers and memory of the basic computer to a common bus system is
shown in Fig(15).
Two registers, AR and PC, have 12 bits each since they hold a memory address. When
the contents of AR or PC are applied to the 16-bit common bus, the four most significant bits
are set to 0's. When AR or PC receives information from the bus, only the 12 least significant
bits are transferred into the register.
The input register INPR and the output register OUTR have 8 bits each and
communicate with the eight least significant bits in the bus. The INPR receives a character
from an input device which is then transferred to AC. OUTR receives a character from AC and
delivers it to an output device. There is no transfer from OUTR to any of the other registers.
Five registers have three control inputs: LD (load), INR (increment), and CLR (clear).
 Computer Instructions
The basic computer has three instruction code formats, as shown in Figure. Each format
has 16 bits.
 The type of instruction is recognized by the computer control from the four bits in
positions 12through 15 of the instruction. If the three opcode bits in positions 12 through 14
are not equal to 111, the instruction is a memory-reference type and the bit in position 15 is
taken as the addressing mode J. If the 3-bit opcode is equal to 111, control then inspects the bit
in position 15. If this bit is 0, the instruction is a register-reference type. If the bit is 1, the
instruction is an input-output type. Note that the bit in position 15 of the instruction code is
designated by the symbol J but is not used as a mode bit when the operation code is equal to
111.
The instructions for the computer are listed in Table(10):

The set of instructions are said to be complete if the computer includes a

sufficientnumber of instructions in each of the following categories:
1. Arithmetic, logical, and shift instructions.
2. Instructions for moving information to and from memory and processor registers.
3. Instructions that check status information to provide decision making capabilities.
4. Input and output instructions.
 5. The capability of stopping the computer
Instruction Cycle
A program residing in the memory unit of the computer consists of a sequence of
instructions. The program is executed in the computer by going through a cycle for each
instruction. In the basic computer each instruction cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
This process continues indefinitely unless a HALT instruction is encountered. Initially, the
program counter PC is loaded with the address of the first instruction in the program. The
sequence counter SC is cleared to 0, providing a decoded timing signal T0. After each clock
pulse, SC is incremented by one, so that the timing signals go through a sequence T 0, T1, T2,
and so on. The micro operations for the fetch and decode phases can be specified by the
following register transfer statements.
𝑇0: 𝐴𝑅 ← 𝑃𝐶
𝑇1: 𝐼𝑅 ← [𝐴𝑅], 𝑃𝐶 = 𝑃𝐶 + 1
𝑇2: 𝐷0, , , , 𝐷7 ← 𝐷𝑒𝑐𝑜𝑑𝑒 𝐼𝑅(12 − 14), 𝐴𝑅 ← 𝐼𝑅(0 − 11), 𝐼 ← 𝐼𝑅(15)
It is necessary to use timing signal T1 to provide the following connections in the bus system.

1. Enable the read input of memory.

2. Place the content of memory onto the bus by making S2S1S0 =111.
3. Transfer the content of the bus to IR by enabling the LD input of IR.
4. Increment PC by enabling the INR input of PC.
Memory - Reference Instructions
The table(11) lists the seven memory-reference instructions. The decoded output D,
fori = 0,1, 2, 3, 4, 5, and 6 from the operation decoder that belongs effective address to each
instruction is included in the table. The effective address of the instruction is in the address
register AR and was placed there during timing signal T2 when I = 0, or during timing signal
T3 when I=1. The symbolic description of each instruction is specified in the table in terms of
register transfer notation. The actual execution of the instruction in the bus system will require
a sequence of micro operations.
UNIT-2
Micro programmed Control and Central Processing Unit

Control Memory
The function of the control unit in a digital computer is to initiate sequences of micro
operations. The number of different types of micro operations that are available in a given
system is finite.A control unit whose binary control variables are stored in memory is called a
micro programmed control unit. Each word in control memory contains within it a
microinstruction. The microinstruction specifies one or more micro operations for the
system.A sequence of microinstructions constitutes a micro program.
A computer that employs a micro programmed control unit will have two separate memories: a
main memory and a control memory. The main memory is available to the user for storing the
programs. The contents of main memory may alter when the data are manipulated and every
time that the program is changed. The user's program in main memory consists of
machine instructions and data. While the control memory holds a fixed micro program that
cannot be altered by the occasional user.
The general configuration of a micro programmed control unit is demonstrated in the block
diagram of Fig(21).

Address Sequencing
Microinstructions are stored in control memory in groups, with each group routine
specifying a routine. An initial address is loaded into the control address register when power
is turned on in the computer. This address is usually the address of the first microinstruction
that activates the instruction fetch routine. The fetch routine may be sequenced by
incrementing the control address register through the rest of its microinstructions.
In summary, the address sequencing capabilities required in a control memory are:
1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.
Instruction format:
 The computer instruction format is depicted in Fig(22-a). It consists of three fields: a 1-
bit held for indirect addressing symbolized by J, a 4-bit operation code (opcode), and an 11-
bit address field. Fig(22-b) lists four of the 16 possible memory-reference instructions.

Microinstruction Format
The microinstruction format for the control memory is shown in Fig(23). The format
20 bits of the microiristruction are divided into four functional parts. The three fields Fl, F2,
and F3 specify micro operations for the computer. The CD field selects status bit conditions.
The BR field specifies the type of branch to be used. The AD field contains a branch address.
The address field is seven bits wide, since the control memory has 128 = 27 words.
The micro operations are subdivided into three fields of three bits each. The three bits in each
field are encoded to specify seven distinct micro operations as listed in Table(13). This gives a
total of 21 micro operations.
The CD (condition) field consists of two bits which are encoded to specify four status bit
conditions as listed in Table. The first condition is always a 1, so that a reference to CD = 00
(or the symbol U) will always find the condition to be true. When this condition is used in
conjunction with the BR (branch) field, it provides an unconditional branch operation. The
indirect bit I is available from bit 15 of DR after an instruction is read from memory. The sign

bit of AC provides the next status bit.

 Design of Control Unit
The Fig(24) shows the three decoders and some of the connections that must be made
from their outputs. Each of the three fields of the microinstruction presently available in the
output of control memory are decoded with a 3x8 decoder to provide eight outputs. For
example, when Fl = 101 (binary 5), the next clock pulse transition transfers the content of
DK(0-10) to AR (symbolized by DRTAR in Table). Similarly, when Fl = 110 (binary 6) there
is a transfer from PC to AR (symbolized by PCTAR).

Central Processing Unit

The CPU is made up of three major parts, as shown in Fig(25).
1- The register set stores intermediate data used during the execution of the instructions.
The arithmetic
2- logic unit (ALU) performs the required micro operations for executing the instructions.
3- The control unit supervises the transfer of information among the registers and
instructsthe ALU as to which operation to perform.
 General Register Organization
The memory locations are needed for storing pointers, counters, return addresses,
temporary results, and partial products during multiplication.
A bus organization for seven CPU registers is shown in Fig(26):
 The control unit that operates the CPU bus system directs the information flow through
the registers and ALU by selecting the various components in the system. For example, to
perform the operation:
𝑅1 ← 𝑅2 + 𝑅3

The control must provide binary selection variables to the following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic addition A + B.
4. Decoder destination selector (SELD): to transfer the content of the output bus into Rl.To
achieve a fast response time, the ALU is constructed with high-speed circuits.
There are 14 binary selection inputs in the unit, and their combined value control word
specifies a control word. The three bits of SELA select a source register for the A input of the
ALU. The three bits of SELB select a register for the B input of the ALU. The three bits of
SELD select a destination register using the decoder and its seven load outputs. The five bits
of OPR select one of the operations in the ALU.
The encoding of the register selections is specified in Table(14):

Table(15) OPR field has five bits and each operation is designated with a symbolic name.
 For example, the subtract micro operation given by the statement:

𝑅1 ← 𝑅2 − 𝑅3

The binary control word for the subtract micro operation is 010 01l 001 00101 and is obtained
as follows:

Stack Organization
A useful feature that is included in the CPU of most computers is a stack or last-in,
first-out (LIFO) list. The two operations of a stack are the insertion and deletion of items. The
operation of insertion is called push, while the operation of deletion is called pop. In a 64-word
stack, the stack pointer contains 6 bits because 26 = 64.
The push operation is implemented with the following sequence of microoperations:

The pop operation consists of the following sequence of micro operations:

Instruction Formats
The format of an instruction is usually depicted in a rectangular box symbolizing the
bits of the instruction as they appear in memory words or in a control register. The bits of the
instruction are divided into groups called fields. The most common fields found in instruction
formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is determined.
An example of an accumulator-type organization, the instruction that specifies an arithmetic
addition is defined by an assembly language instruction as:

𝐴𝐷𝐷 𝑋
Where 𝑋 is the address of the operand. The ADD instruction in this case results in the
operation:
𝐴𝐶 ← 𝐴𝐶 + 𝑀[𝑋]
An example of a general register type of organization the instruction for an arithmetic addition
may be written in an assembly language as:
𝐴𝐷𝐷 𝑅1, 𝑅2, 𝑅3
to denote the
operation: 𝑅1 ← 𝑅2 + 𝑅3
The following is a program to evaluate 𝑋 = (𝐴 + 𝑏) ∗ (𝐶 + 𝐷) :
with three-address instruction formats as:

Two-address instructions formats as:

One-address instructions use an implied accumulator (AC) register for all data manipulation
as:

Addressing Modes
Computers use addressing mode techniques for the purpose of accommodating one or
both of the following provisions:
1. To give programming versatility to the user by providing such facilities as pointers to
memory, counters for loop control, indexing of data, and program relocation.
2. To reduce the number of bits in the addressing field of the instruction.
PC holds the address of the instruction to be executed next and is incremented each time an
instruction is fetched from memory. An example of an instruction format with a distinct
addressing mode field is shown in Fig(27).
 Immediate Mode: In this mode the operand is specified in the instruction itself. In other
words, an immediate-mode instruction has an operand field rather than an address field.
Register Mode: In this mode the operands are in registers that reside within the CPU. The
particular register is selected from a register field in the instruction.
Register Indirect Mode: In this mode the instruction specifies a register in the CPU whose
contents give the address of the operand in memory.
Auto-increment or Auto-decrement Mode: This is similar to the register indirect mode
except that the register is incremented or decremented after (or before) its value is used to
access memory.
The effective address is defined to be the memory address obtained from the computation
dictated by the given addressing mode.
Direct Address Mode: In this mode the effective address is equal to the address part of the
instruction.
Indirect Address Mode: In this mode the address field of the instruction gives the address
where the effective address is stored in memory.
The effective address in these modes is obtained from the following computation:
effective address = address part of instruction + content of CPU register
Relative Address Mode: In this mode the content of the program counter is added to the
address part of the instruction in order to obtain the effective address.
Indexed Addressing Mode: In this mode the content of an index register is added to the
address part of the instruction to obtain the effective address.
Base Register Addressing Mode: In this mode the content of a base register is added to the
address part of the instruction to obtain the effective address.

Numerical Example:
1- The two-word instruction at address 200 and 201 is a "load to AC" instruction with
anaddress field equal to 500.
2- The first word of the instruction specifies the operation code and mode, and the
secondword specifies the address part.
3- PC has the value 200 for fetching this instruction.
4- The content of processor register Rl is 400, and the content of an index register XR
is100.
AC receives the operand after the instruction is executed. The Fig(28) lists a few pertinent
addresses and shows the memory content at each of these addresses.
Answer:
1- In the direct address mode the effective address is the address part of the instruction
500and the operand to be loaded into AC is 800.
2- In the immediate mode the second word of the instruction is taken as the operand
ratherthan an address, so 500 is loaded into AC. (The effective address in this case is
201)
3- In the indirect mode the effective address is stored in memory at address 500.
Therefore,the effective address is 800 and the operand is 300.
4- In the relative mode the effective address is 500 + 202 = 702 and the operand is
325.(Note that the value in PC after the fetch phase and during the execute phase is
202)
5- In the index mode the effective address is XR + 500 = 100 + 500 = 600 and the
operandis 900.
6- In the register mode the operand is in Rl and 400 is loaded into AC. (There is
noeffective address in this case)
7- In the register indirect mode the effective address is 400, equal to the content of Rl
andthe operand loaded into AC is 700.
8- The auto-increment mode is the same as the register indirect mode except that Rl
isincremented to 401 after the execution of the instruction.
9- The auto-decrement mode decrements Rl to 399 prior to the execution of the instruction.
The operand loaded into AC is now 450.
Table (16) lists the values of the effective address and the operand loaded into AC for the
nine addressing modes.
 CISC Characteristics

A computer with large number of instructions is called complex instruction set computer or
CISC. Complex instruction set computer is mostly used in scientific computing applications
requiring lots of floating point arithmetic.

1. A large number of instructions - typically from 100 to 250 instructions.

2. Some instructions that perform specialized tasks and are used infrequently.
3. A large variety of addressing modes - typically 5 to 20 different modes.
4. Variable-length instruction formats
5. Instructions that manipulate operands in memory.

RISC Characteristics

A computer with few instructions and simple construction is called reduced instruction set
computer or RISC. RISC architecture is simple and efficient. The major characteristics of RISC
architecture are,

1. Relatively few instructions

2. Relatively few addressing modes
3. Memory access limited to load and store instructions
4. All operations are done within the registers of the CPU
5. Fixed-length and easily-decoded instruction format.
6. Single cycle instruction execution
7. Hardwired and micro programmed control.
 Introduction about Program Control:-

A program that enhances an operating system by creating an environment in which you

can run other programs. Control programs generally provide a graphical interface and enable
you to run several programs at once in different windows.

Control programs are also called operating environments.

The program control functions are used when a series of conditional or unconditional jump
and return instruction are required. These instructions allow the program to execute only certain
sections of the control logic if a fixed set of logic conditions are met. The most common
instructions for the program control available in most controllers are described in this section.

Introduction About status bit register:-

A status register, flag register, or condition code register is a collection of status flag
bits for a processor. An example is the FLAGS register of the computer architecture. The flags
might be part of a larger register, such as a program status word (PSW) register.

The status register is a hardware register which contains information about the state of
the processor. Individual bits are implicitly or explicitly read and/or written by the machine
code instructions executing on the processor. The status register in a traditional processor design
includes at least three central flags: Zero, Carry, and Overflow, which are set or cleared
automatically as effects of arithmetic and bit manipulation operations. One or more of the flags
may then be read by a subsequent conditional jump instruction (including conditional calls,
returns, etc. in some machines) or by some arithmetic, shift/rotate or bitwise operation, typically
using the carry flag as input in addition to any explicitly given operands. There are also
processors where other classes of instructions may read or write the fundamental zero, carry or
overflow flags, such as block-, string- or dedicated input/output instructions, for instance.

Some CPU architectures, such as the MIPS and Alpha, do not use a dedicated flag register.
Others do not implicitly set and/or read flags. Such machines either do not pass implicit status
information between instructions at all, or do they pass it in a explicitly selected general purpose
register.

A status register may often have other fields as well, such as more specialized
flags, interrupt enable bits, and similar types of information. During an interrupt, the status of the
thread currently executing can be preserved (and later recalled) by storing the current value of
the status register along with the program counter and other active registers into the machine
stack or some other reserved area of memory.
 UNIT-IV

Input-Output Organization and Memory Organization

Input-Output Organization
The input-output subsystem of a computer, referred to as I/O, provides an
efficientmode of communication between the central system and the outside environment.
Programs and data must be entered into computer memory for processing and results obtained
from computations must be recorded or displayed for the user.
Peripheral Devices
Input or output devices attached to the computer are also called peripherals.
 The display terminal can operate in a single-character mode where all characters
entered on the screen through the keyboard are transmitted to the computer
simultaneously. In the block mode, the edited text is first stored in a local memory
inside the terminal. The text is transferred to the computer as a block of data.
 Printers provide a permanent record on paper of computer output data.
 Magnetic tapes are used mostly for storing files of data.
 Magnetic disks have high-speed rotational surfaces coated with magnetic material.

Introduction about Input Output Organization:-

Input Output Organization:

I/O operations are accomplished through external devices that provide a means of exchanging
data between external environment and computer. An external device attaches to the computer
by a link to an I/O module. An external device linked to an I/O module is called peripheral
device or peripheral. The figure below shows attachment of external devices through I/O
module.

External Devices can be categorized as

1. Human readable: suitable for communicating with computer user. For example - video
display terminals and printers.
2. Machine readable: suitable for communicating with equipment. For example - sensor,
actuators used in robotics application.
3. Communication: suitable for communicating with remote devices. They may be human
readable device such as terminal and machine readable device such as another computer.

Block diagram of external device is described below.

 1. The interface to I/O module: The interface to I/O module is in the form of

a) Control Signal – determines the function that the device will perform. E.g. send data to I/O
module (READ or INPUT), receive data from I/O module (WRITE or OUTPUT), report status
or perform some control function such as position a disk head. b) Data Signal – send or receive
the data from I/O module. c) Status Signal – it indicates the status of signal. E.g. READY/NOT
READY

1. Control Logic: associated with the device controls on specific operation as directed from
I/O module.
2. Transducer: converts the data from electrical to other form of energy during output and
from other forms of electrical during input.
3. Buffer: is associated with transducer to temporarily hold data during data transmission
from I/O module and external environment. Buffer size of 8 to 16 bits is common.

Introduction about input-output interface:-

An I/O interface is required whenever the I/O device is driven by the processor. The interface
must have necessary logic to interpret the device address generated by the processor.
Handshaking should be implemented by the interface using appropriate commands (like BUSY,
READY, and WAIT), and the processor can communicate with an I/O device through the
interface.

It would not be practical for every I/O device to be wired to the computer in a different way, so
we must have a scheme where the hardware connections are fixed, and yet the communication
with the device is flexible, so that the widely varying needs of devices can all be met.

An I/O device, from the viewpoint of the CPU, is a set of registers. The CPU communicates with
and controls the I/O device by reading and writing these registers. For example, SPIM, the MIPS
simulator, uses two registers to communicate with the keyboard.

 The keyboard data register contains the ASCII code of the last key pressed.
 The keyboard control register indicates when a new key has been pressed. If bit 0 is one,
a key has been pressed since the last character was read. The keyboard controller sets this
bit when a key is pressed. It clears this bit when the keyboard data register is read.
The CPU can find out whether a new character is available by reading the keyboard control
register and testing bit 0. If bit 0 is 1, it then reads the keyboard data register to get the new key.

Accessing I/O devices at the hardware level is a lot like accessing memory. The registers in the
I/O devices are connected to the CPU using buses. We need an address bus to specify which I/O
device register is to be accessed. We need control lines to specify what kind of access is desired
(read, write, reset, etc.) Finally, we need a data bus to transfer the data between the CPU and the
device.

Each device has one or more control, status, and data registers at various I/O addresses. A
hypothetical example:

Address Register

ff00 keyboard status

ff01 keyboard data
ff02 display status
ff03 display data
ff04 disk status
ff05 disk block address
ff06 disk block size
ff07 disk data address
...

I/O read and write operations can be more complex than memory read and write operations, but
the basic idea is the same. I/O control generally involves more than just read and write control
lines. In a sense, memory can be viewed as a very simple, fast I/O device.

Whereas memory is just a large pool of slow, inexpensive registers for storing data, each I/O
device register has a unique purpose in controlling a specific I/O device. This does not affect
how the CPU accesses them at the hardware level, but it does affect how they are used by
software.

Simple device control, such as stating whether an I/O register is to be read or written, can be
done over the control lines. More complex devices are often controlled by sending special data
blocks called Peripheral Control Blocks (PCBs) over the data lines. This is the primary method
for communicating with disk drives, for example.

Since I/O devices are of a very different nature than CPU circuits, there must be interface
hardware to connect each device to the CPU.

Example of I/O Interface

An example of an I/O interface unit is shown in figure. It consists of two data registers called
ports, a control register, a status register, bus buffers and timing and control circuits.

The four registers communicate directly with the I/O device attached to the interface. The I/O
data to and from the device can be transferred into either port A or port B. Port A may be
defined as an input port and port B may be defined as an output port. The output device such as
magnetic disk transfers data in both directions. So bidirectional data bus is used. CPU gives
control information to control register. The bits in the status register are used for status
conditions. It is also used for recording errors that may occur during the data transfer. The bus
buffers use the bidirectional data bus to communicate with the CPU. A timing and control circuit
is used to detect the address assigned to the bus buffers.

Register
CS RS1 RS0
selected
None: data bus
0 X X in high-
impedance
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register

There are basically three type of input-output interfaces. These are as:-
1. I/O bus and interface modules,.

2. I/O versus memory bus.

3. isolated versus memory-mapped I/O.

Introduction About Input-Output Bus And Interface Module:-

The processor of computer is communicate with several peripheral devices such as keyboard,
VDU, Printer, magnetic disk, magnetic tape, etc.

Each peripheral device has its own interface . Each interface communicate with i/o bus. The
communication link between processor and peripherals is shown as below:-

Each interface decode addresses and control receive from input-output bus and interpret them for
peripherals and provide signal for peripheral controller . It synchronize data flow at supervise the
transfer between peripherals and CPU. Each peripheral has its own controller.

For example:- Printer controller control the paper motion , the printing time and selection of
printing characters.

The input-output bus fro the processor is attached to all peripheral interfaces.

The input-output bus three lines:

1. Data line

2. Address line.

3. Control line.

1. Data line:-Data line of input-output bus carry the data to and from the peripherals.

1. Address line:-Address line contain the address of data and instructions.

1. Control line:-It contain control instructions in the form of function and input-output
command.These command control instruction are of four types:-

1.Control Command

2.Status Command

3.Data output Command

4. Data input Command

1. Control Command:-A control command is issue to activate the peripheral and to inform it
what to do.

2.Status Command:-A Status command is used to test the various status condition in the
interface and the peripheral.

3.Data output Command:-A Data output command is responsible for transfering the data from
the bus into peripherals.

3.Data output Command:-A Data output command is responsible for transfering the data from
the peripherals into input-output bus.

Introduction About Asynchronous Data Transfer:-

Asynchronous Data Transfer

The internal operations in a digital system are synchronized by means of clock pulses supplied
by a common pulse generator. Clock pulses are applied to all registers within a unit and all data
transfers among internal registers occur simultaneously during the occurrence of a clock pulse.
Two units, such as a CPU and an I/O interface, are designed independently of each other.

If the registers in the interface share a common clock with the CPU registers, the transfer
between the two units is said to be synchronous. In most cases, the internal timing in each unit is
independent from the other in that each uses its own private clock for internal registers.

In that case, the two units are said to be asynchronous to each other. This approach is widely
used in most computer systems. Asynchronous data transfer between two independent units
requires that control signals be transmitted between the communicating units to indicate the time
at which data is being transmitted. One way of achieving this is by means of a strobe pulse
supplied by one of the units to indicate to the other unit when the transfer has to occur.

Another method commonly used is to accompany each data item being transferred with a
control signal that indicates the presence of data in the bus. The unit receiving the data item
responds with another control signal to acknowledge receipt of the data. This type of agreement
between two independent units is referred to as handshaking.

The strobe pulse method and the handshaking method of asynchronous data transfer are not
restricted to I/O transfers. In fact, they are used extensively on numerous occasions requiring the
transfer of data between two independent units. In the general case we consider the transmitting
unit as the source and the receiving unit as the destination.

For example, the CPU is the source unit during an output or a write transfer and it is the
destination unit during an input or a read transfer. It is customary to specify the asynchronous
transfer between two independent units by means of a timing diagram that shows the timing
relationship that must exist between the control signals and the data in the buses. The sequence
of control during an asynchronous transfer depends on whether the transfer is initiated by the
source or by the destination unit.

There are two types of asynchronous data transmittion methods:-

1. Strobe control

2. Handshaking.

Strobe Control

This method of asynchronous data transfer uses a single control line to time each transfer. The
strobe may be activated by the source or the destination unit.

(i) Source Initiated Data Transfer:

 The data bus carries the information from source to destination. The strobe is a single
line. The signal on this line informs the destination unit when a data word is available in
the bus.
 The strobe signal is given after a brief delay, after placing the data on the data bus. A
brief period after the strobe pulse is disabled the source stops sending the data.

Source - initiated strobe for data transfer

(ii) Destination Initiated Data Transfer:

  In this case the destination unit activates the strobe pulse informing the source to send
data. The source places the data on the data bus. The transmission is stopped briefly after
the strobe pulse is removed.
 The disadvantage of the strobe is that the source unit that initiates the transfer has no way
of knowing whether the destination unit has received the data or not. Similarly if the
destination initiates the transfer it has no way of knowing whether the source unit has
placed data on the bus or not. This difficulty is solved by using hand shaking method of
data transfer.

Destination - initiated strobe for data transfer

A Handshaking Protocol

 Three control lines

 ReadReq: indicate a read request for memory

Address is put on the data lines at the same time

  DataRdy: indicate the data word is now ready on the data lines

Data is put on the data lines at the same time

 Ack: acknowledge the ReadReq or the DataRdy of the other party

Asynchronous Serial Transfer

The transfer of data between tow units my be done in parallel or serial. in parallel data
transmission, total message is transmitted at the same time. In serial data transmission, each bit
in the message is sent in sequence one at a time. In asynchronous transmission, binary
information is sent only when it is available and the line remains idle when there is no
information to be transmitted.

Asynchronous serial transmission

Asynchronous serial transmission is character oriented. Each character transmitter consists of

a start bit, character bits, and stop bits. The first bit is called the start bit. It is always a 0 and is
used to indicate the beginning of a character. The last bit called the stop bit is always a 1.

Introduction About Mode of transfer:-

Mode of transfer are work in between CPU and peripherals. Input peripherals sends the data to
memory which is computed by CPU. The computed data is further send back to the memory and
further to output peripherals.

CPU merely execute the input-output instruction and may accept the data temporary but ultimate
source and destination is the memory location.

Data transfer between CPU and input-output devices may be handled in variety of modes. these
are:-

1. Programmed input-output.

2. Interrupt initiated input-output.

3. Direct Memory Access input-output.

Programmed I/O

 Programmed I/O operations are the result of I/O instructions written in computer
program. Each data item transfer is initiated by an instruction in the program. The I/O
device does not have direct access to memory. A transfer from an I/O device to memory
requires the execution of several instructions by the CPU. The data transfer can be
synchronous or asynchronous depending upon the type and the speed of the I/O devices.
 If the speeds match then synchronous data transfer is used. When there is mismatch then
asynchronous data transfer is used. The transfer is to and from a CPU register and
peripheral. Other instructions are needed to transfer the data to and from CPU and
memory. This method requires constant monitoring of the peripheral by the CPU. Once a
data transfer is initiated the CPU is required to monitor
 The interface to see when a transfer can again be made. In this method the CPU stays in
a loop till the I/O unit indicates that it is ready for data transfer. This is time consuming
process which can be solved by using interrupt.

Interrupt initiated I/O

In the programmed I/O method, the CPU stays in a program loop until the I/O unit indicates that
it is ready for data transfer. This is a time-consuming process since it keeps the processor busy
needlessly.

It can be avoided by using an interrupt facility and special commands to inform the interface to
issue an interrupt request signal when the data are available from the device.

In the meantime the CPU can proceed to execute another program. The interface meanwhile
keeps monitoring the device. When the interface determines that the device is ready for data
transfer, it generates an interrupt request to the computer.

Upon detecting the external interrupt signal, the CPU momentarily stops the task it is processing,
branches to a service program to process the I/O transfer, and then returns to the task it was
originally performing.

Example of Interrupt initiated I/O:

1. Vectored interrupt
2. Non vectored interrupt

Vectored interrupt :
In vectored interrupt, the source that interrupts supplies the branch information to the computer.
This information is called the interrupt vector.
Non vectored interrupt
In a non vectored interrupt, the branch address is assigned to a fixed location in memory.

Direct Memory Access

DMA Short for direct memory access, a technique for transferring data from main memory to
a device without passing it through the CPU. Computers that have DMA channels can transfer
data to and from devices much more quickly than computers without a DMA channel can. This
is useful for making quick backups and for real-time applications. Some expansion boards, such
as CD-ROM cards, are capable of accessing the computer's DMA channel. When you install the
board, you must specify which DMA channel is to be used, which sometimes involves setting a
jumper or DIP switch.

Direct Memory Access interactions

Direct Memory Access Controller

DMA controller is used to transfer the data between the memory and i/o device.

 The DMA controller needs the usual circuits to communicate with the CPU and i/o device.
 In addition to this, it needs an address register and address bus buffer.
 The address register contains an address of the desired location in memory.
 The word count register holds the number of words to be transferred. The control register
specifies the mode of transfer.
 The DMA communicates with the i/o devices through the DMA request and DMA
acknowledge line.
 The DMA communicates with the CPU through the data bus and control lines.
 The RD (Read) and WR (write) signals are bidirectional.
 When the BG (Bus Grant) signal are bidirectional.
 When the BG (Bus Grant) signal is 0, the CPU can communicate with the DMA registers
through the data bus.
 When BG is 1, the CPU has relinquished the buses. The the DMA can communicate directly
with the memory.

DMA Transfer

The connection between the DMA controller and other components in a computer system for
DMA transfer is shown in figure.

DMA transfer in a computer system

 The DMA request line is used to request a DMA transfer.

 The bus request (BR) signal is used by the DMA controller to request the CPU to
relinquish control of the buses.
 The CPU activates the bus grant (BG) output to inform the external DMA that its buses
are in a high-impedance state (so that they can be used in the DMA transfer.)
 The address bus is used to address the DMA controller and memory at given location
 The Device select (DS) and register select (RS) lines are activated by addressing the
DMA controller.
 The RD and WR lines are used to specify either a read (RD) or write (WR) operation on
the given memory location.
 The DMA acknowledge line is set when the system is ready to initiate data transfer.
 The data bus is used to transfer data between the I/O device and memory.
 When the last word of data in the DMA transfer is transferred, the DMA controller
informs the termination of the transfer to the CPU by means of the interrupt line.
 Memory Hierarchy
The memory unit is an essential component in any digital computer since it is needed
for storing programs and data. The memory unit that communicates directly with the CPU is
called the main memory. Devices that provide backup storage are called auxiliary memory.
They are used for storing system programs, large data files, and other backup information.
Only programs and data currently needed by the processor reside in main memory. All other
information is stored in auxiliary memory and transferred to main memory when needed.
A special very-high-speed memory called a cache is sometimes used to increase the speed of
processing by making current programs and data available to the CPU at a rapid rate. Fig(29)
shows the Memory Hierarchy:

Main Memory The main memory is the central storage unit in a computer system. It is a
relatively large and fast memory used to store programs and data during the computer
operation. The principal technology used for the main memory is based on semiconductor
integrated circuits. Integrated circuit RAM chips are available in two possible operating
modes:
The static RAM consists essentially of internal flip-flops that store the binary information.
The dynamic RAM stores the binary information in the form of electric charges that are
appliedto capacitors.

Associative Memory
Many data-processing applications require the search of items in a table stored in
memory. An assembler program searches the symbol address table in order to extract the
symbol's binary equivalent.
A memory unit accessed by content is called an associative memory or content
addressable memory (CAM). When a word is written in an associative memory is capable of
finding an empty unused location to store the word. When a word is to be read from an
associative memory, the content of the word, or part of the word, is specified. The memory
locates all words which match the specified content and marks them for reading.
The block diagram of an associative memory is shown in Fig(30):
To illustrate with a numerical example, suppose that the argument register A and the key
register K have the bit configuration shown below. Only the three left most bits of A are
compared with memory words because K has l's in these positions.

Word 2 matches the unmasked argument field because the three leftmost bits of the argument
and the word are equal.
Cache Memory
If the active portions of the program and data are placed in a fast small memory, the
average memory access time can be reduced, thus reducing the total execution time of the
program. Such a fast small memory is referred to as a cache memory. It is placed between the
CPU and main memory.
The basic operation of the cache is as follows. When the CPU needs to access memory,
the cache is examined. If the word is found in the cache, it is read from the fast memory. If the
word addressed by the CPU is not found in the cache, the main memory is accessed to read the
word. The performance of cache memory is frequently measured in terms of a quantity called
hit ratio. When the CPU refers to memory and finds the word in cache, it is said to produce a
hit. If the word is not found in cache, it is in main memory and it counts as a miss.
Three types of mapping procedures are of practical interest when considering the
organization of cache memory:
1. Associative mapping
2. Direct mapping
3. Set-associative mapping
 If the active portions of the program and data are placed in a fast small memory, the
average memory access time can be reduced,

 Thus reducing the total execution time of the program

 Such a fast small memory is referred to as cache memory

 The cache is the fastest component in the memory hierarchy and approaches the speed of
CPU component
 When CPU needs to access memory, the cache is examined

 If the word is found in the cache, it is read from the fast memory
 If the word addressed by the CPU is not found in the cache, the main memory is accessed
to read the word
 The performance of cache memory is frequently measured in terms of a quantity called
hit ratio
 When the CPU refers to memory and finds the word in cache, it is said to produce a hit
 Otherwise, it is a miss

 Hit ratio = hit / (hit+miss)

 The basic characteristic of cache memory is its fast access time,
 Therefore, very little or no time must be wasted when searching the words in the cache
 The transformation of data from main memory to cache memory is referred to as a
mapping process, there are three types of mapping:
 Associative mapping
 Direct mapping
 Set-associative mapping

To help understand the mapping procedure, we have the following example:

Associative mapping
 The fastest and most flexible cache organization uses an associative memory

 The associative memory stores both the address and data of the memory word
 This permits any location in cache to store ant word from main memory
 The address value of 15 bits is shown as a five-digit octal number and its corresponding
12-bitword is shown as a four-digit octal number

 A CPU address of 15 bits is places in the argument register and the associative memory us
searched for a matching address
 If the address is found, the corresponding 12-bits data is read and sent to the CPU
 If not, the main memory is accessed for the word

 If the cache is full, an address-data pair must be displaced to make room for a pair that is
needed and not presently in the cache

Direct Mapping
 Associative memory is expensive compared to RAM

 In general case, there are 2^k words in cache memory and 2^n words in main memory (in
our case, k=9, n=15)

 The n bit memory address is divided into two fields: k-bits for the index and n-k bits for
the tag field
 Set-Associative Mapping
 The disadvantage of direct mapping is that two words with the same index in their
address but with different tag values cannot reside in cache memory at the same time

 Set-Associative Mapping is an improvement over the direct-mapping in that each word of

cache can store two or more word of memory under the same index address
  In
the slide, each index address refers to two data words and their associated tags

 Each tag requires six bits and each data word has 12 bits, so the word length is 2*(6+12)
= 36 bits

UNIT-V

Pipeline and Vector Processing and Multi Processors

Pipelining
Pipelining is a technique of decomposing a sequential process into sub-operations; with
each sub-process being executed in a special dedicated segment that operates concurrently
with all other segments. A pipeline can be visualized as a collection of processing
segmentsthrough which binary information flows.
General Considerations
Any operation that can be decomposed into a sequence of sub-operations of about the same
complexity can be implemented by a pipeline processor. The general structure of a four-
segment pipeline is illustrated in Fig. 46. The operands pass through all four segments in a
fixed sequence.
The space-time diagram of a four-segment pipeline is demonstrated in Fig47.

The speedup(S) of a pipeline processing over an equivalent non-pipeline processing is

𝑛𝑡
defined by the ratio: 𝑆= 𝑛
(𝑘+𝑛−1)𝑡𝑝
 As the number of tasks increases, n becomes much larger than 𝑘 − 1, and 𝑘 + 𝑛 − 1
approaches the value of n. Under this condition, the speedup becomes:
𝑡𝑛
𝑆=
𝑡𝑝
numerical example: Let the time it takes to process a sub-operation in each segment be
equal to 𝑡𝑝= 20 ns. Assume that the pipeline has 𝑘 = 4 segments and executes 𝑛 =
100tasks in sequence. The pipeline system will take
(𝑘 + 𝑛 − 1)𝑡𝑝 = (4 + 99) × 20 = 2060𝑛𝑠
to complete. Assuming that t = ktp = 4 x 20 =
80 ns,a non-pipeline system requires:
𝑛𝑘𝑡𝑝 = 100 × 80 = 8000𝑛𝑠
to complete the 100 tasks. The speedup ratio is equal to:
8000⁄
2060 = 3.88
Instruction Pipeline
The computer needs to process each instruction with the following sequence of steps:
1. Fetch the instruction from memory.
2. Decode the instruction.
3. Calculate the effective address.
4. Fetch the operands from memory.
5. Execute the instruction.
6. Store the result in the proper place.
Figure 48 shows how the instruction cycle in the CPU can be processed with a four-segment
pipeline. While an instruction is being executed in segment 4, the next instruction in sequence
is busy fetching an operand from memory in segment 3.
The four segments are represented in the flowchart:
1. FI is the segment that fetches an instruction.
2. DA is the segment that decodes the instruction and calculates the effective address.
3. FO is the segment that fetches the operand.
4. EX is the segment that executes the instruction.
A pipeline operation is said to have been stalled if one unit (stage) requires more time to
perform its function, thus forcing other stages to become idle. Consider, for example, the case
of an instruction fetch that incurs a cache miss. Assume also that a cache miss requires three
extra time units.
Instruction-Level Parallelism
Contrary to pipeline techniques, instruction-level parallelism (ILP) is based on the idea of
multiple issue processors (MIP). An MIP has multiple pipelined datapaths for instruction
execution. Each of these pipelines can issue and execute one instruction per cycle. Figure 49
shows the case of a processor having three pipes. For comparison purposes, we also show in
the same figure the sequential and the single pipeline case.
 Arithmetic Pipeline
Pipeline arithmetic units are usually found in very high speed computers. They are used to
implement floating-point operations, multiplication of fixed-point numbers, and similar
computations encountered in scientific problems.
an example of a pipeline unit for floating-point addition and subtraction. The inputs to the
floating-point adder pipeline are two normalized floating-point binary numbers.

A, B are two fractions that represent the mantissas and a, b are the exponents. The sub-
operations that are performed in the four segments are:
1. Compare the exponents.
2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.
Numerical example may clarify the sub-operations performed in each segment. For
simplicity,we use decimal numbers, although Fig.49 refers to binary numbers. Consider the
two normalized floating-point numbers:

The two exponents are subtracted in the first segment to obtain (3 − 2 = 1). The largerexponent
3 is chosen as the exponent of the result. The next segment shifts the mantissa of Yto the
right to obtain:

This aligns the two mantissas under the same exponent. The addition of the two mantissas in
segment 3 produces the sum:
Suppose that the time delays of the four segments are 𝑡1 = 60𝑛𝑠, 𝑡2 = 70𝑛𝑠, 𝑡3 = 100𝑛𝑠,
𝑡4 = 80𝑛𝑠, and the interface registers have a delay of 𝑡𝑟 = 10𝑛𝑠. The clock cycle is chosen to
be 𝑡𝑝 = 𝑡3 + 𝑡𝑟 = 110 . An equivalent non-pipeline floating point adder-subtractor will have
a delay time 𝑡𝑛 = 𝑡1 + 𝑡2 + 𝑡3 + 𝑡4 + 𝑡𝑟 = 320𝑛𝑠. In this case the pipelined adder has a
speedup of 320/110 = 2.9 over the non-pipelined adder.
Supercomputers
Supercomputers are very powerful, high-performance machines used mostly for scientific
computations. To speed up the operation, the components are packed tightly together to
minimize the distance that the electronic signals have to travel. Supercomputers also use
special techniques for removing the heat from circuits to prevent them from burning up
because of their close proximity.
A supercomputer is a computer system best known for its high computational speed, fast and
large memory systems, and the extensive use of parallel processing.
Delayed Branch
Consider now the operation of the following four instructions:

If the three-segment pipeline proceeds: (I: Instruction fetch, A:ALU operation, and E: Execute
instruction) without interruptions, there will be a data conflict in instruction 3 because the
operand in R2 is not yet available in the A segment. This can be seen from the timing of the
pipeline shown in Fig. 50(a). The E segment in clock cycle 4 is in a process of placing the
memory data into R2. The A segment in clock cycle 4 is using the data from R2, but the value
in R2 will not be the correct value since it has not yet been transferred from memory. It is up
to the compiler to make sure that the instruction following the load instruction uses the data
fetched from memory. It was shown in Fig. 50 that a branch instruction delays the pipeline
operation by NOP instruction until the instruction at the branch address is fetched.
 MULTIPROCESSORS
A multiple processor system consists of two or more processors that are connected in a manner that allows
them to share the simultaneous (parallel) execution of a given computational task. Parallel processing has been
advocated as a promising approach forbuilding high-performance computer systems. The organization and
performance of a multipleprocessor system are greatly influenced by the interconnection network used to connect
them. On the one hand, a single shared bus can be used as the interconnection network for multiple processors.
CLASSIFICATION OF COMPUTER ARCHITECTURES

The instruction stream is defined as the sequence of instructions performed by the computer. The data stream is
defined as the data traffic exchanged between the memory and the processing unit. This leads to four distinct
categories of computer architectures:
1. Single-instruction single-data streams (SISD)
2. Single-instruction multiple-data streams (SIMD)
3. Multiple-instruction single-data streams (MISD)
4. Multiple-instruction multiple-data streams (MIMD)
SIMD SCHEMES

Two main SIMD configurations have been used in real-life machines. These are shown in Figure 56.
 MIMD SCHEMES
MIMD machines use a collection of processors, each having its own memory, which can be used to collaborate on
executing a given task. In general, MIMD systems can be categorized based on their memory organization into
shared-memory and message-passing architectures.

INTERCONNECTION NETWORKS
The classification of interconnection networks is based on topology. Interconnection networksare classified as either
static or dynamic. In Figure 58, is provide such a taxonomy.
 Direct Course Assessment

Direct Attainment Calculation

Program- Year -
AY:2022-23 B.Tech II-II- CSD-A
SEM-Branch
Computer A LAKSHMAN
Subject Name: Organization Faculty Name:

MID 1 MID-2 Avg of Mids End Exam Total

S.no Roll Number
(30M) (30M) (30M) (70M) (100M)
1 217R1A6701 30 30 30
2 217R1A6702 30 30 30
3 217R1A6703 27 22 25
4 217R1A6704 25 26 26
5 217R1A6705 30 30 30
6 217R1A6706 27 29 28
7 217R1A6707 29 29 29
8 217R1A6708 29 27 28
9 217R1A6709 25 27 26
10 217R1A6710 23 28 26
11 217R1A6711 21 20 21
12 217R1A6712 29 30 30
13 217R1A6713 29 27 28
14 217R1A6714 12 21 17
15 217R1A6715 29 27 28
16 217R1A6716 30 30 30
17 217R1A6717 30 21 26
18 217R1A6718 13 21 17
19 217R1A6719 29 25 27
20 217R1A6720 20 23 22
21 217R1A6722 30 30 30
22 217R1A6723 12 17 15
23 217R1A6725 30 30 30
24 217R1A6726 30 29 30
25 217R1A6727 30 30 30
26 217R1A6728 28 29 29
27 217R1A6729 30 29 30
28 217R1A6730 23 22 23
29 217R1A6731 30 30 30
30 217R1A6732 25 22 24
31 217R1A6733 30 30 30
32 217R1A6734 29 23 26
33 217R1A6735 28 26 27
34 217R1A6736 29 27 28
35 217R1A6737 30 30 30
36 217R1A6739 28 23 26
37 217R1A6740 7 20 14
38 217R1A6741 22 26 24
39 217R1A6742 28 28 28
40 217R1A6743 30 28 29
41 217R1A6744 27 28 28
42 217R1A6746 30 30 30
43 217R1A6747 26 27 27
44 217R1A6748 30 30 30
45 217R1A6749 29 30 30
46 217R1A6750 28 29 29
47 217R1A6751 23 14 19
48 217R1A6752 19 25 22
49 217R1A6753 8 12 10
50 217R1A6754 27 30 29
51 217R1A6755 11 12 12
52 217R1A6756 30 29 30
53 217R1A6757 27 24 26
54 217R1A6758 27 26 27
55 217R1A6759 30 30 30
56 217R1A6760 30 30 30
57 217R1A6761 26 28 27
58 217R1A6762 19 12 16
59 217R1A6763 27 29 28
60 217R1A6764 19 13 16
61 227R5A6701 25 26 26
62 227R5A6702 28 30 29
63 227R5A6703 28 27 28
64 227R5A6704 29 29 29
65 227R5A6705 29 29 29
66 227R5A6706 30 30 30
67 227R5A6707 28 29 29
68 227R5A6708 29 26 28
Average Marks 25.96
Number of students attempted 68 68 68

Course Attainment Calculation

Number of
Students % Target Attainment Attainment Level
reached
target
Interna1 68 91.5549296 3
Attainment(b)
External Attainment(a) 68 100 3
Course Attainment (0.75*a+0.25*b) 3

Direct Attainment Calculation

Program- Year -
AY:2022-23 B. Tech. II-II SEM CSD-A
SEM-Branch
Computer
Subject Name: Organization Faculty Name: A Lakshman
ID TERM-2 QUESTION PAPER:

CMR TECHNICAL CAMPUS

UGC AUTONOMOUS
B. Tech IV Semester I-Mid Examination
Department of CSD & CSG

Subject: Computer Organization Date: 20-05-2023 AN

Time: 1 Hours Max. Marks: 25
Note
i. This Question paper contains Part- A and Part- B.
ii. All the Questions in Part A are to be answered compulsorily.
iii. All Questions from Part B are to be answered with internal choice among them.
****
PART-A 5 X 02 = 10 Marks
Q. Questions Marks
BL CO
No.
1a Define Digital Computer and Draw the Block-Diagram of 2M L1
CO1
Computer Organization.
1b Mention the Names of Computer Registers? 2M L1 CO1
1c Explain Number Systems and its types briefly? Example? 2M L2 CO2
1d Explain Micro-operations and types? 2M L1 CO2
1e Define Instruction Cycle its phases? 2M L1 CO3

PART- B
06 + 06 + 03 = 15 Marks
Q. Questions Marks
BL CO
No.
2a Explain Basic Register Transfer Operations? 3M L2
2b Explain 4-bit Bus & memory Transfer Using Multiplexer and 3M
L3
3state Bus buffer with diagram?
OR CO1
3a Explain Arithmetic Logic Shift Operations with Diagram? 3M L2
3b Explain Binary Complements and Decimal Complements With 3M
L2
Example?
4a Explain Basic Computer Registers and their functionality? 3M L3
4b Explain 16-Line Common BUS System how the registers are 3M
L4
connected.
OR CO2
5a Explain the Instruction Cycle and its phases briefly? 3M L3
5b Explain the Timing Signals with Control Unit connectivity 3M
L3
Diagram with an example?
6 Explain Memory Reference Instructions? 3M L2
OR CO3
7 Explain Arithmetic Micro-operations briefly? 3M L4
 CO-PO & PSO Mapping
CO CO1 CO2 CO3

PO
PSO
BL– Bloom’s Taxonomy Levels (L1-Remembering, L2-Understanding, L3–Applying,
L4 – Analyzing, L5 – Evaluating, L6 - Creating)

CMR TECHNICAL CAMPUS

UGC AUTONOMOUS
B. Tech IV Semester I-Mid Examination
Department of CSD & CSG
Subject: Computer Organization Date: 20-05-2023 AN
Time: 1 Hours Max. Marks: 25
Note
i. This Question paper contains Part- A and Part- B.
ii. All the Questions in Part A are to be answered compulsorily.
iii. All Questions from Part B are to be answered with internal choice among them.
****
PART-A 5 X 02 = 10 Marks
Q. Questions Marks
No. BL CO

1a Define Digital Computer? Draw the Picture of Block Diagram Of 2M L1

CO1
CPU?
1b List out the Names of Different Number Systems with Example? 2M L1 CO1
1c What is the use of Complements in Computer Organization? 2M L1 CO2
1d Define Instruction codes and its formats? 2M L1 CO2
1e Define Instruction Cycle its phases? 2M L1 CO3

PART- B 06 + 06 + 03 = 15 Marks
Q. Questions Marks
BL CO
No.
2a 3M
Comparethe following. L2
I. Arithmetic Addition II. Arithmetic Subtraction
2b Explain 4-bit Binary Arithmetic addition & Subtracted with 3M
L3
Diagram? CO1
OR
3a Explain Arithmetic Logic Shift Operations with Diagram? 3M L2
3b Explain Binary Complements and Decimal Complements With 3M
L3
Example?
4a Explain Basic Computer Registers and their functionality? 3M L4
4b Explain 16-Line Common BUS System how the registers are 3M
L3
connected. CO2
OR
5a Explain the Instruction Cycle and its phases briefly? 3M L3
 5b Explain the Timing Signals with Control Unit connectivity 3M
L4
Diagram with an example?
6 Explain Memory Reference Instructions? 3M L2
OR CO3
7 Briefly Explain Number System and its types? 3M L4

CO-PO & PSO Mapping

CO CO1 CO2 CO3

PO
PSO

BL–Bloom’s Taxonomy Levels (L1-Remembering, L2-Understanding, L3–Applying,

L4– Analyzing, L5–Evaluating, L6- Creating)

CMR TECHNICAL CAMPUS

UGC AUTONOMOUS
B. Tech IV Semester II-Mid Examination
Department of CSD & CSG
Subject: Computer Organization Date: 00-00-2023 FN
Time: 1 Hours Max. Marks: 25
Note
i. This Question paper contains Part- A and Part- B.
ii. All the Questions in Part A are to be answered compulsorily.
iii. All Questions from Part B are to be answered with internal choice among them.
****
PART-A 5 X 02 = 10 Marks
Q. Questions Marks
No. BL CO
1a Define Cache memory. 2M L2 CO4
1b What is Array Processing 2M L3 CO5
1c What is Vector Processing 2M L3 CO5
1d Write short note on CISC & RISC Characteristics 2M L4 CO5
1e Write short note on Characteristics of Multiprocessor. 2M L4 CO5

PART- B 03 + 06 + 06 = 15 Marks
Q. Questions Marks
BL CO
No.
2 Explain Cache Memory in Memory Organization. 3M L5 CO3
OR
3 What is the difference between Direct and Indirect address 3M
L3 CO3
modes?
4a Explain how addition and subtraction performed in singed 3M
L4 CO4
magnitude notation.
 4b Explain Booths multiplication algorithm with example. 3M L5
OR
5a What are Various Modes of Transfer explain. 3M L3
5b Explain Associative Memory in Memory Organization. 3M L5
6a Explain floating point representation of decimal numbers. 3M L5
6b Explain in detail various types of addressing modes with 3M
L5
examples. CO5
OR
7a Explain the parallel processing architecture and its uses 3M L5
7b Draw the block diagram of a typical DMA controller and explain. 3M L5

CO-PO & PSO Mapping

CO CO3 CO4 CO5

PO 1,2,3,4,5 1,2,3,4,5 1,2,3,4,5

PSO 1,2 1,2 1,2

BL–Bloom’s Taxonomy Levels (L1-Remembering, L2-Understanding, L3–Applying,

L4– Analyzing, L5–Evaluating, L6- Creating)

CMR TECHNICAL CAMPUS

UGC AUTONOMOUS
B. Tech IV Semester II-Mid Examination
Department of CSD & CSG

Subject: Computer Organization Date: 00-00-2023 FN

Time: 1 Hours Max. Marks: 25
Note
i. This Question paper contains Part- A and Part- B.
ii. All the Questions in Part A are to be answered compulsorily.
iii. All Questions from Part B are to be answered with internal choice among them.
****
PART-A 5 X 02 = 10 Marks
Q. Questions Marks
BL CO1
No.
1a What is Three address Instructions. 2M L3 CO3
1b Draw the RAM and ROM Chip Diagrams. 2M L2 CO3
1c What is Parallel Processing 2M L2 CO5
1d Write short note on CISC & RISC Characteristics 2M L3 CO5
1e Write short note on Characteristics of Multiprocessor. 2M L3 CO5

PART- B
03 + 06 + 06 = 15
Marks
 Q. Questions Marks
BL CO1
No.
2 What is Cache memory mapping techniques with example 3M L3 CO3
OR
3 Explain Associative Memory in Memory Organization 3M L5 CO3
4a Explain how addition and subtraction performed in singed 3M
L5
magnitude notation
4b Explain Booths multiplication algorithm with example 3M L5
CO4
OR
5a Draw the block diagram of a typical DMA controller and explain 3M L2
5b Explain floating point representation of decimal numbers 3M L5
6a What is the parallel processing architecture and its uses 3M L3
6b Explain Vector Processing 3M L5 CO5
OR
7a Explain Direct Memory Access? 3M L5
7b Explain in detail various types of addressing modes with 3M L5
examples.

CO-PO & PSO Mapping

CO1 CO3 CO4 CO5

PO 1,2,3,4,5 1,2,3,4,5 1,2,3,4,5

PSO 1,2 1,2 1,2
BL– Bloom’s Taxonomy Levels (L1-Remembering, L2-Understanding, L3–Applying,
L4 – Analyzing, L5 – Evaluating, L6 - Creating)