Numerical on Paging

*Note: 210 = 1K, 220 = 1M, 230 = 1G, 240 = 1T, 250 = 1P

Type 01 Numerical: Address to Space/Memory Translation

*Note: The total size of memory (to find) depends upon two values:
1. Number of locations the memory has (2n); where n is no of address bits
2. Size of Memory Location (if Size of Location is not given in question,
then by default we take it as 1Byte (1B) as our system is Byte Addressable.)*

Now, Size of memory = No. of Memory Location (2n) x Size of

Memory Location
Using the above information we can solve the numerical on address to space
translation
Q1. An address of 10 bits can support memory of how much size?
Sol:
Given Data:
No. of address bits (n) = 10bits

Therefore, no. of memory locations = 2n = 210

Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
= 210 x 1B = 1KB (ans)
Q2. An address of 14 bits can support memory of how much size?
Sol:
Given Data:
No. of address bits (n) = 14bits

Therefore, no. of memory locations = 2n = 214

Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
= 214 x 1B = 24 x 210 x 1B = 16 x 1K x 1B = 16KB (ans)
Q3. An address of 22 bits can support memory of how much size, when the size
of memory location is 2B?
Sol:
Given Data:
No. of address bits (n) = 22bits

Therefore, no. of memory locations = 2n = 222

Size of memory location = 2B
Now, Size of memory = no. of memory locations x size of memory location
= 222 x 2B = 22 x 220 x 2B = 4 x 1M x 2B = 8MB (ans)

Q4. An address of 34 bits can support memory of how much size?

Sol:
Given Data:
No. of address bits (n) = 34bits

Therefore, no. of memory locations = 2n = 234

Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
= 234 x 1B = 24 x 230 x 1B = 16 x 1G x 1B = 16GB (ans)
Type 02 Numerical: Space/Memory to Address Translation
*Note: As we have seen above, the total size of memory depends upon two
values:
1. Number of locations the memory has (2n); where n (to find) is no of
address bits
2. Size of Memory Location (if Size of Location is not given in question,
then by default we take it as 1Byte (1B) as our system is Byte Addressable.)*

w.k.t, Size of memory = No. of Memory Location (2 n) x Size of

Memory Location
now, No. of Memory Location (2 n)= Size of memory/ Size of
Memory Location
and n (to find) =upper bound of Log2n
Using the above information we can solve the numerical on address to space
translation
Q1. A memory of 64KB can support an address of how many bits?
Sol:
Given Data:
Size if memory = 64KB
Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
Therefore,
no. of memory locations (2n) = size of memory/size of memory location
= 64KB/1B = 64K = 26 x 210 = 216
Therefore n = 16bits (ans)
Q2. A memory of 32KB can support an address of how many bits?
Sol:
Given Data:
Size if memory = 32KB
Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
Therefore,
no. of memory locations (2n) = size of memory/size of memory location
= 32KB/1B = 32K = 25 x 210 = 215
Therefore n = 15bits (ans)
Q3. A memory of 256 MB can support an address of how many bits?
Sol:
Given Data:
Size if memory = 256MB
Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
Therefore,
no. of memory locations (2n) = size of memory/size of memory location
= 256MB/1B = 256M = 28 x 220 = 228
Therefore n = 28bits (ans)
Q4. A memory of 16 GB can support an address of how many bits, when the size
of location is 4B?
Sol:
Given Data:
Size if memory = 16 GB
Size of memory location = 4B
Now, Size of memory = no. of memory locations x size of memory location
Therefore,
no. of memory locations (2n) = size of memory/size of memory location
 = 16 GB/4B = 4G = 22 x 230 = 232
Therefore n = 32bits (ans)
Types 03 Numericals: To find number of Pages (Sec Memory) and
number of Frames (Main Memory) from Logical Address, Physical
Address and Page Size.
Steps to solve the numerical
1. Find the size of Secondary Memory using given Logical Address (LA)
bits (numerical type 01)
2. Find the size of Main Memory using given Physical Address (PA) bits
(numerical type 01)
3. Using given Page Size, find the bits of instruction offset (d) of Logical
Address and Physical Address. (d is same in both address)
4. Using d, find the bits of p in Logical Address and f in Physical Address
5. Using the bits of p and d, find the number of pages and frames.
Q1. When LA= 24 bits, PA = 16bits and Page Size= 1KB, find the total
number of pages and frames in the system.
Sol.
Step 01: To find the size of Secondary Memory using given Logical
Address (LA) bits.
No. of LA bits (n) = 24bits

Therefore, no. of memory locations = 2n = 224

Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of secondary memory = no. of memory locations x size of memory
location
= 224 x 1B = 24 x 220 x 1B = 16 x 1M x 1B = 16MB
Step 02: To find the size of Main Memory using given Physical Address
(PA) bits.
No. of LA bits (n) = 16bits

Therefore, no. of memory locations = 2n = 216

Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of main memory = no. of memory locations x size of memory
location
 = 216 x 1B = 26 x 210 x 1B = 64 x 1K x 1B = 64KB
Step 03: Using given Page Size, find the bits of instruction offset (d) of
Logical Address and Physical Address. (d is same in both address)
Page Size (size of memory) = 1KB
Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
Therefore,
no. of memory locations (2n) = size of memory/size of memory location
= 1KB/1B = 1K = 210
Therefore n = 10bits
i.e. d = n = 10bits
now the value of d in LA and also in PA is same i.e. 10bits
Step 04: Using d, find the bits of p in Logical Address and f in Physical
Address
w.k.t, LA= p+d
Therefore, p= LA-d = 24-10 bits = 14 bits
Also, w.k.t, PA= f+d
Therefore, f= PA-d = 16-10 bits = 6 bits
Step 05: Using the bits of p and d, find the number of pages and frames.
Now, p=14 bits
Therefore, no of pages (no. of locations) = 2p = 214 = 24 x 210 = 16K no of pages
approx. (ans)
Now, f=6 bits
Therefore, no of frames (no. of locations) = 2 f = 26 = 64 no of frames approx.
(ans)
Q2. When LA= 33 bits, PA = 24bits and Page Size= 2KB, find the total number
of pages and frames in the system.
Sol.
Step 01: To find the size of Secondary Memory using given Logical
Address (LA) bits.
No. of LA bits (n) = 33bits

Therefore, no. of memory locations = 2n = 233

Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of secondary memory = no. of memory locations x size of memory
location
= 233 x 1B = 23 x 230 x 1B = 8 x 1G x 1B = 8GB
Step 02: To find the size of Main Memory using given Physical Address
(PA) bits.
No. of LA bits (n) = 24bits

Therefore, no. of memory locations = 2n = 224

Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of main memory = no. of memory locations x size of memory location
= 224 x 1B = 24 x 220 x 1B = 16 x 1M x 1B = 16KB
Step 03: Using given Page Size, find the bits of instruction offset (d) of
Logical Address and Physical Address. (d is same in both address)
Page Size (size of memory) = 2KB
Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
Therefore,
no. of memory locations (2n) = size of memory/size of memory location
= 2KB/1B = 2K = 21 x 210 = 211
Therefore n = 11bits
i.e. d = n = 11bits
now the value of d in LA and also in PA is same i.e. 11bits
Step 04: Using d, find the bits of p in Logical Address and f in Physical
Address
w.k.t, LA= p+d
Therefore, p= LA-d = 33-11 bits = 22 bits
Also, w.k.t, PA= f+d
Therefore, f= PA-d = 24-11 bits = 13 bits
Step 05: Using the bits of p and d, find the number of pages and frames.
Now, p=22 bits
Therefore, no of pages (no. of locations) = 2p = 222 = 22 x 220 = 4M no of pages
approx. (ans)
Now, f=13 bits
Therefore, no of frames (no. of locations) = 2 f = 213 = 23 x 210 = 8K no of frames
approx. (ans)
Types 04 Numerical: To find the total space/memory wasted in
maintaining the page table for all processes in the system or a
single process in the system (*NOT IN SYLLABUS* only for
GATE)
Refer https://www.youtube.com/watch?v=NMtHuK2i2dc
Types 05 Numerical: To find the size of process using the size of
Page Table system (*NOT IN SYLLABUS* only for GATE)
Refer https://www.youtube.com/watch?v=gRzwXIRG1Dc
 Paging Diagram

Translation Lookaside Buffer (TLB) in Paging

In Operating System (Memory Management Technique: Paging), for each process page table
will be created, which will contain Page Table Entry (PTE). This PTE will contain information
like frame number (The address of main memory where we want to refer), and some other
useful bits (e.g., valid/invalid bit, dirty bit, protection bit etc.). This page table entry (PTE) will
tell where in the main memory the actual page is residing.
Now the question is where to place the page table, such that overall access time (or reference
time) will be less.
The problem initially was to fast access the main memory content based on address generated
by CPU (i.e. logical/virtual address). Initially, some people thought of using registers to store
page table, as they are high-speed memory so access time will be less.
The idea used here is, place the page table entries in registers, for each request generated from
CPU (virtual address), it will be matched to the appropriate page number of the page table,
which will now tell where in the main memory that corresponding page resides. Everything
seems right here, but the problem is register size is small (in practical, it can accommodate
maximum of 0.5k to 1k page table entries) and process size may be big hence the required page
table will also be big (let’s say this page table contains 1M entries), so registers may not hold
all the PTE’s of Page table. So this is not a practical approach.
To overcome this size issue, the entire page table was kept in main memory. But the problem
here is two main memory references are required:
1. To find the frame number
2. To go to the address specified by frame number
To overcome this problem a high-speed cache is set up for page table entries called a
Translation Lookaside Buffer (TLB). Translation Lookaside Buffer (TLB) is nothing but a
special cache used to keep track of recently used transactions. TLB contains page table entries
that have been most recently used. Given a virtual address, the processor examines the TLB if
a page table entry is present (TLB hit), the frame number is retrieved and the real address is
formed. If a page table entry is not found in the TLB (TLB miss), the page number is used to
index the process page table. TLB first checks if the page is already in main memory, if not in
main memory a page fault is issued then the TLB is updated to include the new page entry.

Steps in TLB hit:

1. CPU generates virtual address.
2. It is checked in TLB (present).
3. Corresponding frame number is retrieved, which now tells where in the main memory
page lies.

Steps in TLB miss:

1. CPU generates virtual address.
2. It is checked in TLB (not present).
3. Now the page number is matched to page table residing in main memory (assuming
page table contains all PTE).
 4. Corresponding frame number is retrieved, which now tells where in the main memory
page lies.
5. The TLB is updated with new PTE (if space is not there, one of the replacement
technique comes into picture i.e. either FIFO, LRU or MFU etc.).

Effective memory access time (EMAT): TLB is used to reduce effective memory access
time as it is a high speed associative cache.
EMAT = h*(c+m) + (1-h)*(c+2m) where h*(c+m) refers t0 TLB HIT and (1-h)*(c+2m)
refers to TLB MISS
where, h = hit ratio of TLB
m = Memory access time
c = TLB access time

Numerical on TLB

Q1. If memory access time is 400µs and TLB access time is 50µs and TLB hit%
is 90%. Find the average instruction access time and effective memory access
time.
Sol.
Given:
m= 400µs, c= 50µs, h= 0.9
If TLB is not present,
Then Total memory access time = 2 x m = 2 x 400µs = 800 µs (*solve only if
asked*)
If TLB is present,
Then Effective memory access time (EMAT) = h*(c+m) + (1-h)*(c+2m)

= 0.9*(50 µs+400 µs) + 0.1*(50 µs+2x400 µs)

= 405 µs + 85 µs = 490 µs (ans)

 Difference between Segmentation and Paging
Sr. Key Paging Segmentation
No.

Memory Size In Paging, a process address In Segmentation, a process

space is broken into fixed address space is broken in
1
sized blocks called pages. varying sized blocks called
sections.

Accountability Operating System divides the Compiler is responsible to

memory into pages. calculate the segment size, the
2
virtual address and actual
address.

Size Page size is determined by Section size is determined by the

3
available memory. user.

Speed Paging technique is faster in Segmentation is slower than

4
terms of memory access. paging.

Fragmentation Paging can cause internal Segmentation can cause external

5 fragmentation as some pages fragmentation as some memory
may go underutilized. block may not be used at all.

Logical During paging, a logical During segmentation, a logical

6 Address address is divided into page address is divided into section
number and page offset. number and section offset.

Table During paging, a logical During segmentation, a logical

7 address is divided into page address is divided into section
number and page offset. number and section offset.

Data Storage Page table stores the page Segmentation table stores the
8
data. segmentation data.