Ummidi Chandrika

Day 51: TB Hello World

Day 52: TB LOgic Data Type

Day 53: TB Unpacked Struct Data Type

Day 54:TB Packed Struct Data Type

Day 55: TB Arrays

Day 56: TB Functions

Day 57: TB Tasks

Day 58: TB Interfaces

Day 59: TB Object Assignment & Shallow Copy Methods

Day 60: TB Deep Copy Method

Day 61: TB Inheritance

Day 62: TB Polymorphism

Day 63: TB to Verify Static Function and FUnction Static Methods

Day 64: TB to verify Parameterized Class

Day 65: TB to verify Randomization

Day 66: TB Interface to Verify Clocking Blocks

Day 67: TB Fork-Join None

Day 68: TB Fork- Join

Day 69: TB Fork - Join Any

Day 70: TB Events

Day 71 : TB Mailbox Example-1

Day 72: TB for Sending Transaction Data with Mailbox

Day 73: TB Parameterized Mailbox

Day 74: TB Semaphore

Day 75- TB Wait Fork

Ummidi Chandrika

Day 76- TB Automatic Variables

Day 77: TB to Verify D-Flipflop

Day 78 :TB to Verify Half Adder

Day 79: TB to Verify Full adder

Day 80: TB to Verify 4:1 Multiplexer

Day 81: TB to Verify Full Subtractor

day 82: TB to Verify 3:8 Decoder

Day 83: TB to Verify Priority Encoder

Day 84: TB to Verify 1:4 Demultiplexer

Day 85 : TB to Verify FIFO

Day 86: TB to Verify Binary to Gray Converter

Day 87: TB to Verify Gray to Binary Converter

Day 88: TB to Verify Tristate Buffer

Day 89: TB to Verify T-Flipflop

Day 90: TB to Verify ALU

Day 91- TB to Verify Self Reloading Counter

Day 92" TB to Verify Priority Arbiter

Day 93 : Constraint to generate the below pattern in dynamic array ? 0 1 0 2 0 3 0 4 0 5 0

Day 94 : Constraint for 2D 3D for dynamic array to print consecutive elements

Day 95 : Identify how many number of zeros count in an array / number of ones count in an array

Day 96: TB Constraint to generate a pattern 0102030405

Day 97: TB Constraint to generate unique numbers between 99 to 100

Day 98: TB Constraint to Generate Pattern 0, 2, 1, 3, 4, 6, 5, 7, 8
Day 99: TB to Verify CoverGroup in Functional Coverage

Day 100: Functional Coverage

Ummidi Chandrika

100DaysofRTL
Part-2(SystemVerilog)
Day 51: Testbench to print Hello World in System Verilog
EdaPlayground Link; https://www.edaplayground.com/x/KMMH

Day 52: Testbench to verify Logic Data type

logic is the improved version of reg form Verilog to SystemVerilog, so it Can be driven by
continuous assignments, gates, and modules in addition to being a variable.
EdaPlayground Link: https://www.edaplayground.com/x/ hpJ
Ummidi Chandrika

Day 53: Testbench to verify unpacked struct datatype

A Normal array contain group of elements/variables of same datatype. But in a
structure can contain group of variables of different datatype. A structure is unpacked
by default and de ined using 'struct' keyword. To create multiple structure variables we
use user de ined data type of the structure by "typedef".

Day 54: Testbench to verify Packed Struct

When used in RTL code, a packed SystemVerilog struct is the most useful. A packed
struct is treated as a single vector, and each data type in the structure is represented as a
bit ield. The entire structure is then packed together in memory without gaps. Only
packed data types and integer data types are allowed in a packed struct. Because it is
de ined as a vector, the entire structure can also be used as a whole with arithmetic and
logical operators.

SystemVerilog struct is often de ined with the typedef keyword to give the structure
type a name so it can be more easily reused across multiple iles.
Ummidi Chandrika

Day 55: Testbench to Verify array Types

Associative array Stores entries in a sparse matrix.Associative arrays allocate the
storage only when it is used, unless like in the dynamic array we need to allocate
memory before using it.In associative array index expression is not restricted to integral
expressions, but can be of any type

A dynamic array is one dimension of an unpacked array whose size can be set or
changed at run-time. Dynamic array is Declared using an empty word subscript [ ].

A queue is a variable-size, ordered collection of homogeneous elements like a dynamic

array, queues can grow and shrink
queue supports adding and removing elements anywhere
Queues are declared using the same syntax as unpacked arrays, but specifying $ as the
array size. In queue 0 represents the irst, and $ representing the last entries.
Ummidi Chandrika
Ummidi Chandrika

Day 56: Testbench to verify Functions

EdaPlayground Link: https://www.edaplayground.com/x/KCDd
SystemVerilog provides below means for passing arguments to functions,
-->argument pass by value
-->argument pass by reference
-->argument pass by name
-->argument pass by position
also, functions and tasks can have default argument values.
Ummidi Chandrika

Day 57: Testbench to verify Tasks

Eda Playground Link: https://www.edaplayground.com/x/8wRJ
Tasks and Functions provide a means of splitting code into small parts. A Task can
contain a declaration of parameters, input arguments, output arguments, in-out
arguments, registers, events, and zero or more behavioral statements.
SystemVerilog task can be of 2 types:
1.static
2.automatic
-->Static tasks
Static tasks share the same storage space for all task calls.
-->Automatic tasks
Automatic tasks allocate unique, stacked storage for each task call.
Ummidi Chandrika

Day 58: TB Interface to verify Exor Gate

EdaPlayground Link: https://www.edaplayground.com/x/WXZj
The interface construct is used to connect the design and testbench.
An interface is a named bundle of wires, the interfaces aim is to encapsulate
communication.Also speci ies the, directional information, i.e modports timing
information, i.e clocking blocks
An interface can have parameters, constants, variables, functions, and tasks.
Ummidi Chandrika

Day 59: TB to verify Object Assignment copy and Shallow Copy Methods
EdaPlayground Link: https://www.edaplayground.com/x/7qUQ
In Object Assignment ,same memory location will be allocated and which can be
accessed by two different handles. If any handle would like to change class properties, it
will re lect the same changes when it is accessed by another handle.
The shallow copy is used to copy
1.Class properties like integers, strings, instance handle
2.Nested objects are not copied, only instance handles are copied which means any
changes are done in ‘nested copied object’ will also re lect in the ‘nested original object’
or vice-versa.
The new() method is used for copying.
Ummidi Chandrika

Day 60: TB to verify Deep Copy Method

EdaPlayground Link: https://www.edaplayground.com/x/Fj5c
SystemVerilog deep copy copies all the class members and its nested class members.
unlike in shallow copy, only nested class handles will be copied. In shallow copy, Objects
will not be copied, only their handles will be copied. to perform a full or deep copy, the
custom method needs to be added.
In the custom method, a new object is created, all the class properties will be copied to a
new handle and the new handle will be returned.
Ummidi Chandrika
Ummidi Chandrika

Day 61: TB Inheritance

EdaPlayground Link: https://www.edaplayground.com/x/Bwj3
Inheritance is an OOP concept that allows the user to create classes that are built upon
existing classes. The new class will be with new properties and methods along with
having access to all the properties and methods of the original class. Inheritance is about
inheriting base class members to the extended class.
Ummidi Chandrika

Day 62: TB to verify Polymorphism

Eda Playground Link: https://www.edaplayground.com/x/CkqF
Polymorphism means many forms. Polymorphism in SystemVerilog provides an ability
to an object to take on many forms. Method handle of super-class can be made to refer
to the subclass method, this allows polymorphism or different forms of the same
method.
Ummidi Chandrika

Day 63: TB to verify Static function and Function static methods

Eda Playground Link: https://www.edaplayground.com/x/PpHC
‘Static function‘ is a function whose scope is static. That mean, a static function remains
same for ALL the objects of a class. In system memory, the function is stored at a single
place and all the objects access that function memory.A static function can only access
static variables of a class.
‘Function static‘ is another type of function that makes the scope of its internal variables
as static. This type of function DO NOT initialize its variables during each call. The scope
of internal variables of function becomes static. Rest of the class variables scope remains
the same (auto). All the automatic variables of class are initialized for every object, but
the function’s internal variables remains static.
Ummidi Chandrika

Day 64: TB to verify Parameterized Class

EdaPlayground Link: https://www.edaplayground.com/x/BzrE
Parameterized classes are same as the parameterized modules in the verilog.
parameters are like constants local to that particular class.
The parameter value can be used to de ine a set of attributes in class. default values can
be overridden by passing a new set of parameters during instantiation. this is called
parameter overriding.

Datatype can be also parameterized and can be overidden during instantiation

Ummidi Chandrika

Day 65: TB to verify Randomization

Eda Playground Link: https://www.edaplayground.com/x/JdvY
Randomization is the process of making something random; SystemVerilog
randomization is the process of generating random values to a variable. Verilog has a
$random method for generating the random integer values. This is good for
randomizing the variables alone, but it is hard to use in case of class object
randomization. for easy randomization of class properties, SystemVerilog provides rand
keyword and randomize() method.
Ummidi Chandrika

Day 66 : TB Interface to verify Clocking Blocks ( Adder circuit )

Eda Playground Link: https://www.edaplayground.com/x/Lm4W
A clocking block speci ies timing and synchronization for a group of signals. It speci ies
The clock event that provides a synchronization reference for DUT and testbench, the
set of signals that will be sampled and driven by the testbench and the he timing,
relative to the clock event, that the testbench uses to drive and sample those signals.
Clocking block can be declared in interface, module or program block. Clocking skew
speci ies the moment at which input and output clocking signals are to be sampled or
driven respectively.
default skews : " default input #1step output #0; "
Ummidi Chandrika
Ummidi Chandrika

Day 67 : TB to verify Threads [ join_none ]

Eda Playground Link: https://www.edaplayground.com/x/Jgh9
A thread or process is any piece of code that gets executed as a separate entity. In
verilog, each of the initial and always blocks are spawned off as separate threads that
start to run in parallel from zero time. A fork join block also creates different threads
that run in parallel. A fork and join_none will allow the main thread to resume execution
Ummidi Chandrika

of further statements that lie after the fork regardless of whether the forked threads
inish. If three threads are launched, the main thread will resume execution immediately
while all the three threads remain running in the background.

Day 68: TB Threads to verify Fork-Join

Eda Playground Link: https://www.edaplayground.com/x/GVus
Fork-Join will start all the processes inside it parallel and wait for the completion of all
the processes.
Ummidi Chandrika

Day 69: TB to verify Fork Join_Any

Eda Playground Link: https://www.edaplayground.com/x/vnBD
Fork-Join_any will be unblocked after the completion of any of the Processes.

Day 70: TB to verify Events

Eda Playground: https://www.edaplayground.com/x/Ac9G
Interprocess communication is a way to communicate between processes or testbench
components. SystemVerilog provides three mechanisms for communication.

1. Events

2. Semaphores

3. Mailbox

SystemVerilog event is used to synchronize between two or more processes or threads.

Ummidi Chandrika

An event is also a synchronization object that can be passed to a function or task or class
constructor. This allows event sharing without declaring it as a global event. One
process triggers an event while other processes will wait until the event is triggered.
The System Verilog events are triggered using -> operator. The processes can wait for an
event to be triggered either via @ operator or wait() construct.

Day 71: TB to Verify Mailbox Example-1

EDA Playground Link: https://www.edaplayground.com/x/AWbU
A mailbox is a communication mechanism that allows messages to be exchanged
between processes. The process which wants to talk to another process posts the
message to a mailbox, which stores the messages temporarily in a system de ined
memory object, to pass it to the desired process.
Ummidi Chandrika

Day-72 : Tb for sending Transaction data using Mailbox

Eda Playground Link: https://www.edaplayground.com/x/MpBg

Mailbox is a built-in class that provides the following methods:

—> Create a mailbox: new()
—> Place a message in a mailbox: put()
—> Try to place a message in a mailbox without blocking: try_put()
—>Retrieve a message from a mailbox: get() or peek()
—>Try to retrieve a message from a mailbox without blocking: try_get() or try_peek()
—> Retrieve the number of messages in the mailbox: num()
Ummidi Chandrika
Ummidi Chandrika

Day 73: TB to Verify Parameterised Mailbox

EDA Playground Link: https://www.edaplayground.com/x/6kNx
Parameterized mailbox is used to transfer a data of particular type.
The parameterized mailbox can be put or get data of particular data_type. The parameterized
mailbox is useful when data_type needs to be ixed. For differences in data_type, a compilation error
is expected.
The difference between Queue and Mailbox is A queue is just a data structure, and a mailbox is an
higher level concept that is built around a combination of queues and semaphores.
Ummidi Chandrika

Day 74: TB to Verify Semaphore

EDA Playground Link: https://www.edaplayground.com/x/UsBu

Semaphore is a SystemVerilog built-in class, used for access control to shared resources, and for
basic synchronization.
Semaphore is just like a bucket with a ixed number of keys. Processes that use a semaphore must
irst get a key from the bucket before they can continue to execute. Other proceses must wait until
keys are available in the bucket for them to use.
Ummidi Chandrika

Day 75- TB to Verify Wait Fork

The wait fork statement is used to ensure that all immediate child subprocesses (processes created
by the current process, excluding their descendants) have completed their execution. wait fork :-
causes the process to block until the completion of all processes started from fork blocks.
Ummidi Chandrika

Day 76- TB to Verify Automatic Variables

EDA Playground Link: https://www.edaplayground.com/x/LayF
For a variable Automatic lifetime is, it is stack storage of variable (for multiple entries to a task,
function or block, it will have stack storage) and its memory will be de-allocated once execution of
that method or block is over.

Day 77: TB Veri ication of D- Flip lop

Testbench or Verification Environment is used to check the functional correctness of
the Design Under Test (DUT) by generating and driving a predefined input sequence to
a design, capturing the design output and comparing with-respect-to expected output.

Verification environment is a group of class’s performing specific operation. i.e,

generating stimulus, driving, monitoring, etc. and those classes will be named based on
the operation
Ummidi Chandrika
Ummidi Chandrika
Ummidi Chandrika
Ummidi Chandrika
Ummidi Chandrika

Day 78 :TB to Verify Half Adder

EDA Playground Link: https://www.edaplayground.com/x/ie4d

Ummidi Chandrika
Ummidi Chandrika

Day 79: TB to Verify Full adder

EDA Playground Link: https://www.edaplayground.com/x/r_wr

The testbench environment in systemverilog is reusable. So I have used the same

testbench which is used in full adder. The RTL Code only changes from here and
testbench is same for every code.

Day 80: TB to Verify 4:1 Multiplexer

EDA Playground Liink: https://www.edaplayground.com/x/wCSh

Ummidi Chandrika

Day 81: TB to Verify Full Subtractor

EDA Playground Link: https://www.edaplayground.com/x/k_Lu

Day 82: TB to Verify 3:8 Decoder

EDA Playground Link: https://www.edaplayground.com/x/YuXi

Ummidi Chandrika

Day 83: TB to Verify Priority Encoder

EDA Playground Link: https://www.edaplayground.com/x/Q4iB

Day 84: TB to Verify 1:4 Demultiplexer

EDA Plaground Link: https://www.edaplayground.com/x/8dQ8

Day 85 : TB to Verify FIFO

Ummidi Chandrika

EDA Plaground Link: https://www.edaplayground.com/x/SJB6

Day 86: TB to Verify Binary to Gray Converter

EDA Plaground Link: https://www.edaplayground.com/x/UtKp

Day 87: TB to Verify

Gray to Binary
Converter

EDA Plaground Link: https://www.edaplayground.com/x/hr25

Ummidi Chandrika

Day 88: TB to Verify Tristate Buffer

EDA Plaground Link: https://www.edaplayground.com/x/LC6j

Day 89: TB to Verify T-Flipflop

EDA Plaground Link:https://www.edaplayground.com/x/dXjN

Day 90: TB to Verify ALU

EDA Plaground Link: https://www.edaplayground.com/x/fD9y

Ummidi Chandrika

Day 91- TB to Verify Self Reloading Counter

EDA Playground Link: https://www.edaplayground.com/x/e34Q

Ummidi Chandrika

Day 92: TB to Verify Priority Arbiter

EDA Playground Link: https://www.edaplayground.com/x/U_qk

Ummidi Chandrika

Day 93 : Constraint to generate the below pattern in dynamic array

0 1 0 2 0 3 0 4 0 5 0 https://www.edaplayground.com/x/Av5M

Day 94 : Constraint for 2D 3D for dynamic array to print consecutive elements

EDA Playground Link: https://www.edaplayground.com/x/gQjb

Day 95 : Identify how many number of zeros count in an array / number of ones count in
an array
EDA Playground Link: https://www.edaplayground.com/x/KL4m
Ummidi Chandrika

Day 96: TB Constraint to generate a pattern 0102030405

EDA Playground Link: https://www.edaplayground.com/x/KM2L

Day 97: TB Constraint to generate unique numbers between 99 to 100

Ummidi Chandrika

EDA Playground Link: https://www.edaplayground.com/x/KM3D

Day 98: TB Constraint to Generate Pattern 0, 2, 1, 3, 4, 6, 5, 7, 8

Eda Playground Link: https://www.edaplayground.com/x/fAiN
Ummidi Chandrika

Day 99: TB to Verify CoverGroup in Functional Coverage

EDA Playground Link: https://www.edaplayground.com/x/k9CG

Day 100: Functional Coverage

EDA Playground Link: https://www.edaplayground.com/x/QSij
Ummidi Chandrika
Ummidi Chandrika