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Design Test6

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171 views5 pages

Design Test6

Uploaded by

gowthamasenthur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Design_test

www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

Table of Contents

Part- 1: Digital ....................................................................................................................................... 3


Part- 2: Verilog...................................................................................................................................... 4

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VLSI Training Services
Setting standards in VLSI Design

Part- 1: Digital(25 Maks)


1. Design 3 input NOR gate using only one 2:4 decoder (3M)
2. Design the circuit for the digital block as shown in the figure. Assume t < t0 , Q1=Q2=0

Note: Explaination with necessary waveform is mandatory. (7M)

3. The 3 DFF is given in the circuit. Initially Y2Y1Y0 = 111. what is the sequence for Y0Y1Y2
at 237th clock cycle? (7M)

4. If C is one then expression of Y is (2M)

5. If output Y = (A’+B’)(C+D) then G1 & G2 gates must be (6M)

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Setting standards in VLSI Design

Part- 2: Verilog(25 marks)

1. Draw the waveform for the following snippet and calculate the time-period of the signal
clk. (5M)

2. Write RTL code such that the memory size of the below code is changed from 16x32 to
32x64 without editing the source code. Implement parameter over-riding. (5M)

3. Draw the stratified event queue for the following snippet: (5M)

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4. Design a magnitude comparator circuit for 2-bit binary numbers A=A1A0 and
B=B1B0. The outputs are F, G, and H, where F is 1 if A>B, G is 1 if A=B, and H is 1
if A<B.

[A] Implement your comparator design by using 2-to-4-line active high output
decoders and minimum number of gates. (Do not draw the internal circuit for the
decoders.) (2M)

[B] Write the RTL code for the design (4 M)


[C] Write the TB and verify the FSM (4 M)

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