Scribd
Upload
69 views4 pages

Design Test3

Uploaded by

gowthamasenthur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
69 views4 pages

Design Test3

Uploaded by

gowthamasenthur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Design_test

www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

Table of Contents

Part- 1: Digital ....................................................................................................................................... 3


Part- 2: Verilog...................................................................................................................................... 4

www.maven-silicon.com [email protected] Page 2


VLSI Training Services
Setting standards in VLSI Design

Part- 1: Digital(25 Maks)


1. Design 2 bit comparator using two 2:4 decoders and minimum logic gates. (8M)
2. Design 8 i/p NOR gate using only 3 i/p NOR gates (6M)
3. How many minimum number of flipflops are required to design a counter which counts
75, 76, 77, 78, 75, 76, 77, 78, 75…and so on? (2M)
4. Design a sequential circuit to produce output frequencies as per the below specification (9M)

Control i/p
C1 C0 Output
0 0 y1 (1MHz)
0 1 y2 (2MHz)
1 0 y3(500KHz)
1 1 y4(4MHz)

www.maven-silicon.com [email protected] Page 3


VLSI Training Services
Setting standards in VLSI Design

Part- 2: Verilog(25 marks)

1. Draw the waveform for the following snippet:


(5 M)

2. Write synthesizable RTL code for a n- bit left shift SISO register such that shifting
happens only for first 2 clock cycles within every four clock cycles. (Reset is active
high, synchronous reset). For the rest 2 clock cycles shifter holds the last shifted value.
(5 M)
3. Draw the stratified event queue for the following snippet: (5 M)

4. Draw the block diagram of a dual port synchronous Static RAM of size (64x16).
Clock is active at posedge , reset is active high synchronous reset. Address pointers
are input ports, “re” and “we” are two active high control inputs. The memory supports
simultaneous read and write operation. Implement parameter over-riding such that the
new RAM has a size (16x64).

[A] Draw the digital schematic (2 M)


[B] Write the RTL code for the design (4 M)
[C] Write the TB and verify the write operation only. (4 M)

www.maven-silicon.com [email protected] Page 4

You might also like