SEMICONDUCTOR TECHNICAL DATA

 
   
 L SUFFIX
CERAMIC
The MC14539B data selector/multiplexer is constructed with MOS CASE 620
P–channel and N–channel enhancement mode devices in a single
monolithic structure. The circuit consists of two sections of four inputs each.
One input from each section is selected by the address inputs A and B. A P SUFFIX
“high” on the Strobe input will cause the output to remain “low”. PLASTIC
This device finds primary application in signal multiplexing functions. It CASE 648
permits multiplexing from N–lines to I–line, and can also perform parallel–to–
serial conversion. The Strobe input allows cascading of n–lines to n–lines.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
SOIC
• Capable of Driving Two Low–Power TTL Loads or One Low–Power CASE 751B
Schottky TTL Load Over the Rated Temperature Range
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic
MC14XXXBD SOIC
VDD DC Supply Voltage – 0.5 to + 18.0 V
TA = – 55° to 125°C for all packages.
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
BLOCK DIAGRAM
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C 14 A
2 B Z 7
TL Lead Temperature (8–Second Soldering) 260 _C
1 ST
* Maximum Ratings are those values beyond which damage to the device may occur. 6 X0
†Temperature Derating:
5 X1
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 4 X2
3 X3
TRUTH TABLE
Address A
Inputs Data Inputs B W 9
X3 X2 X1 X0 Outputs 15 ST′
B A Y3 Y2 Y1 Y0 ST, ST′ Z, W 10 Y0
11 Y1
X X X X X X 1 0
12 Y2
0 0 X X X 0 0 0
13 Y3
0 0 X X X 1 0 1
0 1 X X 0 X 0 0 VDD = PIN 16
0 1 X X 1 X 0 1 VSS = PIN 8
1 0 X 0 X X 0 0
1 0 X 1 X X 0 1
1 1 0 X X X 0 0
1 1 1 X X X 0 1
X = Don’t Care

REV 3
1/94

 Motorola, Inc. 1995

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (0.85 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.70 µA/kHz) f + IDD
Per Package) 15 IT = (2.60 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14539B MOTOROLA CMOS LOGIC DATA

2
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
X, Y Input to Output tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 125 ns 5.0 — 210 420
tPLH, tPHL = (0.66 ns/pF) CL + 57 ns 10 — 90 180
tPLH, tPHL = (0.55 ns/pF) CL + 45 ns 15 — 70 140
A Input to Output tPLH ns
tPLH = (1.7 ns/pF) CL + 140 ns 5.0 — 225 450
tPLH = (0.66 ns/pF) CL + 77 ns 10 — 110 220
tPLH = (0.5 ns/pF) CL + 60 ns 15 — 85 170
tPHL = (1.7 ns/pF) CL + 160 ns tPHL 5.0 — 245 490 ns
tPHL = (0.66 ns/pF) CL + 82 ns 10 — 115 230
tPHL = (0.5 ns/pF) CL + 65 ns 15 — 90 180
Strobe Input to Output tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 60 ns tPHL 5.0 — 145 290
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 — 75 150
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns 15 — 60 120
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD

20 ns 20 ns
A
B
PULSE ST Z
GENERATOR X0 INPUT
X1 CL
X2
X3
OUTPUT
ST′
(TEST 1) tTLH tTHL
Y0 tPLH tPHL
Y1 W OUTPUT
Y2 (TESTS 2 AND 3)
Y3
tTHL tTLH
VSS tPHL tPLH

INPUT CONNECTIONS FOR tTLH, tTHL, tPHL, tPLH

Test Strobe A X0
1 Gnd Gnd P.G.
2 P.G. Gnd VDD
3 Gnd P.G. VDD

Figure 1. AC Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14539B

3
 VDD

0.01 µF
500 µF ID CERAMIC

A
B
ST Z 20 ns 20 ns
PULSE X0 VDD
GENERATOR 90%
X1 50%
X2 Vin 10% VSS
X3 CL
ST′ 50% DUTY CYCLE
Y0
Y1 W
Y2
Y3 CL

VSS

Figure 2. Power Dissipation Test Circuit and Waveform

LOGIC DIAGRAM
2
B
14
A

6 ST
X0 1 PIN ASSIGNMENT
ST 1 16 VDD
5
X1 7 B 2 15 ST′
Z
X3 3 14 A
4
X2 X2 4 13 Y3
X1 5 12 Y2
3
X3 X0 6 11 Y1
Z 7 10 Y0

10 VSS 8 9 W
Y0

11
Y1
9
W
12
Y2

15
13 ST′
Y3

MC14539B MOTOROLA CMOS LOGIC DATA

4
 OUTLINE DIMENSIONS

L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V

–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
16 9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
–B– FORMED PARALLEL.
1 8 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
–T– C ––– 0.200 ––– 5.08
N K D 0.015 0.020 0.39 0.50
SEATING
PLANE E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
E M H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
F G J 16 PL
L 0.300 BSC 7.62 BSC
D 16 PL 0.25 (0.010) M T B S M 0_ 15 _ 0_ 15 _
N 0.020 0.040 0.51 1.01
0.25 (0.010) M T A S

P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

MOTOROLA CMOS LOGIC DATA MC14539B

5
 OUTLINE DIMENSIONS

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J

–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315

MFAX: [email protected] – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

*MC14539B/D*
◊ MC14539B/D