Faculty of Engineering, O.U.

AICTE Model Curriculum with effect from Academic Year 2019-20

Course Code Course Title Core/Elective

ES216EC Digital Electronics Core
Contact Hours per Week
Prerequisite CIE SEE Credits
L T D P

- 3 - - - 30 70 3
Course Objectives
 To learn the principles of digital hardware and support given by it to the software.
 To explain the operation and design of combinational and arithmetic logic circuits.
 To design hardware for real world problems.
Course Outcomes
At the end of this course the students will be able to
1. Understand the deign process of digital hardware, use Boolean algebra to minimize the logical
expressions and optimize the implementation of logical functions.
2. Understand the number representation and design combinational circuits like adders, MUX etc.
3. Design Combinational circuits using PLDS and write VHDL code for basic gates and
combinational circuits.
4. Analyse sequential circuits using flip-flops and design registers, counters.
5. Represent a sequential circuit using Finite State machine and apply state minimization techniques
to design a FSM

UNIT – I
Design Concepts: Digital Hardware, Design process, Design of digital hardware. Introduction to logic
circuits – Variables and functions, Logic gates and networks. Boolean algebra, Synthesis using gates, Design
examples. Optimized implementation of logic functions using K-Map and Quine-McCluskey Tabular
method

UNIT – II
Number representation: Addition and Subtraction of signed and unsigned numbers.
Combinational circuit building blocks: Half adder, Full adder, Multiplexers. Decoders. Encoders. Code
converters, BCD to 7-segment converter, Arithmetic comparator circuits.

UNIT – III
Design of combinational circuits using Programmable Logic Devices (PLDs): General structure of a
Programmable Array Logic (PAL), Programmable Logic Arrays(PLAs), Structure of CPLDs and FPGAs, 2-
input and 3-input lookup tables (LUTs)
Introduction to Verilog HDL: Verilog code for basic logic gates, adders, decoders

UNIT – IV
Sequential Circuits: Basic Latch, Gated SR Latch, gated D Latch, Master-Slave edge triggered flip-flops, T
Flip-flop, JK Flip-flop, Excitation tables. Registers, Counters, Verilog code for flip-flops

UNIT – V
Synchronous Sequential Circuits: Basic Design Steps, Finite State machine(FSM) representation using
Moore and Mealy state models, State minimization, Design of FSM for Sequence Generation and Detection,
Algorithmic State Machine charts.

12
Faculty of Engineering, O.U. AICTE Model Curriculum with effect from Academic Year 2019-20
Suggested Readings:
1. Moris Mano and Michael D CIletti, Digital Design, Pearson, fourth edition,2008
2. Zvi Kohavi, Switching and Finite Automata Theory, 3rd ed., Cambridge University Press-New Delhi,
2011.
3. R. P Jain, Modern Digital Electronics,4th ed., McGraw Hill Education (India) Private Limited, 2003
4. Ronald J.Tocci, Neal S. Widmer &Gregory L.Moss, “Digital Systems: Principles and Applications,”
PHI, 10/e, 2009.
5. Samir Palnitkar, “Verilog HDL A Guide to Digital Design and Synthesis,” 2nd Edition, Pearson
Education, 2006.

13
DIGITAL ELECTRONICS
UNIT-I
Part-1
DIGITAL ELECTRONICS
UNIT-I
Part-2
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DIGITAL ELECTRONICS
UNIT-I
Part-3
All possible combinations of 3 logic variables

A B C Decimal
Value
0 0 0 0
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All possible combinations of 4 logic variables

A B C D Decimal
Value
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0 1 1 1 7
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A B C D E Decimal
Value
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0 0 1 1 0 6
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UNIT-I
Part-4
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Half-adder:

Half adder is a logic circuit which adds two 1-bit numbers x and y and produce
two outputs sum s and carry c. The following diagrams in Fig.1 gives the truth
table , symbol and logic circuit of the half adder.

Fig.1.Half adder details

From the truth table it is observed that the logical expression for the two outputs
is as follows.

s=ab
c=ab
Full adder:

While adding two multi bit numbers the carry at a particular bit position i will
be moving to the next bit position i+1. The carry at the MSB is treated as carry
out. Hence a full adder is a logic circuit which adds three one bit numbers xi, yi
and ci and produce the outputs sum si and ci+1. The implementation details of
full adder is given in the following Fig.2.

Fig.2 : Full adder implementation details

From the truth table the logical expression for the outputs si and ci+1 are written
as

si =xiyici
ci+1=xiyi+yici+ciyi
Multiplexer (data-selector) :

A multiplexer is a combinational circuit which accepts multiple inputs and

produce one output. Generally the number of inputs will be 2n, where n is the
number of selection lined for the desired output. The smallest value of n is 1.
Multiplexer is termed simply as MUX. We have 2:1 MUX, 4:1 MUX, 8:1 MUX
,16:1 MUX and so on.

2: 1 MUX:

For a 2:1 MUX the two inputs are denoted as w0,w1 and output is denoted as f.
s is the single selection input. Figure 3 gives the implementation details of 2:1
MUX.

Fig.3 2:1 MUX implementation

From the truth table the sum of products logical expression for the 2:1 MUX is
given by f=s'w0+sw1 and the corresponding logic circuit is shown in (c).
4:1 MUX:

A 4:1 MUX (22: 1 MUX) consists of four inputs w0,w1,w2,w3 two selection
inputs s0,s1 and an output f. Figure 4 gives the implementation details of 2:1
MUX.

Fig.4 4:1 MUX implementation

The logical expression for the 4 : 1 MUX is given by

Implementation of a 4: 1 MUX using 2: 1 MUX:

Fig.5 4:1 MUX using 2:1 MUX

16:1 MUX:

A 16:1(24:1) MUX consists of 16 inputs w0,w1.w2,...........,w15 and an output f

with four selection outputs s0,s1,s2,s3. The truth table of 16:1 is given in the
following Figure 6.

s3 s2 s1 s0 Input
0 0 0 0 wo
0 0 0 1 w1
0 0 1 0 w2
0 0 1 1 w3
0 1 0 0 w4
0 1 0 1 w5
0 1 1 0 w6
0 1 1 1 w7
1 0 0 0 w8
1 0 0 1 w9
1 0 1 0 w10
1 0 1 1 w11
1 1 0 0 w12
1 1 0 1 w13
1 1 1 0 w14
1 1 1 1 w15

Fig.6 16:1 MUX truth table

16:1 MUX using 4:1 MUX:

Fig.7 16:1 MUX Implementation using 4:1 MUX

Demultiplexer:

A demultiplexer is a combinational circuit that accepts 1 input and routes the

output to 2N lines, where N denote the number of selection lines. Figure 8 gives
the general implementation of a demutiplexer.

Fig.8 Demultiplexer
Decoder :
Decoder is a combinational circuit that is used to decode the encoded
information. A decoder will have n inputs and 2n outputs. For each input
combination 1 of the 2n is asserted. There are two types of decoders.
1. active high 2. active low

In a active high decoder the output is asserted to '1'. In an active low decoder
the output is asserted to '0'. By default a decoder is active high.
Each decoder will have an input En for enabling or disabling the decoding.
The following figure 9 gives the structure of a n to 2n decoder.

Fig.9 : n to 2n decoder
2-to- 4 decoder:

For a 2 to 4 decoder the two inputs are w0,w1 and four outputs y0,y1,y2.y3 and a
single En bit.

Truth tables:

Active high 2-to-4 decoder :

En w1 w0 y0 y1 y2 y3

1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 x x 0 0 0 0

Active low 2-to-4 decoder :

En w1 w0 y0 y1 y2 y3

1 0 0 0 1 1 1
1 0 1 1 0 1 1
1 1 0 1 1 0 1
1 1 1 1 1 1 0
0 x x 0 0 0 0
From the truth table of an active high decoder the logical expressions for the
four outputs y0,y1,y2.y3 are as follows.

y0 = w1'w0'
y1= w1'wo
y2=w1w0'
y3=w1w0

The logic diagram of a 2 to 4 decoder is shown in figure 10.

Fig.10 : 2-to-4 decoder logic circuit

3 to 8 decoder:

A 3 to 8 decoder will have 3 inputs w0,w1,w2 and 8 outputs from y0 to y7.The truth table of a
3 to 8 decoder is given below. Figure 11 gives the block diagram of 3-to-8 decoder.

w0 y0
y1
w1
3-to-8 y2
decoder
y3
w2
y4

y5
En y5
y6
y7
Fig 11: 3-to-8 decoder
 En w2 w1 w0 y0 y1 y2 y3 y4 y5 y6 y7

1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
0 x x x 0 0 0 0 0 0 0 0

Implementation of a 3 to 8 decoder using 2 to 4 decoder:

The following structure in figure 11 gives the implementation of a 3 to 8

decoder using two 2 to 4 decoders. The inputs for both the decoders are w1,w0 .
The outputs of the upper decoder are y0,y1,y2.y3 and the outputs of the lower
decoder are y4,y5,y6.y7.

Enable inputs for upper and lower decoders are w2' En and w2 En respectively.

Fig .11 : 3-to-8 decoder using two 2-to-4 decoders

 4-to-16 decoder

This type of decoder is having four inputs w0, w1,w2,w3 and 16 inputs y0 to y15
with an Enable input En.

Truth Table

En w3 w2 w1 w0 y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15

1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4-to-16 decoder implementation using 2-to-4 decoder is shown in Figure 12.

It consists of five 2-to-4 decoders --- 1 decoder at the first level and 4 decoders
at the second level. For the first level decoder the inputs are w3,w2 and En
inputs. The four outputs of this decoder act as enable inputs for the four
decoders at the second level. All the four decoders at the second level will have
the common inputs w1,w0
 Fig 12: 4-to-16 decoder using 2-to-4 decoder

Encoder:

It has maximum of 2n inputs and n outputs. The output of an encoder is a binary

code equivalent to the input, which is active high. The general structure is
shown in the following figure.
The truth table and logic diagram of the 4-to-2 encoder is shown in
Figure 13.
4 to 2 encoder truth table :

Fig 13: 4-to-2 encoder

The logical expressions for the 4-to-2 encoder are given by

y1= w1+w3
y0=w2+w3

while deriving the logical expressions for the encoder the values of the outputs
for the remaining 12 rows are considered as don't care.
Priority Encoder :

 The encoding is done based on the priority of input signals.

 In a priority encoder each input has a priority level associated

with it.

 The encoder outputs indicate the active input that has the highest
priority.

 When an input with a highest priority is asserted , the other

inputs with lowest priority are ignored.

 In a priority encoder there will be an enable bit variable z at the

output. When z=1 the encoding will be performed.
BCD to 7-Segment Display

A BCD to 7- segment display accepts BCD inputs w0, w1.w2 , w3 and produce
outputs on seven segments a,b,c,d,e,f,g. All the segments are light emitting
diodes. When any segment is activated it will have a value of 1 and 0 if
deactivated. The details of the BCD to 7-segment display is shown in Figure 14.

Fig 14: BCD to 7-Segment display

The SOP expressions for the seven segments are as follows. The
decimal values from 10 to 15 are treated as don't cares since BCD
digits are from 0 to 9.

a=∑m(0,2,3,5,6,7,8,9)+ D(10,11,12,13,14,15)

b= ∑m(0,1,2,3,4,7,8,9)+ D(10,11,12,13,14,15)

c=∑m(0,1,3,4,5,6,7,8,9)+ D(10,11,12,13,14,15)

d=∑m(0,2,3,5,6,8,9)+ D(10,11,12,13,14,15)

e=∑m(0,2,6,8)+ D(10,11,12,13,14,15)

f=∑m(0,5,6,8,9)+ D(10,11,12,13,14,15)

g=∑m(2,3,4,5,6,8.9)+ D(10,11,12,13,14,15)
 UNIT-3

Programmable Logic Devices:

The logic gates such as AND, OR , NAND , NOR gates etc always produce fixed
functionality. In order to design logic circuits with variable functionality Programmable logic
Devices (PLDs) are used. PLDs contains a collection of logic circuit elements that can be
customized in different ways. A PLD can be viewed as a “black box” that contains logic
gates and programmable switches, as illustrated in Fig.1. The programmable switches allow
the logic gates inside the PLD to be connected together to implement whatever logic circuit is
needed.

Fig 1. Programmable Logic Device as a Black Box

There are several types of PLDs out of which the popularly used are
1.Programmable Logic Array (PLA)
2. Programmable Array Logic (PAL)

Programmable Logic Array (PLA) : The general structure of a PLA is shown in Fig.2.

Fig 2: General structure of PLA

Based on the idea that logic functions can be realized in sum-of-products form, a PLA
comprises a collection of AND gates that feeds a set of OR gates. As shown in the Fig.2
the PLA’s inputs x1, . . . , xn pass through a set of buffers (which provide both the true value
and complement of each input) into a circuit block called an AND plane, or AND array.
The AND plane produces a set of product terms P1, . . . , Pk . Each of these terms can be
configured to implement any AND function of x1, . . . , xn. The product terms serve as the
inputs to an OR plane, which produces the outputs f1, . . . , fm. Each output can be configured
to realize any sum of P1, . . . , Pk and hence any sum-of-products function of the PLA
inputs.

In PLA both AND plane and OR plane or programmable.

An example of a PLA implementing the logic functions f1 = x1x2+ x1x3'+x1'x2'x3
and f2 = x1x2+x1'x2'x3+x1x3 is shown in Fig.3. In this there are four product terms
P1= x1x2 , P2= x1x3', P3 = x1'x2'x3 and P4= x1x3
Hence the logic functions implemented are f1 =P1+P2+P3 and f2 = P1+P3+P4

Fig 3: An example of a logic functions implemented by PLA.

Programmable Array Logic (PAL) :

In PLA both AND plane and OR plane or programmable. Historically, the programmable
switches presented two difficulties for manufacturers of these devices: they were hard to
fabricate correctly, and they reduced the speed-performance of circuits implemented in the
PLAs. These drawbacks led to the development of a similar device in which the AND plane
is programmable, but the OR plane is fixed. Such a chip is known as a programmable array
logic (PAL) device. Because they are simpler to manufacture, and thus less expensive than
PLAs, and offer better performance, PALs have become popular in practical applications.
An example of PAL implementing the logic functions f1=x1x2x3'+x1'x2x3 and
f2 = x1'x2'+x1x2x3 is shown in Fig.4
In this example there are four product terms P1= x1x2x3' , P2= x1'x2x3, P3=x1'x2', P4= x1x2x3
Hence the logic functions implemented are f1=P1+P2 and f2= P3+P4

Fig 4: An example of a logic functions implemented by PAL

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Conesion
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3 to a
be obbed y adelivg BCD umben

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a BCD numbe Cith blts

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a x S 3 numbenb

B B2 B Bo X3 Y2 X o
Xo

B O D
1

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5
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O O O

Fig- nuth Tabla of BCB to xs-3 Coiension

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 Subjeci: DIGITAL ELECTRONICs

TOPIC: Poqrammable Logic Devic

Implement xDR2 and XNOR2 Using frogrammable

Lo9ic Anay (PLA) and 'roqrammable Ardy Logi

(PAL).

Spl Let the logcal éxprt5sion or he tuoo dnput

XOR gate be fie,

dimilarly, the Jogi Cal Expstbsion for he tuoo dnput

XAlOR 9aBe be fo 1. e

The n0.oPooduct rms om he fonctiony Gnct f

Qve a ollo5

theunctHon's f and a Can be e-coritten

AloO
1eyms 4
in tems of froduct
The
The no.
no. o AND gat eg uired Qn AND Plane coi|
be
gVtn byno. Roduct emy,Simila-dy, te no.P
OR at seguired io an OR plane Lsill be ven

by th no.
fonc ons toe hav.

Implemecotinq xOR 2 USin9 PLA

In a PLA , both he AND Plane and OR plane

QTe r0grammna ble .

Hese, Lo e Teguie AuD alts nan ANND plane

and OR m An OR Plane. Qnd tte tuoo 3]ps

qatts
Ore 1 and .

OR Plane

D
D
DA
AND lane
PLA tor XOR 2
lmplementing XNOR 2 Using PAL

In aPAL ,A ND plane is PrOqommable coh treas

OR Plane is not
psog7ammable.
Htre, we regure AND gate n an AND plane
and te 2 oR gate esith ffa, 3, Re 0s dnpuls, tor

Gnd fa

a
D
AND P Gne

PAL tor XNDR 2

*IMPLEMENT FULL ADDER UsING PLLA

Truth table -foY Fu Adder

S Co
O O

O O

O
O

S, , ,c
,9,e; 7,,,+ 19,C 7,9, +

Co

Assianining the product terms :

P,,,C P 7,9;C, P - z,9, , ;9,C; ,

P ;3

PLA:
Implemesting
C

P2

Ps
Pa

Co
 IMPLEMENT HALF ADDER USIN6 PAL
Troth table fov Ha1f AddeY

O O

S ®y

C 1
Assigning the product terms

P, P,9 P
Implem enting3 using PAL

-S

P
C
Complex Programmable Logic Device (CPLD):

PLAs and PALs are useful for implementing a wide variety of small digital circuits. They are
useful designing chips which are supporting a combined number of inputs plus outputs of not
more than 32. For implementation of circuits that require more inputs and outputs, either
multiple PLAs or PALs can be employed or else a more sophisticated type of chip, called a
complex programmable logic device (CPLD), can be used.

A CPLD comprises multiple circuit blocks on a single chip, with internal wiring resources
to connect the circuit blocks. Each circuit block is similar to a PLA or a PAL; we will refer to
the circuit blocks as PAL-like blocks. An example of a CPLD is given in Fig.5.
It includes four PAL-like blocks that are connected to a set of interconnection wires.
Each PAL-like block is also connected to a sub circuit labeled I/O block, which is attached
to a number of the chip’s input and output pins. CPLDs are used for the implementation of
many types of digital circuits.

Fig.5: Structure of CPLD

Field Programmable Gate Array (FPGA):

A large CPLD that has 1000 macrocells can implement circuits of up to about 20,000
equivalent gates. To implement larger circuits, it is convenient to use a different type of chip
that has a larger logic capacity. A field-programmable gate array (FPGA) is a programmable
logic device that supports implementation of relatively large logic circuits. FPGAs are quite
different from SPLDs and CPLDs because FPGAs do not contain AND or OR planes.

Instead, FPGAs provide logic blocks for implementation of the required functions. The
general structure of an FPGA is illustrated in Fig.6. It contains three main types of resources:
logic blocks, I/O blocks for connecting to the pins of the package, and interconnection wires
and switches. The logic blocks are arranged in a two-dimensional array, and the
interconnection wires are organized as horizontal and vertical routing channels between rows
and columns of logic blocks. The routing channels contain wires and programmable switches
that allow the logic blocks to be interconnected in many ways.

Fig.6 : General structure of FPGA

FPGAs can be used to implement logic circuits of more than a few hundred thousand
equivalent gates in size. Each logic block in an FPGA typically has a small number of inputs
and outputs. The most commonly used logic block is a lookup table (LUT), which contains
storage cells that are used to implement a small logic function. Each cell is capable of
holding a single logic value, either 0 or 1. The stored value is produced as the output of the
storage cell. LUTs of various sizes may be created, where the size is defined by the number
of inputs. Fig.7 shows the structure of a small LUT. It has two inputs, x1 and x2, and one
output, f .

Fig.7 : Structure of a 2-input LUT

Implementation of a logic function of a 2-input LUT:

Fig 8:Truth Table of 2 i/p XOR gate

Fig.9 : Storage cell contents in the 2-input LUT

Implementation of logic function using a 3-input LUT:

Consider the implementation of 3 input XOR gate using a 3 input LUT. The truth table is
shown in Fig.10

x1 x2 x3 f

0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Fig .10 : Truth table of 3 input XOR gate

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Sequential Circuits:

In combinational logic circuits the output at any pint of time dependent upon the present
inputs. In sequential circuits the output is dependent not only on the present inputs and also
on the past behavior of the circuit. To store the past storage elements are required. The
contents of the storage elements are said to represent the state of the circuit. Hence in
sequential circuits the output is dependent not only on the inputs applied but also on the state
of the circuit.The storage elements are referred to as memory elements. There are two types
of memory elements. 1. Latches 2. Flip-flops.

Basic Latch:

The basic SR (Set- Reset) latch using NOR gates is shown Fig. 1(a) and its truth table in
Fig.1(b). The outputs Qa and Qb of the NOR gates represents the state of the latch. Both are
complementary to each other.

Fig.1 : Basic SR Latch

S=0, R=0 will keep the latch to remain in the same state
S=0 , R=1 will give Qa = 0 , Qb =1 represent the Reset state.

S=1, R=0 will give Qa = 1, Qb =0 represent the Set state.

S=1, R=1 will give Qa=0 , Qb=0 represent the undesired state.

The timing diagram of SR latch is shown in Fig.2. A timing diagram represent the state
changes i.e Qa & Qb of the latch with respect to changes in the values of inputs S and R at
different time instants. The timing diagram in Fig.2 can be interpreted as follows.

 The initial state of latch are shown as Qa=0 and Qb=1 till time t2
 At t2, for S=1. R=0 the states change to set state with Qa=1 and Qb=0
 At t3, for S=0 , R=0, no change in the present state. Hence Qa=1 and Qb=0
 At t4, for S=0, R=1, the states change to reset state with Qa=0 and Qb=1
 At t5, for S=1, R=1, the undesired state is obtained with Qa=0 and Qb=0
 The causality relationship is indicated by the arrows in the timing diagram. As
observed at t2 S=1, causes Qb to change to 0 which in turn causes Qa to change to
1.At t4 R=1 causes Qa to change to 0 which in turn changes Qb to change to 1. At t5
S=1 causes Qb to change to 0 and so on.
 Like this we can observe state changes for the remaining time instants
 Fig.2: Timing Diagram of SR latch

SR Latch using NAND gates:

Fig.3 shows two NAND gates 1 and 2 connected in a cross-coupled manner acting as SR
latch.

Fig.3: SR latch using NAND gates

Truth Table:

S R Q Q'

0 0 1 1
0 1 1 0 ( Set state)
1 0 0 1 (Reset state)
1 1 No change

The interpretation of truth table is as follows. For a NAND gate if one of the inputs is 0 then
the output is 1. Q and Q' denote the true and complementary state of the latch. H
There fore for S=0, R=0 Q=1,Q'=1 which is an undesired state
For S=0, R=1 Q=1, Q'=0 Set State
For S=1,R=0 Q=0, Q'=1 Reset state
For S=1, R=1 ------ > Assume present state Q=0, Q'=1 then the output of gate 1 Q=0 and
output of gate 2 Q'=1. Hence there is no change in the present state. Similar analysis can be
done for present state Q=1, Q'=0. For this also S=R=1 represent the no change state.

Gated SR latch using NAND gates:

In order to control the state change of a SR latch a control signal is applied as input Such type
of a latch with a control input signal is called Gated SR latch which is shown in Fig.4.

Fig.4: Gated SR latch

As shown in Fig.4(a) the SR latch is enabled when clk=1. For clk=0 , the circuit is disabled.
The truth table is shown in Fig.4(b). The timing diagram is shown in Fig.5. For a latch or flip-
flop the present state is denoted as Q(t). The state transition or next state is denoted as Q(t+1).
The timing diagram is shown in Fig.5.
The timing diagram can be interpreted as follows.
 Initially Q=0, Q'=1
 For the first instance of Clk=1, S=1,R=0 the state changed to Q=1,Q'=0
 For the second instance of Clk=1, S=0, R=1 the state changed to Q=0, Q'=1
 For the third instance of Clk=1, S=0, R=0, the state is not changed
 Like that state changes can be examined for Clk=1 and different values of S and R

Fig.5: Timing diagram of Gated SR Latch

 Fig.6: Graphical Symbol of SR latch

Gated SR Latch with NAND gates:

Fig.7: Gated SR Latch with NAND gates

The operation of the circuit shown in Fig.7 is described by the truth table in Fig.4(b). As this
design using NAND gated requires fewer transistors this is more preferred when compared to
the structure in Fig.4(a).

Gated D Latch:

In applications such serial addition of two numbers the carries generated from LSB to MSB
are to stored for some time while performing addition at each bit position. Hence it is
advisable to a single input latch to store the carry value instead of two values S and R. The
complete structure of a Gated D Latch is shown Fig.8. Fig.8(a) represents the logic diagram,
Fig.8(b) represents the truth table, Fig.8(c) represents the graphical symbol and Fig.8(d)
represents the timing diagram.
As shown in Fig.8(a) , D latch is a modified version of SR latch with NAND gates. It consists
of single data input, called D, and it stores the value on this input, under the control of a clock
signal, It is called gated D latch. Here S=D and R=D'. Let the outputs of the first two NAND
gates will be S' and R'.

The interpretation of the truth table in Fig. 8(b) is as follows.

 For Clk=0, D=x, the D latch will remain in the present state Q(t) since S'=1, R'=1
 For Clk=1, D=0, the latch will be reset with Q(t+1)=0, since S'=1, R'=0
 For Clk=1, D=1, the latch will be set with Q(t+1)=1, since S'=0,R'=1
 Same observation can be made from the timing diagram in Fig.8(d)
 Fig.8 Gated D Latch

Detailed truth table of the D Latch:

Clk D S=D R=D' S' R' Q(t+1)

0 x x x 1 1 Q(t)

1 0 0 1 1 0 0

1 1 1 0 0 1 1

Master-Slave D Flip-flop:

 Consider the circuit shown in Fig.9(a). It consists of two gated D latches.

 The first,called master, changes its state while Clock = 1. The second, called slave,
changes its state while Clock = 0.
 The operation of the circuit is such that when the clock is high, the master tracks the
value of the D input signal and the slave does not change. Thus the value of Qm
follows any changes in D, and the value of Qs remains constant.
 When the clock signal changes to 0, the master stage stops following the changes in
the D input. At the same time,the slave stage responds to the value of the signal Qm
and changes state accordingly. Since Qm does not change while Clock = 0, the slave
stage can undergo at most one change of state during a clock cycle.
 From the external observer’s point of view, namely, the circuit connected to the
output of the slave stage, the master-slave circuit changes its state at the negative-
going edge of the clock. The negative edge is the edge where the clock signal changes
from 1 to 0.
 Regardless of the number of changes in the D input to the master stage during one
clock cycle, the observer of the Qs signal will see only the change that corresponds to
the D input at the negative edge of the clock.
 The same behavior is observed from the timing diagram in Fig.9 (b).
 Such type of a latch which changes its state at the edge of a clock is called Flip-flop.

Fig.9: Master-Slave D Flip-flop

D Flip-flop with Clear and Preset:

a) Positive Edge Triggered D-FF b) Negative Edge Triggered D-FF

Fig.10: D Flip-flop with Clear and Preset for positive and negative edge triggering

As observed from the graphical symbols of D-FF from Fig.10(a) & 10(b), the two control
active low inputs Preset and Clear are used to set and reset the states of the flip-flop before
applying inputs. If Clear=0 , in both the cases the state Q=0 . If Preset=0, in both the cases
Q=1.
For a D FF , Q(t+1) =D at the edge of the clock

T Flip-flop:

Fig 11: T Flip-flop

T (Toggle) Flip-flop is a modified version of D flip-flop as shown in the logic diagram of
Fig.11(a). As observed positive edge triggering is used for the clock. There is a feedback
from the true state Q and complementary state Q' to the input. In this case D =T'Q+TQ'. As
observed from the truth table of Fig.11(b) and the detailed truth table given in Fig.12, the
state of the T-FF is not changed when T=0 and it is toggled or complemented when T=1.

T D=T'Q+TQ' Q(t+1)

0 Q(t) Q(t)

1 Q'(t) Q'(t)

Fig.12 Detailed Truth table of T-FF

The interpretation of the timing diagram in Fig.11 is as follows.

 Initial state of Q=0

 For the first instance of positive edge of the clock T=1, hence Q is toggled from 0 to
1.
 For the second instance of positive edge of the clock T=0, hence Q is unchanged and
will remain at 1
 For the third instance of positive edge of the clock T=1, hence Q is toggled from 1 to
0.
 In this way the process will be repeated for different positive instances of the clock
and the value of T.

JK Flip-flop:

Fig.13: JK Flip-flop
Figure 13 shows the details of the JK Flip-flop. In Fig.13(a) the logic diagram is shown,
which is a modified version of D Flip-flop. Here also There is a feedback from the true state
Q and complementary state Q' to the input. In JK FF D=JQ'+K'Q. The truth table and the
graphical symbol are given in Fig.13(a) & 13(b) respectively. The detailed truth table is given
in Fig.14.

J K D=JQ'+K'Q Q(t+1)

0 0 Q(t) Q(t)

0 1 0 0

1 0 1 1

1 1 Q'(t) Q'(t)

Fig.14: Detailed truth table of JK FF

Excitation Tables:

Excitation tables are the inputs required for the various flip-flops to make a transition from
present state to next state i.e from Q(t) to Q(t+1).

SR Flip-flop Excitation Table:

Q(t) Q(t+1) S R S R
0 0 0 0 0 x
0 1
0 1 1 0 1 0
1 0 0 1 0 1

JK Flip-flop Excitation Table

Q(t) Q(t+1) J K J K
0 0 0 0 0 x
0 1
0 1 1 0 1 x
1 1
1 0 0 1 x 1
1 1
1 1 0 0 x 0
1 0

Characteristic equation of JK FF Q(t+1) = JQ’+K’Q

D Flip-flop Excitation Table :

Q(t) Q(t+1) D

0 0 0

0 1 1

1 0 0

1 1 1

Characteristic equation of D FF , Q(t+1) = D

T Flip-flop Excitation Table :

Q(t) Q(t+1) T

0 0 0

0 1 1

1 0 1

1 1 0

Characteristic equation of T FF, Q(t+1) = TQ

Applications of Flip-flops:

Flip-flops are used in many applications such as counters , registers etc.

Counters:

Counter circuits are used in digital systems for many purposes. They may count the number
of occurrences of certain events, generate timing intervals for control of various tasks in a
system, keep track of time elapsed between specific events, and so on.
There are two types of counters
1. Asynchronous counters
2.Synchronous counters

Asynchronous counters : In asynchronous counters all the flip-flops are not triggered by the
same clock. The first flip-flop is triggered directly by the clock and the subsequent flip-flops
are triggered either by the true or complementary states of the previous flip-flops. These are
also called as ripple counters.

Synchronous counters: In synchronous counters all the flip-flops are triggered by the same
clock.
Asynchronous 3-bit up counter:

This counter consists of three T flip-flops. The counting sequence will be

000,001,010,011,100,101,110,110,000,.......................... . The structure and the timing
diagram are given in Fig .15

The up and down count sequence of the states of FFS for one iteration is given in the
following table.

Q2 Q1 Qo Q2 Q1 Qo

0 0 0 1 1 1
0 0 1 1 1 0
0 1 0 1 0 1
0 1 1 1 0 0
1 0 0 0 1 1
1 0 1 0 1 0
1 1 0 0 0 1
1 1 1 0 0 0

As shown in Fig.15 (a) the asynchronous 3-bit up counter is realized by three T FFs with
states Q0, Q1, Q2. The first FF is triggered directly by the positive edge of the clock, second
FF by Q0' and the third by Q1'. The timing diagram is shown in Fig.15(b).

Fig .15 : Asynchronous 3-bit up counter

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Synchronous 3-bit up counter:

It consists of three T flip-flops with states Q 0, Q 1, Q 2 respectively. The count sequence for one
iteration is as follows

The T-inputs to the FFs will be as follows

T0 =1
T1= Q0
T2=Q0 Q1

For a n-bit synchronous up-counter

Tn = Q0 Q1 Q2 ............... Qn-1

Synchronous 3-bit down counter:

It consists of three T flip-flops with states Q 0, Q 1, Q 2 respectively. The count sequence for one
iteration is as follows

Clock Pulse Q2 Q1 Q0

1 1 1 1
2 1 1 0
3 1 0 1
4 1 0 0
5 0 1 1
6 0 1 0
7 0 0 1
8 0 0 0

As observed from the above table Q0 changes for every clock pulse. Q1 changes when Q0 =0 and Q2
changes when Q1=0.

The T inputs of the three FFs will be T0=1 , T1=Q0' , T2 = Q0' Q1'

For a n-bit synchronous down counter Tn = Q0' Q1' .................. Qn-1'

Synchronous 4-bit up-counter:

The details of a synchronous 4-bit up-counter are shown in the following Fig.1(a) and 1(b) with the
timing diagram. As observed from the figure it consists of four T-FFs with states Q0,Q1, Q2,Q3. All the
FFs are triggered by the same clock. The T inputs of the four FFs will be
T0=1, T1=Q0 , T2 = Q0 Q1 , T3 = Q0 Q1 Q2.

The counting sequence will be from 0000 to 1111. From the timing diagram it can be observed that Q 0
changes on every positive edge of clock, Q1 changes on the negative edge of Q0 , Q2 changes on the
negative edge of Q1. Q3 changes on the negative edge of Q2. The initial state of all FFs is 0000.

Fig 1. Synchronous 4-bit up counter

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Registers:
A flip-flop stores one bit of information. When a set of n flip-flops is used to store n bits of
information, such as an n-bit number, we refer to these flip-flops as a register. A common
clock is applied to each flip-flop in a register. D flip-flop is commonly used in the registers.
The most popularly used register is a shift register, which shifts data bits either serially or
parallely The shift can be performed either to left or right. There are 4 types of shift registers.
T
1. Serial Input Serial Output shift register
2. Serial Input Parallel Output shift register
3. Parallel Input Serial Output shift register
4. Parallel Input Parallel Output shift register

The data transfer in the 4 registers is shown in Fig.1

Fig.1 : Data Transfer in shift registers

The structure of different shift registers is shown in Fig.2, Fig.3 & Fig.4

Fig.2: Serial Input Serial Output shift right register

 Fig.3: Serial Input Serial Output shift left register

Fig.4: Serial Input Parallel Output shift left register

Operation of a shift register:

Fig.5(a) shows a four-bit shift register that is used to shift its contents one bit position
to the right. The data bits are loaded into the shift register in a serial fashion using
the In input. The contents of each flip-flop are transferred to the next flip-flop at each
positive edge of the clock. An illustration of the transfer is given in Fig.5 (b), which
shows what happens when the signal values at In during eight consecutive clock cycles are
1, 0, 1, 1, 1, 0, 0, and 0, assuming that the initial state of all flip-flops is 0.
 Fig.5 : a 4-bit shift right register and a shift sequence

Let the initial state of all the D FFs Q1, Q2, Q3, Q4 will be 0000. As observed from the shift
sequence in Fig.5(b), for an input sequence In = 10111000 1-bit will be serially shifted right
on every clock pulse. For every clock pulse Q1 = In, Q2 =Q1, Q3= Q2 and Q4 = Q3 and
out= Q4.

Comparison between Synchronous and Asynchronous counters:

For Synchronous counters ------

 All the FFs are clocked simultaneously.

 Design and implementation becomes tedious and complex as the number of states
increases.
 They are faster because of reduced propagation delay.

For Asynchronous counters -------

 All the FFs are not clocked simultaneously.

 Design and implementation is very simple even for more number of states.
 The speed of these counters is slow as the clock is propagated through a number of
FFs.
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Synchronous Sequential circuits

Sequential circuits are also called finite state machines (FSMs). The name derives from the
fact that the functional behavior of these circuits can be represented using a finite number of
states. The general form of a sequential circuit is shown in Fig.1.

Fig.1: General form of a sequential circuit

From the structure shown in Fig.1, the input is W ,output is Z and the state is Q. Two types
of FSM are defined, Mealy FSM and Moore FSM. In Mealy FSM the output Z is dependent
on both the primary inputs and the state. In Moore FSM output is dependent on the state of
the circuit.

Basis Design steps of FSM:

Suppose that we wish to design a circuit that meets the following specification:

1. The circuit has one input, w, and one output, z.

2. All changes in the circuit occur on the positive edge of a clock signal.
3. The output z is equal to 1 if during two immediately preceding clock cycles the input
w was equal to 1. Otherwise, the value of z is equal to 0.

The sequence of the input and output signals for the given specifications is given in the
following Fig.2

Fig.2: Sequence of the input and output signals

State Diagram; The pictorial representation of the FSM can be represented in the form
of a state diagram, which is a graph that depicts states of the circuit as nodes (circles)
and transitions between states as directed arcs.
Mealy FSM State Diagram:

Fig.3: State diagram using Mealy FSM

The state diagram shown in Fig.3 can be interpreted as follows.

 States A and B appear as nodes in the diagram

 On Reset the machine is in state A, it will remain in state A if w = 0 and the output
will be 0. This is indicated by an arc with the label w = 0/z = 0. When w becomes 1,
the output stays at 0 until the machine moves to state B at the next active clock edge.
This is denoted by the arc from A to B with the label w = 1/z = 0.
 In state B the output will be 1 if w = 1, and the machine will remain in state B, as
indicated by the label w=1/z=1 on the corresponding arc. If w = 0 in state B, then the
output will be 0 and a transition to state A will take place at the next active clock
edge.

State Table:

The tabular representation of the state diagram is called state table. The table indicates all
transitions from each present state to the next state for different values of the input signal.

The state table and state assigned table of the Mealy FSM shown in the state diagram of Fig.3
is shown in Fig.4 and Fig.5 respectively.

Fig.4 : Mealy FSM State Table

 Fig.5 : Mealy FSM State Assigned Table

Moore FSM:

The state diagram for the specifications listed in Fig.2 is shown in the following Fig.6.

Fig.6: Moore FSM state diagram

The interpretation of the Moore FSM state diagram in Fig.6 is as follows.

 States A, B, and C appear as nodes in the diagram.

 Node A represents the starting state, and it is also the state that the circuit will reach
after an input w = 0 is applied. In this state the output z should be 0, which is
indicated as A/z=0 in the node. The circuit should remain in state A as long as w= 0,
which is indicated by an arc with a label w = 0 that originates and terminates at this
node.
 The first occurrence of w = 1 (following the condition w = 0) is recorded by moving
from state A to state B. This transition is indicated on the graph by an arc originating
at A and terminating at B. The label w = 1 on this arc denotes the input value that
 causes the transition. In state B the output remains at 0, which is indicated as B/z=0 in
the node.
 When the circuit is in state B, it will change to state C if w is still equal to 1 at the next
active clock edge. In state C the output z becomes equal to 1. If w stays at 1 during
subsequent clock cycles, the circuit will remain in state C maintaining z = 1.
 If w becomes 0 when the circuit is either in state B or in state C, the next active clock
edge
 will cause a transition to state A to take place.

The state table and state assigned table of the Moore FSM shown in the state diagram of Fig.6
is shown in Fig.7 and Fig.8 respectively.

Fig.7: State Table of Moore FSM

Fig.8: State Assigned Table of Moore FSM

Algorithmic State Machine (ASM) Charts: The state diagrams and tablesare convenient for
describing the behavior of FSMs that have only a few inputs and outputs. For larger machines
the designers often use a different form of representation, called the algorithmic state
machine (ASM) chart.
An ASM chart is a type of flowchart that can be used to represent the state transitions and
generated outputs for an FSM. The three types of elements used in ASM charts are 1.State
box 2. Decision box. 3. Conditional output box. Their representation is shown in Fig. 9(a), (b)
& (c).
 Fig.9: Elements of ASM Chart

State box – A rectangle represents a state of the FSM. It is equivalent to a node in the
state diagram or a row in the state table. The name of the state is indicated outside the
box in the top-left corner. The Moore-type outputs are listed inside the box. These are
the outputs that depend only on the values of the state variables that define the state;
we will refer to them simply as Moore outputs. It is customary to write only the name
of the signal that has to be asserted. Thus it is sufficient to write z, rather than z = 1, to
indicate that the output z must have the value 1.

Decision box –A diamond indicates that the stated condition expression is to be tested
and the exit path is to be chosen accordingly. The condition expression consists of one
or more inputs to the FSM. For example, w indicates that the decision is based on the
value of the input w, whereas w1 ・w2 indicates that the true path is taken if w1 = w2 = 1
and the false path is taken otherwise.

Conditional output box – An oval denotes the output signals that are of Mealy type.
These outputs depend on the values of the state variables and the inputs of the FSM;
we will refer to these outputs simply as Mealy outputs. The condition that determines
whether such outputs are generated is specified in a decision box.
ASM chart for Mealy FSM:

The following Fig.10 gives the ASM chart of Mealy FSM of the state diagram represented in
Fig.3

Fig.10: ASM chart for Mealy FSM

ASM chart for Moore FSM:

The following Fig,11 describes the ASM chart of the state diagram shown in Fig.6

Fig.11: ASM chart for Moore FSM

Comparison between Mealy and Moore FSM:

Mealy FSM Moore FSM

1. The output is a function of both inputs and 1. The output is a function of present
present state. state.
2. Input changes may effect the output of the FSM 2. Input changes may not effect the
output of the FSM
3. It requires less number of states to implement 3. It requires more number of states
the same logic function. implement the same logic function

Sequence Detection:

One of the main application of the FSM is to detect the occurrence of a sequence of bits or a
pattern in a random binary input sequence 'w' or 'x'. If a particular sequence is detected the
output 'z; will be 1.
The sequence detector can be represented by state diagram using Mealy or Moore FSM.

Serial Adder: Consider the addition of two binary numbers 'a' and 'b' . If they are added bit
by bit from LSB to MSB they will produce two outputs carry 'c' and sum 's'. This can be
represented by a Mealy or Moore FSM with states representing the carry of '0' or '1'. The
following Fig.12 represent the Mealy FSM state diagram and state table with state 'G'
representing the carry '0' and state 'H" representing the carry '1'. At each state the two input
bits a & b are tested for the combinations '00', '01', '10' , '11' and to verify the sum 's' being '0'
or '1'.

Fig.12 :Mealy FSM state diagram and state table for serial adder
Fig.13 represent the Moore FSM state diagram and state table for a serial adder. As observed
from the state diagram it requires more number of states G0. G1. H0, and H1. Here G0 and G1
represent produce the output sum of '0' and '1' respectively for carry '0'. H0 and H1 represent
produce the output sum of '0' and '1' respectively for carry '1'.

Fig.13: Moore FSM state diagram and state table for serial adder
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