R18 B.Tech.

IT Syllabus
I.RAVI KUMAR JNTU HYDERABAD

IT601PC: INTRODUCTION TO EMBEDDED SYSTEMS

III Year B.Tech. IT II -Sem L T P C

3 0 0 3
Prerequisites
1. A course on “Digital Logic Design and Microprocessors”
2. A course on “Computer Organization and Architecture”

Course Objectives
 To provide an overview of principles of Embedded System
 To provide a clear understanding of role of firmware, operating systems in correlation with
hardware systems.

Course Outcomes
 Expected to understand the selection procedure of processors in the embedded domain.
 Design procedure of embedded firm ware.
 Expected to visualize the role of realtime operating systems in embedded systems.
 Expected to evaluate the correlation between task synchronization and latency issues

UNIT - I
Introduction to Embedded Systems:
Definition of Embedded System, Embedded Systems Vs General Computing Systems, History of
Embedded Systems, Classification of Embedded Systems, Major application areas, Purpose of E
bedded Systems, Characteristics and Quality attributes of Embedded Systems.

UNIT - II
The Typical Embedded System:
Core of the Embedded System, Memory, Sensors and Actuators, Communication Interface, Embedded
Firmware, Other System components.

UNIT - III
Embedded Firmware Design and Development:
Embedded Firmware Design, Embedded Firmware Development Languages, Programming in
Embedded C.

UNIT - IV
RTOS Based Embedded System Design:
Operating System basics, Types of Operating Systems, Tasks, Process, Threads, Multiprocessing and
Multi-tasking, Task Scheduling, Threads-Processes-Scheduling putting them together, Task
Communication, Task Synchronization, Device Drivers, How to choose an RTOS

UNIT - V
Integration and Testing of Embedded Hardware and Firmware:
Integration of Hardware and Firmware, Boards Bring up
The Embedded System Development Environment:
The Integrated Development Environment (IDE), Types of files generated on Cross-Compilation,
Disassembler/Decompiler, Simulators, Emulators and Debugging, Target Hardware Debugging,
Boundary Scan.

TEXT BOOKS:
1. Shibu K V, “Introduction to Embedded Systems”, Second Edition, Mc Graw Hill
 I.RAVI KUMAR
INTRODUCTION TO EMBEDDED SYSTEMS

Unit-I:
Introduction to Embedded Systems:
Definition of Embedded System, Embedded Systems Vs General Computing Systems, History of
Embedded Systems, Classification of Embedded Systems, Major application areas, Purpose of E
bedded Systems, Characteristics and Quality attributes of Embedded Systems.

Embedded Systems
An Electronic/Electro mechanical system which is designed to perform a specific function
and is a combination of both hardware and firmware (Software). E.g. Electronic Toys, Mobile
Handsets, Washing Machines, Air Conditioners, Set Top Box, DVD Player etc.
Embedded Systems vs. General Computing Systems
No. General Purpose Computing System Embedded System (ES)
1. A system which is a combination of A system which is a combination of
generic hardware and General Purpose special purpose hardware and embedded
Operating System for executing a variety of Operating System for executing a specific
applications. set of applications.
2. Contain a General Purpose Operating May or may not contain an operating
System (GPOS). system for functioning.
3. Applications are alterable (programmable) The firmware of the embedded system is
by user. (The end user can re-install the pre-programmed and it is non-alterable by
OS, and add or remove user applications). end-user.
4. Performance is the key deciding factor on Application specific requirements (like
the selection of the system. Always “Faster performance, power requirements,
is Better”. memory etc) are the key deciding factors.
5. Less/not at all tailored towards reduced Highly tailored to take advantage of the
operating power requirements, options for power saving modes supported by
different levels of power management. hardware and Operating System.
6. Response requirements are not time For certain category of ES, the response
critical. time requirement is highly critical.
7. Need not be deterministic in execution Execution behaviour is deterministic
behaviour. for few ES like “Hard Real Time‟ systems.

1
 I.RAVI KUMAR
Classification of Embedded Systems
The criteria used in the classification of embedded systems are:
1. Based on generation.
2. Complexity and performance requirements.
3. Based on deterministic behaviour.
4. Based on triggering.
1. Classification Based on Generation
 First Generation: The early embedded systems were built around 8-bit microprocessors
like 8085 and 280, and 4-bit microcontrollers. Simple in hardware circuits with
firmware developed in Assembly code. Eg: Digital telephone keypads, stepper motor
control units etc.
 Second Generation: Embedded systems built around 16-bit microprocessors and 8 or
16-bit microcontrollers. The instruction set became much more complex and powerful
than the first generation processors/controllers. Eg: Data Acquisition Systems, SCADA
systems etc.
 Third Generation: Embedded systems built around powerful 32-bit processors and 16-
bit microcontrollers. Application and domain specific processors /controllers like Digital
Signal Processors (DSP) and Application Specific Integrated Circuits (ASICs) came into
the picture. The instruction set is more complex and powerful. Eg: Robotics, media,
industrial process control, networking, etc.
 Fourth Generation: Embedded system built around System on Chips (SOC),
reconfigurable processors and multicore processors. The fourth generation embedded
systems are making use of high performance real time embedded operating systems for
their functioning. Eg: Smart phone devices, mobile internet devices (MIDs), etc.
2. Classification Based on Complexity and Performance
 Small-Scale Embedded Systems: Small-scale ES are usually built around low
performance and low cost 8 or 16 bit microprocessors / microcontrollers. These ES are
suitable for simple applications and where performance is not time critical. It may or
may not contain an operating system (OS) for functioning. Eg: Electronic toy.
 Medium-Scale Embedded Systems: Embedded systems built around medium
performance, low cost 16 or 32 bit microprocessors/microcontrollers or DSPs. These
embedded systems which are slightly complex in hardware and firmware (software)

2
 I.RAVI KUMAR
requirements. It usually contains an Embedded OS for functioning.
 Large-Scale Embedded Systems/Complex Systems: ES built around 32 or 64 bit
RISC processors/controllers or Reconfigurable System on Chip (RSC) or multi-core
processors and programmable logic devices. These embedded systems involve highly
complex hardware and firmware. They may contain multiple processors/controllers and
co-units/hardware accelerators. Complex embedded systems usually contain a high
performance Real Time Operating System (RTOS).
3. Classification based on deterministic system behaviour
It is applicable for Real Time systems. The application/task execution behaviour for an
embedded system can be either deterministic or non-deterministic. Classified into:
 Soft Real Time Systems: Missing a deadline may not be critical and can be tolerated to
a certain degree. Eg: ATM.
 Hard Real Time Systems: Missing any deadline may produce disastrous results
(financial, human loss of life, etc.). Eg: ABS, Air bags etc.
4. Classification based on triggering
Embedded Systems which are 'Reactive' in nature can be classified based on the trigger.
Reactive systems can be classified as event triggered or time triggered.
Major Application Areas of Embedded Systems
 Consumer Electronics: Camcorders, Cameras etc.
 Household Appliances: Television, Washing Machine, Fridge, Microwave Oven etc.
 Home Automation and Security Systems: Air conditioners, CCTVs, Fire alarms etc.
 Automotive Industry: Anti-lock Breaking Systems (ABS), Engine Control, Automatic
Navigation Systems etc.
 Telecom: Cellular Telephones, Telephone switches, Handset etc.
 Computer Peripherals: Printers, Scanners, Fax machines etc.
 Computer Networking Systems: Network Routers, Switches, Hubs, Firewalls etc.
 Health Care: Different Kinds of Scanners, EEG, ECG Machines etc.
 Measurement & Instrumentation: Digital multi meters, Digital CRO, Logic analyzers,
PLC systems etc.
 Banking & Retail: Automatic Teller Machines (ATM), Currency counters etc.
 Card Readers: Barcode, Smart Card Readers, Hand held Devices etc.
 Cloud Computing and Internet of Things (IoT).

3
 I.RAVI KUMAR
Purpose of Embedded Systems
Each Embedded Systems is designed to serve the purpose of any one or a combination of
the following tasks:
1. Data Collection/Storage/Representation
Embedded system designed for the purpose of data collection performs acquisition of data
from the external world. Data collection is usually done for storage, analysis, manipulation
and transmission. Data can be analog or digital.
Embedded systems with analog data capturing techniques collect data directly in the
form of analog signal whereas embedded systems with digital data collection mechanism
converts the analog signal to the digital signal using analog to digital converters. If the data
is digital it can be directly captured by digital embedded system.
A digital camera is a typical example of an embedded System with data
collection/storage/representation of data. Images are captured and the captured image
may be stored within the memory of the camera. The captured image can also be presented
to the user through a graphic LCD unit.
2. Data communication
Embedded data communication systems are deployed in applications from complex satellite
communication to simple home networking systems. The transmission of data is achieved
either by a wire-line medium or by a wire-less medium. USB, TCP/ IP, PS2 are examples of
wired communication and Bluetooth, ZigBee and Wi-Fi are examples for wireless
communication.
Data can either be transmitted by analog means or by digital means. Network hubs,
routers, switches are examples of dedicated data transmission embedded systems.
3. Data (Signal) Processing
Embedded systems with signal processing functionalities are employed in applications
demanding signal processing like speech coding, audio video codec, transmission
applications etc.
A digital hearing aid is a typical example of an embedded system employing data
processing.
4. Monitoring
All embedded products coming under the medical domain are with monitoring functions.
They are used for determining the state of some variables using input sensors.

4
 I.RAVI KUMAR
Electro cardiogram (ECG) machine is intended to do the monitoring of the heartbeat
of a patient but it cannot impose control over the heartbeat. Other examples with
monitoring function are digital CRO, digital multi-meters, and logic analyzers.
5. Control
Embedded systems with control functionalities are used for imposing control over some
variables according to the changes in input variables. A system with control functionality
contains both sensors and actuators.
Sensors are connected to the input port for capturing the changes in environmental
variable and the actuators connected to the output port are controlled according to the
changes in the input variable. Air conditioner system used to control the room temperature
to a specified limit is a typical example for control purpose.
6. Application Specific User Interface
These are the embedded systems that are designed for a specific application. Buttons,
switches, keypad, lights, bells, display units etc. are application specific user interfaces.
Mobile phone is an example of application specific user interface. In mobile phone the
user interface is provided through the keypad, system speaker, vibration alert etc.

5
 I.RAVI KUMAR

Characteristics of Embedded Systems

Embedded systems possess certain specific characteristics. These characteristics are
unique to each embedded system. Some of the important characteristics of an embedded
system are:
1. Application and domain specific
2. Reactive and Real Time
3. Operates in harsh environments
4. Distributed
5. Small size and weight
6. Power concerns
1. Application and domain specific
Each embedded system has certain functions to perform and they are developed in such a
manner to do the intended functions only. They cannot be used for any other purpose. For
example, the embedded control unit of a microwave oven cannot be replaced with an air
conditioner's embedded control unit, because the embedded control units of microwave
oven and air conditioner are specifically designed to perform certain specific tasks.
Similarly, an embedded control unit developed for a particular domain, say telecom,
cannot be replaced with another control unit designed to serve another domain like
consumer electronics.
2. Reactive and Real Time
Embedded systems are in constant interaction with the real world through sensors and
user defined input devices. Any changes happening in the Real world (which is called an
Event) are captured by the sensors or input devices in Real Time and the control algorithm
running inside the unit reacts in a designed manner to bring the controlled output
variables to the desired level.
Embedded systems produce changes in output in response to the changes in the
input. So they are generally referred as Reactive Systems.
Real Time System operation means the timing behaviour of the system should be
deterministic. The system should respond to requests or tasks in a known amount of time.

6
 I.RAVI KUMAR
A Real Time system should not miss any deadlines for tasks or operations.
Embedded applications or systems which are mission critical, like flight control
systems, Antilock Brake Systems (ABS), etc. are examples of Real Time systems.
3. Operates in harsh environments
The environment in which the embedded system deployed may be a dusty one or a high
temperature zone or an area subject to vibrations and shock. Systems placed in such areas
should be capable to withstand all these adverse operating conditions. The design should
take care of the operating conditions of the area where the system is going to implement.
For example, if the system needs to be deployed in a high temperature zone, then all
the components used in the system should be of high temperature grade. Power supply
fluctuations, corrosion and component aging, etc. are the other factors that need to be
taken into consideration for embedded systems to work in harsh environments.
4. Distributed
“Distributed” means that embedded systems may be a part of larger systems. Many
numbers of such distributed embedded systems form a single large embedded control unit.
For example, a car has many embedded systems controlled to its dash board. Each one is
an independent embedded system yet the entire car can be said to function properly only if
all the systems work together.
Another example is Automatic Teller Machine (ATM). It contains a card reader
embedded unit, responsible for reading and validating the user's ATM card, transaction
unit for performing transactions, a currency counter for dispatching/vending currency to
the authorized person and a printer unit for printing the transaction details.
5. Small size and weight
An embedded system that is compact in size and has light weight will be desirable or more
popular than one that is bulky and heavy. For example: Cell phones. The cell phones that
have the maximum features are popular but also their size and weight is an important
characteristic.
People believe in the phrase "Small is beautiful". Moreover, it is convenient to handle
a compact device than a bulky product. In embedded domain, compactness is a significant
deciding factor. Most of the application demands small sized and low weight products.
6. Power concerns
Power management is another important factor that needs to be considered in designing

7
 I.RAVI KUMAR
embedded systems. Embedded systems should be designed in such a way as to minimize
the heat dissipation by the system. The production of high amount of heat demands cooling
requirements like cooling fans which in turn occupies additional space and make the
system bulky. Also power management is a critical constraint in battery operated
application. The more the power consumption the less is the battery life.
Quality Attributes of Embedded Systems
Quality attributes are the non-functional requirements that need to be documented
properly in any system design. If the quality attributes are more concrete and measurable it
will give a positive impact on the system development process and the end product. The
quality attributes in any embedded system development are broadly classified into two:
 Operational Quality Attributes
 Non-Operational Quality Attributes
Operational Quality Attributes
The operational quality attributes represent the relevant quality attributes related to the
embedded system when it is in the operational mode or 'online' mode. The important
operational quality attributes are:
1. Response
2. Throughput
3. Reliability
4. Maintainability
5. Security
6. Safety
1. Response
Response is a measure of quickness of the system. It gives you an idea about how fast the
system is tracking the changes in input variables. Most of the embedded systems demand
fast response which should be almost Real Time. For example, an embedded system
deployed in flight control application should respond in a Real Time manner. Any response
delay, may cause potential damages to the safety of the flight as well as the passengers.
It is not necessary that all embedded systems should be Real Time in response. For
example, the response time requirement for an electronic toy is not at all time-critical.
There is no specific deadline that this system should respond within this particular
timeline.

8
 I.RAVI KUMAR
2. Throughput
Throughput deals with the efficiency of a system. Throughput can be defined as the rate of
production or operation of a defined process over a stated period of time. The rates can be
expressed in terms of units of products, batches produced, or any other meaningful
measurements. In the case of a Card Reader, throughput means how many transactions
the Reader can perform in a minute or in an hour or in a day.
Throughput is generally measured in terms of 'Benchmark’. A 'Benchmark' is a
reference point by which something can be measured. Benchmark can be a set of
performance criteria that a product is expected to meet or a standard product that can be
used for comparing other products of the same product line.
3. Reliability
Reliability is a measure of how much percentage you can rely upon the proper functioning
of the system or what is the percentage susceptibility of the system to failures. System
reliability is defined using two terms:
 Mean Time Between Failures (MTBF): It gives the frequency of failures in hours /weeks
/months.
 Mean Time To Repair (MTTR): Specifies how long the system is allowed to be out of order
following a failure. For an embedded system with critical application need, it should be
of the order of minutes.
4. Maintainability
Maintainability deals with support and maintenance to the end user or client in case of
technical issues and product failures or on the basis of a routine system check-up.
Reliability and maintainability are considered as two complementary disciplines. A more
reliable system means a system with less corrective maintainability requirements and vice
versa.
Maintainability can be broadly classified into two categories:
 Scheduled or Periodic Maintenance (preventive maintenance): For example, replacing the
cartridge of a printer after each 'n' number of printouts to get quality prints.
 Maintenance to unexpected failures (corrective maintenance): For example, repairing the
printer if the paper feeding part fails.
Maintainability is also an indication of the availability of the product for use. In any
embedded system design, the ideal value for availability is expressed as

9
 I.RAVI KUMAR
Ai = MTBF / (MTBF + MTTR) , where
Ai = Availability in the ideal condition, MTBF = Mean Time Between Failures & MTTR =
Mean Time To Repair.
5. Security
Three major measures of information security are: Confidentiality, Integrity & Availability.
Confidentiality deals with the protection of data and application from unauthorized
disclosure. Integrity deals with the protection of data and application from unauthorized
modification. Availability deals with protection of data and application from unauthorized
users.
Example of the 'Security' aspect in an embedded product is a Personal Digital
Assistant (PDA). If it is a shared one there should be some mechanism in the form of a user
name and password to access into a particular person's profile-this is an example of
'Availability’. Also, all data and applications present in the PDA need not be accessible to all
users. Some of them are specifically accessible to administrators only-an example of
Confidentiality. Some data present in the PDA may be visible to all users but there may not
be necessary permissions to alter the data by the users-an example of Integrity.
Non-Operational Quality Attributes
The quality attributes that needs to be addressed for the product 'not’ on the basis of
operational aspects are grouped under this category. The important non-operational quality
attributes are:
1. Testability & Debugability
2. Evolvability
3. Portability
4. Time-to-prototype and market
5. Per unit and total cost
1. Testability & Debugability
Testability deals with how easily one can test his/her design, application and by which
means he/she can test it. Testability is applicable to both the embedded hardware and
firmware. Embedded hardware testing ensures that the peripherals and the total hardware
functions in the desired manner. Firmware testing ensures that the firmware is functioning
in the expected way.
Debug-ability is a means of debugging the product as such for figuring out the

10
 I.RAVI KUMAR
probable sources that create unexpected behaviour in the total system. Debug-ability has
two aspects in the embedded system development context:
Hardware level debugging and firmware level debugging.
Hardware debugging is used for figuring out the issues created by hardware
problems. Firmware debugging is employed to figure out the probable errors that appear as
a result of flaws in the firmware.
2. Evolvability
Evolvability is a term which is closely related to Biology. Evolvability is referred as the non-
heritable variation. For an embedded system, the quality attribute 'Evolvability' refers to the
ease with which the embedded product (including firmware and hardware) can be modified
to take advantage of new firmware or hardware technologies.
3. Portability
Portability is measure of “system Independence”. An embedded product is said to be
portable if the product is capable of functioning 'as such' in various environments, target
processors/ controllers and embedded operating systems. A standard embedded product
should always be flexible and portable. In embedded products, 'porting' represents the
migration of the embedded firmware written for one target processor (i.e., Intel x86) to a
different target processor (say ARM Cortex M3 processor). If the firmware is written in a
high level language like ‘C’, it is very easy to port the firmware. If the firmware is written in
Assembly Language for a particular family of processor (say x86 family), then the portability
is poor.
4. Time-to-prototype and market
Time to market is the time elapsed between the conceptualization of a product and the time
at which the product is ready for selling (for commercial product) or use (for non-
commercial products). The commercial embedded product market is highly competitive and
time-to-market the product is a critical factor in the success of a commercial embedded
product. If a new design takes long time to develop and market it, then competitor might
release their product before you do and/or technology used might have superseded with a
new technology.
Product prototyping helps a lot in reducing time-to-market. Prototyping is an informal kind
of rapid product development in which the important features of the product under
consideration are developed. The time to prototype is also another critical factor. If the

11
 I.RAVI KUMAR
prototype is developed faster, the actual estimated development time can be brought down
significantly. In order to shorten the time to prototype, make use of all possible options like
the use of off-the-shelf components, re-usable assets, etc.
5. Per unit and total cost
Cost is a factor which is closely monitored by both end user (who buy the product) and
product manufacturer (who build the product). Cost is a highly sensitive factor for
commercial products. Any failure to position the cost of a commercial product at a nominal
rate, may lead to the failure of the product in the market. Proper market study and cost
benefit analysis should be carried out before taking a decision on the per-unit cost of the
embedded product. From a designer/ product development company perspective the
ultimate aim of a product is to generate marginal profit. So the budget and total system
cost should be properly balanced to provide a marginal profit.
The Product Life Cycle (PLC)
The product life cycle of every embedded product has different phases:
Design and Development Phase: The product idea generation, prototyping, Roadmap
definition, actual product design and development are the activities carried out during this
phase. There is only investment and no returns.
Product Introduction Phase: Once the product is ready to sell, it is introduced to the
market. During the initial period the sales and revenue will be low. There won't be much
competition and the product sales and revenue increases with time.
Growth Phase: The product grabs high market share.
Maturity Phase: Growth & sales will be steady and the revenue reaches at its peak.
Product Retirement/Decline Phase: Drop in sales volume, market share and revenue.
The decline happens due to various reasons like competition from similar product with
enhanced features or technology changes, etc. At some point of the decline stage, the
manufacturer announces discontinuing of the product.
The different stages of the embedded products life cycle are represented in the below
Product Life-cycle graph. From the graph, the total revenue increases from the product
introduction stage to the product maturity stage. The revenue peaks at the maturity stage
and starts falling in the decline/retirement Stage. The unit cost is very high during the
introductory stage. The profit increases with increase in sales and attains a steady value
and then falls with a dip in sales.

12
 I.RAVI KUMAR
Product Product Product Product
Growth
Development Introduction Maturity Retirement
Revenue

ales
S
u ct
rod
P
Unit Cost
t
Profi
0
Time

Application-Specific Embedded System Washing Machine

An embedded system contains sensors, actuators, control unit and application - specific
user interfaces like keyboards, display units, etc. All these components can be seen in a
washing machine. Some of them are visible and some of them may be invisible.
The major Parts of Washing Machine are:
Actuator part: consists of a motorized medium, heavy duty, etc.
agitator, tumble tub, water drawing pump User feedback is reflected through
and inlet valve to control the flow of water the display unit and LEDs connected to
into the unit. the control board.
Sensor part: consists of the water
temperature sensor, level sensor, etc. The
sensor data is fed back to the control unit
and the control unit generates the
necessary actuator outputs.
Control part: contains a
microprocessor/controller based board
with interfaces to the sensors and
actuators. The control unit also provides
connectivity to user interfaces like keypad
for setting the washing time, selecting the
type of material to be washed like light,
13
 I.RAVI KUMAR
Washing machine comes in two models: Top loading & Front loading machines.
First phase of washing: The agitator of the machine twists back and forth and pulls the
cloth down to the bottom of the tub. On reaching the bottom of the tub the clothes work
their way back up to the top of the tub where the agitator grabs them again and repeats the
mechanism.
Second phase of washing: Water is pumped out from the tub and the inner tub uses
centrifugal force to wring out more water from the clothes by spinning at several hundred
Rotations Per Minute (RPM). This is called a 'Spin Phase’.
The inner tub of the machine contains a number of holes and during the spin cycle
the inner tub spins, and forces the water out through these holes to the stationary outer
tub from which it is drained off through the outlet pipe.
The basic controls consist of a timer, cycle selector mechanism, water temperature
selector, load size selector and start button. The integrated control panel consists of a
microprocessor / controller based board with I/O interfaces and a control algorithm
running in it.
Domain Specific Embedded System- Automotive
Automotive industry is one of the major application domains of embedded systems.
Automotive embedded systems are the one where electronics take control over the
mechanical system. Ex. Simple viper control. Presence of automotive embedded system in a
vehicle varies from simple mirror and wiper controls to complex air bag controller and
antilock brake systems (ABS).

14
 I.RAVI KUMAR
Automotive embedded systems are normally built around microcontrollers or DSPs or
a hybrid of the two and are generally known as Electronic Control Units (ECUs). The
number of embedded controllers in an ordinary vehicle varies from 20 to 40 whereas a
luxury vehicle like Mercedes S and BMW 7 may contain 75 to 100 numbers of embedded
controllers.
The electronic control units (ECUs) used in the automotive embedded industry can be
broadly classified into two:
High-speed Electronic Control Units (HECUs): These are deployed in critical control units
requiring fast response. They include fuel injection systems, antilock brake systems, engine
control, electronic throttle, steering controls, transmission control and central control unit.
Low-speed Electronic Control Units (LECUs): These are deployed in applications where
response time is not so critical. They generally are built around low cost microprocessors
/microcontrollers and digital signal processors. Audio controllers, passenger and driver
door locks, door glass controls (power windows), wiper control, mirror control, seat control
systems, head lamp controls, sun roof control unit etc. are examples of LECUs.
Serial Interface Buses in Automotive Applications
Automotive applications make use of serial buses for communication, which greatly
reduces the amount of wiring required inside a vehicle. Different types of serial interface
buses are:
 Controller Area Network (CAN) Bus
 Local Interconnect Network (LIN) Bus
 Media-Oriented System Transport (MOST) Bus
Controller Area Network (CAN) Bus: CAN Bus was originally proposed by Robert Bosch. It
supports medium speed (ISO11519-class B with data rates up to 125 Kbps) and high speed
(IS011898 class C with data rates up to 1 Mbps) data transfer. CAN is an event-driven
protocol interface with support for error handling in data transmission. It is generally
employed in safety system like airbag control; power train systems like engine control and
Antilock Brake System (ABS); and navigation systems like GPS.
Local Interconnect Network (LIN) Bus:
LIN bus is a single master multiple slave (up to 16 independent slave nodes)
communication interface. LIN is a low speed, single wire communication interface with
support for data rates up to 20 Kbps and is used for sensor/actuator interfacing. LIN bus

15
 I.RAVI KUMAR
follows the master communication triggering technique to eliminate the possible bus
arbitration problem that can occur by the simultaneous talking of different slave nodes
connected to a single interface bus. LIN bus is employed in applications like mirror
controls, fan controls, seat positioning controls, window controls, and position controls
where response time is not a critical issue.
Media-Oriented System Transport (MOST) Bus: MOST is targeted for automotive audio/
video equipment interfacing, used primarily in European cars. MOST bus is a multimedia
fiber-optic, point-to-point network implemented in a star, ring or daisy-chained topology
over optical fiber cables. MOST bus specifications define the physical (electrical and optical
parameters) layer as well as the application layer, network layer, and media access control.
MOST bus is an optical fiber cable connected between the Electrical Optical Converter
(EOC) and Optical Electrical Converter (OEC), which would translate into the optical cable
MOST bus.
Key Players of the Automotive Embedded Market
The key players of the automotive embedded market can be visualized in three verticals
namely: Silicon providers, Tools & Platform providers and Solution providers.
Silicon Providers: They are responsible for providing the necessary chips which are used
in the control application development. Chip may be a standard product like
microcontroller or DSP or ADC/DAC chips. Some applications may require specific chips
and they are manufactured as Application Specific Integrated Chip (ASIC).
The leading silicon providers in the automotive industry are Analog Devices, Xilinx,
Atmel, Maxim/Dallas, NXP Semiconductors, Texas Instruments, Fujitsu, NEC, etc.
Tools and Platform Providers: They are manufacturers and suppliers of various kinds of
development tools and Real Time Embedded Operating Systems for developing and
debugging different control unit related applications.
Some of the leading suppliers of tools and platforms in automotive embedded
applications are ENEA, The MathWorks, MATLAB, Keil Software, ARTiSAN, Microsoft, etc.
Solution Providers: They supply Original Equipment Manufacturer (OEM) and complete
solution for automotive applications making use of the chips, platforms and different
development tools.
The major players of this domain Bosch Automotive, DENSO Automotive, Infosys
Technologies, Delphi, etc.

16
 I.RAVI KUMAR
INTRODUCTION TO EMBEDDED SYSTEMS

Unit-II:
The Typical Embedded System:
Core of the Embedded System, Memory, Sensors and Actuators, Communication Interface, Embedded
Firmware, Other System components.

Elements of Embedded Systems

An embedded system is a combination of 3 things: Hardware, Software, Mechanical
Components and it is supposed to do one specific task only. A typical embedded system
contains a single chip controller which acts as the master brain of the system.
Diagrammatically an embedded system can be represented as shown in figure 3.1.
Embedded systems are designed to regulate a physical variable or to manipulate the
state of some devices by sending signals to the actuators or devices connected to the output
system, in response to the input signal provided by the end users or sensors which are
connected to the input ports. Hence the embedded systems can be viewed as a reactive
system.
Keyboards, push button, switches, etc. are examples of input devices and LEDs, LCDs,
Piezoelectric buzzers, etc. are examples for output devices for a typical ES.
Some embedded system can automatically sense input parameters from real world
through sensors. Sensor information is passed to the processor after signal conditioning
and digitization. The core of the system performs some predefined operations on input data
with the help of embedded firmware and sends some actuating signals to the actuator.

1
 I.RAVI KUMAR

The memory of the system is responsible for holding the code. There are two types: Fixed
memory (ROM) is used for storing code or program. The user cannot do any modifications
in this type of memory. Common types used are OTP, PROM, EPROM, EEPROM & Flash
memory. Temporary memory (RAM) is used for performing arithmetic operations or control
algorithm executions. Common types used are SRAM, DRAM and NVRAM.
Memory for implementing the code may be present on the processor or may be
implemented as a separate chip interfacing the processor. In a controller based embedded
system, the controller may contain internal memory for storing code and such controllers
are called Micro-controllers with on-chip ROM, eg. Atmel AT89C51.
Core of the Embedded System
The core of the embedded system falls into any one of the following categories:
1. General Purpose and Domain Specific Processors:
o Microprocessors
o Microcontrollers
o Digital Signal Processors
2. Programmable Logic Devices (PLDs)
3. Application Specific Integrated Circuits (ASICs)
4. Commercial off-the-shelf Components (COTS)
2
 I.RAVI KUMAR
1. General Purpose and Domain Specific Processors
Almost 80% of the embedded systems are processor/ controller based. The processor may
be microprocessor or a microcontroller or digital signal processor, depending on the domain
and application.
Microprocessor: A silicon chip representing a Central Processing Unit(CPU), which is
capable of performing arithmetic as well as logical operations according to a pre-defined set
of instructions. In general, the CPU contains the Arithmetic and Logic Unit (ALU), control
unit and working registers.
Microcontroller: A microcontroller is a highly integrated chip that contains a CPU,
RAM, Special and General purpose Register Arrays, On Chip ROM/FLASH memory for
program storage, Timer and Interrupt control units and dedicated I/O ports. Since a
microcontroller contains all the necessary functional blocks for independent working, they
found greater place in the embedded domain in place of microprocessors.
The differences between a Microprocessor and Microcontroller is given in below table:
No. Microprocessors Microcontrollers
1. It is a dependent unit. It requires the It is a self-contained unit & doesn’t
combination of other chips like Timers, require external Interrupt Controller,
Program and data memory chips, Timer, and UART etc. for its functioning.
Interrupt controllers etc. for functioning.

2. Most of the time general purpose in Mostly application oriented or domain

design and operation. specific.
3. Doesn’t contain a built in I/O port. Most of the processors contain multiple
built-in I/O ports.
4. Targeted for high end market where Targeted for embedded market where
performance is important. performance is not so critical.
5. Limited power saving options. Includes lot of power saving features
6.

3
 I.RAVI KUMAR
Digital Signal Processor (DSP)
DSP’s are powerful special purpose 8/16/32 bit microprocessor designed to meet the
computational demands and power constraints of today’s embedded audio, video and
communication applications. DSP are 2 to 3 times faster than general purpose
microprocessors in signal processing applications. This is because of the architectural
difference between DSP and general purpose microprocessors. DSPs implement algorithms
in hardware which speeds up the execution whereas general purpose processor implement
the algorithm in software and the speed of execution depends primarily on the clock for the
processors.
A typical digital signal processor incorporates the following four key units:
1. Program Memory: Memory for storing the program required by DSP to process the data.
2. Data Memory: Working memory for storing temporary variables and data/ signal to be
processed.
3. Computational Engine: Performs the signal processing in accordance with the stored
program memory. Computational Engine incorporates many specialized arithmetic units
and each of them operates simultaneously to increase the execution speed.
4. I/O Unit: Input/Output unit acts as an interface between the outside world and DSP. It
is responsible for capturing signals to be processed and delivering the processed signals.
Audio video signal processing, telecommunication and multimedia applications are
typical examples where DSP is employed. Digital signal processing employs a large amount
of real-time calculations. Sum of Products (SOP) calculation, Convolution, Fast Fourier
Transform (FFT), Discrete Fourier Transform (DFT), etc., are some of the operations
performed by digital signal processors.
RISC V/s CISC Processors/Controllers
The term RISC stands for Reduced Instruction Set Computing. All RISC processors/
controllers possess lesser number of instructions, typically in the range of 30 to 40.
CISC stands for Complex instruction Set Computing. The instruction set of CISC is
complex and instructions are high in number.
From a programmers point of view RISC processors are comfortable, since he/she
needs to learn only a few instructions, whereas CISC processor needs to learn more
number of instructions and should understand the context of usage of each instruction.
The major differences between RISC and CICS controllers are given in below table:

4
 I.RAVI KUMAR
No. RISC Processors/Controllers CISC Processors/Controllers
1. Lesser no. of instructions. Greater no. of Instructions.
2. Instruction Pipelining and increased Generally no instruction pipelining
execution speed. feature.
3. Orthogonal Instruction Set. Non Orthogonal Instruction Set.
4. Operations are performed on registers Operations are performed on registers
only, memory operations are load & store. or memory depending on the instruction
5. Large number of registers are available Limited no. of general purpose registers
6. Programmer needs to write more code to A programmer can achieve the desired
execute a task since the instructions are functionality with a single instruction.
simpler ones.

7. Single, Fixed length Instructions. Variable length Instructions.

8. Less Silicon usage and pin count. More silicon usage.
9. With Harvard Architecture Harvard or Von-Neumann Architecture

Big-Endian vs. Little-Endian Processors/Controllers

Endianness specifies the order in which the data is stored in the memory by processor
operations in a multi byte system. Suppose the word length is two byte then data can be
stored in memory in two different ways:
 Higher order of data byte at the higher memory and lower order of data byte at location
just below the higher memory – Little-Endian. E.g.: Intel x86 Processors
 Lower order of data byte at the higher memory and higher order of data byte at location
just below the higher memory – Big-Endian E.g.: Motorola 68000 Series Processors
Little-endian means the lower-order
byte of the data is stored in memory at the
lowest address, and the higher-order byte
at the highest address (The little end
comes first). For example, a 4 byte long
integer Byte3 Byte2 Byte1 Byte0 will be
stored in the memory as shown:

5
 I.RAVI KUMAR
Big-endian means the higher-order
byte of the data is stored in memory at the
lowest address, and the lower-order byte
at the highest address. (The big end comes
first.) For example, a 4 byte long integer
Byte3 Byte2 Byte1 Byte0 will be stored in
the memory as shown:
2. Programmable Logic Devices (PLDs)
Logic devices are classified into two broad categories - Fixed and Programmable.
 The circuits in a fixed logic device are permanent, they perform one function or set of
functions. Once manufactured, they cannot be changed.
 Programmable logic devices (PLDs) offer customers a wide range of logic capacity,
features, speed, and voltage characteristics. These devices can be re-configured to
perform any number of functions at any time.
Designers can use inexpensive software tools to quickly develop, simulate, and test
their logic designs in PLD based design. The design can be quickly programmed into a
device, and immediately tested in a live circuit. PLDs are based on re-writable memory
technology and the device is reprogrammed to change the design.
Two major types of programmable logic devices are FPGA & CPLD.
 Field Programmable Gate Arrays (FPGAs): FPGAs offer the highest amount of logic
density, the most features, and the highest performance. FPGAs are used in a wide
variety of applications ranging from data processing and storage, to instrumentation,
telecommunications, and digital signal processing
 Complex Programmable Logic Devices (CPLDs): CPLDs, by contrast, offer much
smaller amounts of logic - up to about 10,000 gates. CPLDs offer very predictable timing
characteristics and are therefore ideal for critical control applications
Advantages of PLDs:
1. PLDs offer customer much more flexibility during the design cycle.
2. PLDs do not require long lead times for prototypes or production parts because PLDs are
already on a distributor’s shelf and ready for shipment.
3. PLDs can be reprogrammed even after a piece of equipment is shipped to a customer.
4. PLDs allow customers to order just the number of parts they need.

6
 I.RAVI KUMAR
3. Application Specific Integrated Circuit (ASIC)
ASIC is a microchip designed to perform a specific or unique application. It integrates
several functions into a single chip and thereby reduces the system development cost.
Most of the ASICs are proprietary products. ASIC consumes very small area in the total
system and thereby helps the design of smaller systems with high
capabilities/functionalities.
ASICs can be pre-fabricated for a special application or it can be custom fabricated
by using the components from a re-usable “building block‟ library of components for a
particular customer application. Fabrication of ASICs requires a non-refundable initial
investment (Non-Recurring Engineering (NRE) charges) for the process technology &
configuration expenses.
If NRE is born by a third party and the ASIC is made openly available in the market,
the ASIC is referred as Application Specific Standard Product (ASSP).
4. Commercial off the Shelf Component (COTS)
Commercial off the Shelf product is one which is used 'as-is'. COTS components itself may
be developed around a general purpose or domain specific processor or a ASICs or a PLDs.
Typical examples of COTS hardware unit are remote controlled toy car control units.
Advantage of using COTS is that they are readily available in the market, are cheap
and a developer can cut down his/her development time to a great extent.
Major drawback of using COTS components in embedded design is that the
manufacturer of the COTS component may withdraw the product or discontinue the
production of the COTS at any time if rapid change in technology occurs.
Sensors and Actuators
A sensor is a special kind of transducer that is used to generate an input signal to a
measurement, instrumentation or control system. The signal produced by a sensor is an
electrical analogy of a physical quantity, such as distance, velocity, acceleration,
temperature, pressure, light level, etc. Sensor acts as an input device.
Actuator is a form of transducer device (mechanical or electrical) which converts
signals to corresponding physical action (motion). Actuator acts as an output device.
The I/O Subsystem
The I/O subsystem of embedded system facilitates the interaction of embedded system with
the external world. Various I/O devices used in embedded system applications are:

7
 I.RAVI KUMAR
Light emitted Diode (LED)
LED is an output device for visual used in series between the power supply
indication in any embedded system. Used and the resistor to limit the current
as an indicator for the status of various through the LED. The ideal LED
signals or situations. interfacing circuit is shown.
LED is a p-n junction diode and it
contains an anode & a cathode. For proper
functioning of the LED, the anode of it
should be connected to +ve terminal of the
supply voltage and cathode to the –ve
terminal of supply voltage. A resister is
There are two ways to interface an LED to a microprocessor/microcontroller:
1. The Anode of LED is connected to the port pin and cathode to Ground: In this approach
the port pin sources the current to the LED when it is at logic High (i.e. 1).2. The Cathode
of LED is connected to the port pin and Anode to Vcc: In this approach the port pin sources
the current to the LED when it is at logic Low (i.e. 0).
7-Segment LED Display
The 7 – segment LED display is an output device for displaying alpha numeric characters &
contains 8 LED segments arranged in a special form. Out of the 8 LED segments, 7 are
used for displaying alpha numeric characters. LED segments are named A to G and the
decimal point LED segment is named as DP.
The 7 – segment LED displays are available in two different configurations:
 Common anode configuration: Anodes of 8 segments are connected commonly.
 Common cathode configuration: 8 LED segments share a common cathode line.
Figure 3.4 shows the common anode & cathode configurations of a 7 segment LED.
The current flow through each of the LED segments should be limited to the maximum
value supported by the LED display unit by connecting a current limiting resistor.
Anode Common Cathode LED Display
DP G F E D C B A

DP G F E D C B A
Common Anode LED Display Cathode

8
 I.RAVI KUMAR
Stepper Motor
Stepper motor is an electro mechanical device which generates discrete displacement
(motion) in response to dc electrical signals. It differs from the normal dc motor in its
operation. The dc motor produces continuous rotation on applying dc voltage whereas a
stepper motor produces discrete rotation in response to the dc voltage applied to it. Stepper
motors are widely used in industrial embedded applications, consumer electronic products
and robotics control systems. Eg: Paper feed mechanism of printer/fax makes use of
stepper motor for its functioning.
Based on the coil winding arrangements, a two phase stepper motor is classified into:
 Unipolar: A unipolar stepper motor the terminals to which the coils are
contains two windings per phase. The connected. Figure shows a two phase
direction of rotation (clockwise or unipolar stepper motor.
anticlockwise) of a stepper motor is
controlled by changing the direction of
current flow. Current in one direction
flows through one coil and in the
opposite direction flows through the
other coil. It is easy to shift the
direction of rotation by just switching
 Bipolar: A bipolar stepper motor contains single winding per phase. For reversing the
motor rotation the current flow through the windings is reversed dynamically. It requires
complex circuitry for current flow reversal.
The stepping of stepper motor can be implemented in different ways by changing the
sequence of activation of the stator windings. The different stepping modes supported by
stepper motor are explained below:
 Full Step: In the full step mode both the phases are energized simultaneously. The coils
A, B, C and D are energized in the order, as shown in the Table.
 Wave Step: In the wave step mode, only one phase is energized at a time and each coils
of the phase is energized alternatively. The A, B, C and D are energized in the order, as
shown in the Table.
 Half Step: It uses the combination of wave and full step. It has the highest torque and
stability. The coil energizing sequence for half step is given in the Table below.

9
 I.RAVI KUMAR
Full Step Wave Step Half Step

Coil Coil Coil Coil Coil Coil Coil Coil Coil Coil Coil Coil
Step Step
A B C D A B C D A B C D

1 H L L L
1 H H L L H L L L
2 H H L L
3 L H L L
2 L H H L L H L L
4 L H H L
5 L L H L
3 L L H H L L H L
6 L L H H
7 L L L H
4 H L L H L L L H
8 H L L H

Two-phase unipolar stepper motors are the popular choice for embedded
applications. The current requirement for stepper motor is little high and hence the port
pins of a microcontroller/ processor may not be able to drive the motor directly. Special
driving circuits are required to interface the stepper motor with microcontrollers. ULN2803
is an octal peripheral driver array available for driving a 5V stepper motor.
The following circuit diagram illustrates the interfacing of a stepper motor through a
driver circuit connected to the port pins of a microcontroller/ processor.

Port Pins A
M

Driver IC C
Microcontroller
ULN2803 B D

Vcc
GND Vcc

10
 I.RAVI KUMAR
Optocoupler
Optocoupler is a solid state device to Optocouplers can be used in either input
isolate two parts of a circuit. Optocoupler circuits or in output circuits.
combines an LED and a photo-transistor
in a single housing (package). Figure
shows of an optocoupler device.
In electronic circuits, an optocoupler
is used for suppressing interference in
data communication, circuit isolation,
high voltage separation, simultaneous
separation and signal intensification, etc.
Figure illustrates the usage of optocoupler in input circuit and output circuit of an
embedded system with a microcontroller as the system core.

Vcc

LED AT89C51 LED

I/p interface Port Pin
O/p interface
Port Pin
Photo-transistor Photo-transistor

Opto-Coupler Microcontroller Opto-Coupler

IC MCT2M IC MCT2M
Relay
A relay is an electro mechanical device which acts as dynamic path selectors for signals
and power. The ‘Relay’ unit contains a relay coil made up of insulated wire on a metal core
and an armature with one or more contacts.
’Relay’ works on electromagnet principle. When a voltage is applied to the relay coil,
current flows through the coil, which in turn generates a magnetic field. The magnetic field
attracts the armature core and moves the contact point. The movement of the contact point
changes the power/signal flow path.
Figure below shows widely used relay configurations for embedded applications.
11
 I.RAVI KUMAR

Relay Coil
Relay Coil

Relay Coil
Single Pole Single Single Pole Single Single Pole Double
Throw Normally Throw Normally Throw
Open Closed

The Single Pole Single Throw configuration has only one path for information flow.
The path is either open or closed in normal condition.
 For normally open Single Pole Single Throw relay, the circuit is normally open and it
becomes closed when the relay is energized.
 For normally closed Single Pole Single Throw configuration, the circuit is normally
closed and it becomes open when the relay is energized.
For Single Pole Double Throw Relay, there are two paths for information flow and
they are selected by energizing or de-energizing the relay. The Relay is normally controlled
using a relay driver circuit connected to the port pin of the processor/ controller. A
transistor is used for building the relay driver circuit. The following Figure illustrates the
same.

Vcc
Freewheeling Diode

Relay Coil

Load
Port Pin

Relay Unit

Piezo Buzzer
It is a piezoelectric device for generating audio indications in embedded applications. A
Piezo buzzer contains a piezoelectric diaphragm which produces audible sound in response
to the voltage applied to it.
Piezoelectric buzzers are available in two types: ‘Self-driving’ and ‘External driving’
12
 I.RAVI KUMAR
 Self-driving circuits contains all the necessary components to generate sound at a
predefined tone. It will generate a tone on applying the voltage.
 External driving Piezo Buzzers supports the generation of different tones. The tone can
be varied by applying a variable pulse train to the piezoelectric buzzer.
Push button switch
Push Button switch is an input device. is kept in the pushed state and it
This switch comes in two configurations, breaks/makes the circuit connection when
namely: “Push to Make” and “Push to it is released. Push button is used for
Break”. The switch is normally in the open generating a momentary pulse. In
state and it makes a circuit contact when it embedded application push button is used
is pushed or pressed in the “Push to as reset, start switch & pulse generator.
Make” configuration. In the “Push to
Break” configuration, the switch is
normally in the closed state & it breaks
the circuit contact when it is pushed or
pressed. The push button stays in the
“closed” (For Push to Make type) or “open‟
(For Push to Break type) state as long as it 
Depending on the way in which the push button interfaced to the controller, it can
generate either a 'HIGH' pulse or a 'LOW' pulse. Figure Illustrates how the push button can
be used for generating 'LOW' and 'HIGH' pulses.
Keyboard
Keyboard is an input device for user interface. If the number of keys required is very less,
push button switches can be used. If a large number of keys are required, then Matrix
keyboard is used. Figure illustrates the connection of keys in a matrix keyboard.
In a matrix keyboard, the keys are arranged in matrix fashion. For detecting a key press,
each row of the matrix is pulled low & the columns are read. After reading the status of
each columns corresponding to a row, the row is pulled high and the next row is pulled low
and the status of the columns are read. This process is repeated until the scanning for all
rows are completed. When a row is pulled low and if a key connected to the row is pressed,
reading the column to which the key is connected will give logic 0. Pull-up resistors are
connected to the column lines to limit the current that flows to the row line on a key press.
13
 I.RAVI KUMAR
Vcc

4.7K

4.7K
4.7K

4.7K
Row 0
To Microcontroller/processor Port

Row 1

Row 2

Row 3

Column 1
Column 0

Column 3
Column 2
To Microcontroller/processor Port

Communication Interface
Communication interface is essential for communicating with various subsystems of the
embedded system and with the external world. The communication interface can be viewed
in two different perspectives; namely;
 Device/board level communication interface (Onboard Communication Interface):
The communication channel which interconnects the various components within an
embedded product is referred as Device/board level communication interface.
Eg: Serial interfaces like I2C, SPI, UART, 1-Wire etc. and Parallel bus interface
 Product level communication interface (External Communication Interface): The
Product level communication interface is responsible for data transfer between the
embedded system and other devices or modules. The external communication interface
can be either wired media or wireless media and it can be a serial or parallel interface.
Eg: Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi), Radio Frequency waves (RF),
GPRS etc. (wireless) and RS-232, USB, Parallel port etc. (wired).
Onboard Communication Interfaces:
1. Inter Integrated Circuit (I2C) Bus
Inter Integrated Circuit Bus (I2C) is a synchronous bidirectional half duplex (one-
directional communication at a given point of time) two wire serial interface bus. The I2C
bus comprise of two bus lines:
 Serial Clock (SCL line): Responsible for generating synchronization clock pulses.
 Serial Data (SDA Line): Responsible for transmitting the serial data across devices.
14
 I.RAVI KUMAR
I2C bus is a shared bus system to which many number of I2C devices can be
connected. Devices connected to I2C bus can act as either 'Master' device or 'Slave' device.
'Master' device is responsible for controlling the communication by initiating/ terminating
data transfer, sending data and generating necessary synchronization clock pulses. Slave'
devices wait for the commands from the master and respond upon receiving the commands.
Synchronization clock signal is generated by the ‘Master’ device only.
Figure below shows bus interface diagram, which illustrates the connection of master
and slave devices on the I2C bus.

The sequence of operations for communicating with an I2C slave device is listed below:
1. The master device pulls the clock line (SCL) of the bus to 'HIGH '
2. The master device pulls the data line (SDA) 'LOW', when the SCL line is at logic 'HIGH'
(This is the 'Start' condition for data transfer).
3. The master device sends the address of the 'slave' device to which it wants to
communicate, over the SDA line. Clock pulses are generated at the SCL line for
synchronizing the bit reception by the slave device.
4. The master device sends the Read or Write bit according to the requirement.
5. The master device waits for the acknowledgement bit from the slave device whose
address is sent on the bus along with the Read/ Write operation command.
6. The slave device with the address requested by the master device responds by sending
an acknowledge bit over the SDA line

15
 I.RAVI KUMAR
7. Upon receiving the acknowledge bit, the master device sends the 8-bit data to the slave
device over SDA line, if the requested operation is 'Write to device'. If the requested
operation is 'Read from device', the slave device sends data to the master over the SDA line.
8. The master device waits for the acknowledgement bit from the device upon byte transfer
complete for a write operation and sends an acknowledge bit to the Slave device for a read
operation.
9. The master device terminates the transfer by pulling the SDA line ‘HIGH' when the clock
line SCL is at logic 'HIGH' (Indicating the 'STOP' condition).
2. Serial Peripheral Interface (SPI) Bus
SPI is asynchronous bi-directional full duplex four-wire serial interface bus. It is a single
master multi-slave system. SPI requires four signal lines for communication. They are:
 Master Out Slave In (MOSI): Signal line carrying the data from master to slave device.
It is also known as Slave Input/Slave Data In (SI/SDI).
 Master In Slave Out (MISO): Signal line carrying the data from slave to master device.
It is also known as Slave Output / Slave Data Out (SO/ SDO).
 Serial Clock (SCL): Signal line carrying the clock signals.
 Slave Select (SS): Signal line for slave device select. It is an active low signal.
The bus interface diagram is shown in below figure, illustrates the connection of master
and slave devices on the SPI bus.

MOSI SCL MISO

MISO
SCL
MOSI MOSI Slave 1
SCL SPI Device
Master
MISO (Eg: Serial
(Microprocessor/
SS\ EEPROM)
Controller)
SS1\
SS2\
MOSI
Slave 2
SCL
SPI Device
MISO
(Eg: LCD)
SS\

SPI Bus

16
 I.RAVI KUMAR
The master device is responsible for generating the clock signal. It selects the
required slave device by asserting the corresponding slave device's slave select signal 'LOW'.
SPI works on the principle of 'Shift Register'. The master and slave devices contain a
special shift register for the data to transmit or receive. During transmission from the
master to slave, the data in the master's shift register is shifted out to the MOSI pin and it
enters the shift register of the slave device through the MOSI pin of the slave device. At the
same time, the shifted out data bit from the slave device's shift register enters the shift
register of the master device through MISO pin.
3. Universal Asynchronous Receiver Transmitter (UART)
UART based data transmission is an asynchronous form of serial data transmission. It
doesn't require a clock signal to synchronize the transmitting end and receiving end for
transmission. Instead it relies upon the pre-defined agreement between the transmitting
device and receiving device. Serial communication settings for both transmitter & receiver
should be set as identical. Start & stop of communication is indicated through inserting
special bits in data stream
The 'start' bit informs the receiver that a data byte is about to arrive. The receiver device
starts polling it’s 'receive line'. The UART of the receiving device calculates the parity of the
bits received and compares it with the received parity bit for error checking. The UART of
the receiving device discards the 'Start', 'Stop' and 'Parity' bit from the received bit stream
and converts the received serial bit data to a word.
For proper communication, the Transmit line (TX) of the sending device should be
connected to the Receive line (RX) of the receiving device as shown below.

4. 1-Wire Interface
1-wire interface is an asynchronous half-duplex communication protocol. It makes use of only
a single signal line (wire) called DQ for communication and follows the master-slave
communication model.

17
 I.RAVI KUMAR
One of the key feature of 1-wire bus is that it allows power to be sent along the signal
wire as well. The 1-wire slave devices incorporate internal capacitor to power the device
from the signal line. The 1-wire interface supports a single master and one or more slave
devices on the bus. The bus interface diagram is shown below.
Vcc

4.7K

DQ Slave 1
Port Pin
1-Wire Device
(Eg: DS2760 Battery
GND
monitor IC )
Master
(Microprocessor/
Controller) DQ Slave 2
1-Wire Device
(Eg: DS2431 1024
GND GND
Bit EEPROM )

Every 1-wire device contains a globally unique 64-bit identification number stored
within it. The identifier has three parts: an 8-bit family code, a 48-bit serial number and an
8-bit CRC computed from the first 56-bits.
The sequence of operation for communicating with a 1-wire slave device are:
1. The master device sends a 'Reset' pulse on the 1-wire bus.
2. The slave device(s) present on the bus respond with a 'Presence' pulse.
3. The master device sends a ROM command. This addresses the slave device(s) to which it
wants to initiate a communication.
4. The master device sends a read/ write function command to read/ write the internal
memory or register of the slave device.
5. The master initiates a Read data/ Write data from the device or to the device.
All communication over the 1-wire bus is master initiated.
5. Parallel Interface
The host processor/controller of the embedded system contains a parallel bus and the
device which supports parallel bus can directly connect to this bus system. The
communication through the parallel bus is controlled by the control signal interface
between the device and the host. The control signals are read or write signals and device
select signals. The device becomes active by selecting host processor.

18
 I.RAVI KUMAR
Direction of data transfer is controlled through control signal lines for ‘read’ and ‘write’.
An address decoder circuit is used for generating chip select signal for the device. When the
address selected is in the range, chip select line is activated by decoder circuit. If device
wants to start communication, it can inform the same to processor through interrupts. The
width of the parallel interface is determined by the data bus width of the host processor
(4bit, 8bit, 16bit, 32bit or 64bit).Parallel data communication offers highest speed for data
transfer. Figure below illustrates the interfacing of devices through parallel interface.

External Communication Interfaces

1. RS-232 C
RS-232 C (Recommended Standard number 232, revision C) is a legacy, full duplex, wired,
asynchronous serial communication interface developed by the Electronics Industries
Association (EIA). It was used for connections to modems, printers, uninterruptible power
supplies, and other peripheral devices.
RS-232 supports only point-to-point communication. It supports data rates up to
20Kbps with a maximum operating distance support of 50 feet. The RS-232 interface
defines various handshaking and control signals for communication apart from the
'Transmit' and 'Receive' signal lines for data communication. RS-232 supports two different
types of connectors: DB-9: 9-Pin connector and DB-25: 25-Pin connector.

1 13
1 5

6 9 14 25
DB-25
DB-9

19
 I.RAVI KUMAR
2. Universal Serial Bus (USB)
USB is a wired high speed serial bus for
data communication. The USB
communication system follows a star Peripheral
topology with a USB host at the centre Device 2
and one or more USB peripheral
devices/USB hosts connected to it.
Physical connection between a USB Peripheral
Peripheral USB Host
peripheral device and master device is Device 3
Device 1 (Hub)
established with a USB cable. USB cable
supports communication distance of up to
5 meters. A USB host can support
connections up to 127 devices. USB USB Host
transmits data in packet format. Each
(Hub)
data packet has a standard format. Figure
illustrates the star topology for USB device Peripheral Peripheral
connection. Device 4 Device 5
USB host contains a host controller responsible for controlling the data
communication. The USB standard uses two different types of connectors namely:
 Type A’ connector: used for upstream
connection (connection with host).
 ‘Type B’ connector: used for
downstream connection (connection
with slave device)
Both Type A and Type B connectors
contain 4 pins for communication. (Table)
Each USB device contains a Product ID (PID) and a Vendor ID (VID). The PID and VID
are embedded into the USB chip by the USB device manufacturer. The VID for a device is
supplied by the USB standards forum.
USB supports four different types of data transfers:
 Control transfer is used by USB system software to query, configure and issue
commands to the USB device

20
 I.RAVI KUMAR
 Bulk transfer is used for sending a block of data to a device. Bulk transfer supports
error checking and correction. Transferring data to a printer is an example.
 Isochronous data transfer is used for real time data communication. In Isochronous
transfer, data is transmitted as streams in real time. All streaming devices like audio,
video make use of isochronous transfer.
 Interrupt transfer is used for transferring small amount of data. Interrupt transfer
mechanism makes use of polling technique to see whether the USB device has any data
to send. Devices like Mouse, Keyboard make use of interrupt transfer.
USB supports four data transfers: Low Speed (USB 1.0: 1.5 Mbps), Full Speed (USB
1.1: 12 Mbps), High Speed (USB 2.0: 480 Mbps) & Super Speed (USB 3.0: 4.8 Gbps).
3. IEEE 1394 (Firewire)
IEEE 1394 is a wired, isochronous high speed serial communication bus. It is also known
as High Performance Serial Bus (HPSB). IEEE 1394 supports peer-to-peer connection and
point-to-multipoint communication allowing 63 devices to be connected on the bus in a tree
topology. It is a wired serial interface and can support a cable length of up to 15 feet for
interconnection. The 1394 standard supports a data rate of 400 to 3200 Mbits/second.
The IEEE 1394 uses differential data transfer which increases the noise immunity.
The interface cable supports 3 types of connectors, namely; 4-pin connector, 6-pin
connector (alpha connector) and 9 pin connector (beta connector). IEEE 1394 is a popular
communication interface for connecting embedded devices like Digital Camera, Camcorder,
Scanners to desktop computers for data transfer and storage.
4. Infrared (IrDA)
IrDA serial, half duplex, line of sight based wireless technology for data communication
between devices. Infrared communication technique makes use of Infrared waves of the
electromagnetic spectrum for transmitting the data. IrDA supports point-point and point-
to-multipoint communication, provided all devices involved in the communication are
within the line of sight. The typical communication range for IrDA lies in the range 10cm to
1 m.IR supports data rates ranging from 9600bits/second to 16MbpsSIR supports
transmission rates ranging from 9600bps to 115.2kbps.
IrDA communication involves a transmitter unit for transmitting the data over IR and
a receiver for receiving the data. Infrared Light Emitting Diode (LED) is used as the IR
source for transmitter and at the receiving end a photodiode is used as the receiver.

21
 I.RAVI KUMAR
5. Bluetooth
BT is a low cost, low power, short range wireless technology for data & voice
communication. Bluetooth operates at 2.4GHz of the Radio Frequency spectrum and uses
the Frequency Hopping Spread Spectrum (FHSS) technique for communication. Bluetooth
supports a data rate of up to 1Mbps to 24Mbps and a range of approximately 30 to 100 feet
for data communication. Bluetooth communication has two essential parts; a physical link
part and a protocol part. The physical link is responsible for the physical transmission of
data between devices supporting Bluetooth communication and protocol part is responsible
for defining the rules of communication.
Bluetooth enabled devices contain a Bluetooth wireless radio for the transmission
and reception of data. Each Bluetooth device will have a 48 bit unique identification
number. Bluetooth communication follows packet based data transfer. Bluetooth supports
point-to-point (device to device) and point-to-multipoint (device to multiple device
broadcasting) wireless communication. A Bluetooth device can function as either master or
slave. A network formed with one Bluetooth device as master and more than one device as
slaves is known as Piconet.
Bluetooth technology is very popular among cell phone users as they are the easiest
communication channel for transferring ringtones, music files, pictures, media files, etc.
6. Wireless Fidelity (Wi-Fi)
Wi-Fi is a wireless communication the intended devices on the network. Wi-Fi
technique for networked communication of enabled devices contain a wireless adaptor
devices. Wi-Fi follows the IEEE 802.11 for transmitting and receiving data in the
standard. Wi-Fi is intended for network form of radio signals through an antenna.
communication and it supports Internet Wi-Fi operates at 2.4GHZ or 5GHZ of radio
Protocol (IP) based communication. Wi-Fi spectrum.
based communications require an
intermediate agent called Wi-Fi router
/Wireless Access point to manage the
communications. The Wi-Fi router is
responsible for restricting the access to a
network, assigning IP address to devices
on the network, routing data packets to

22
 I.RAVI KUMAR
For communicating, the device when its Wi-Fi radio is turned ON, searches the
available Wi-Fi network in its vicinity and lists out the Service Set Identifier (SSID) of the
available networks. If the network is security enabled, a password may be required to
connect to a particular SSID. Wi-Fi supports data rates ranging from 1Mbps to 150Mbps
depending on the standards (802.11a/b/g/n). Depending on the type of antenna and usage
location (indoor/outdoor), Wi-Fi offers a range of 100 to 300 feet.
7. ZigBee
ZigBee is a low power, low cost, wireless network communication protocol based on the
IEEE 802.15.4-2006 standard. ZigBee is targeted for low power, low data rate and secure
applications for Wireless Personal Area Networking (WPAN). The ZigBee specifications
support a robust mesh network containing multiple nodes. ZigBee operates worldwide at
the unlicensed bands of Radio spectrum, mainly at 2.400 to 2.484 GHz and supports an
operating distance of up to 100 meters and a data rate of 20 to 250Kbps.
In the ZigBee terminology, each ZigBee device falls under any one of the following
ZigBee device category:
ZigBee Coordinator (ZC) / Network ZED ZED
Coordinator: It acts as the root of the
ZigBee network. The ZC is responsible for ZED
initiating the ZigBee network and it has
ZR
the capability to store information about ZR ZC

the network
ZED
ZigBee Router (ZR) / Full function ZED

Device (FFD): Responsible for passing ZigBee is primarily targeting

information from device to another device application areas like Home & Industrial
or to another ZR Automation, Energy Management, Home
ZigBee End Device (ZED) /Reduced control/security, and sensor networks &
Function Device (RFD): End device active RFID.
containing ZigBee functionality for data Automatic Meter Reading (AMR),
communication. It can talk only with a ZR smoke and detectors, heating control,
or ZC and doesn’t have the capability to lighting controls, environmental controls
act as a mediator for transferring data etc. are examples for applications which
from one device to another. can make use of the ZigBee technology.

23
 I.RAVI KUMAR
8. General Packet Radio Service (GPRS)
GPRS is a communication technique for transferring data over a mobile communication
network like GSM. Data is sent as packets in GPRS communication. The transmitting
device splits the data into several related packets. At the receiving end the data is re-
constructed by combining the received data packets.
GPRS supports a maximum transfer rate of 171.2kbps. In GPRS communication, the
radio channel is concurrently shared between several users instead of dedicating a radio
channel to a cell phone user. The GPRS communication divides the channel into 8
timeslots and transmits data over the available channel. GPRS supports Internet Protocol
(IP), Point to Point Protocol (PPP) and X.25 protocols for communication. GPRS is mainly
used by mobile enabled embedded devices for data communication. GPRS is an old
technology and it is being replaced by new generation data communication techniques
(EDGE).
Embedded Firmware
Embedded firmware refers to the control algorithm (Programs/Instructions) and/or the
configuration settings that an embedded system developer dumps into the code (Program)
memory of the embedded system. Various methods available for developing the embedded
firmware are:
1. Write the program in high level languages like Embedded C/C++ using an Integrated
Development Environment (IDE).
 The IDE will contain an editor, compiler, linker, debugger, simulator, etc.
 IDE’s are different for different family of processors/controllers.
2. Write the program in Assembly language using the instructions supported by your
application's target processor/controller.
Program written in high level language or assembly code should be converted into a
processor understandable machine code before loading it into the program memory.
The process of converting the program written in either a high level language or
processor/controller specific Assembly code to machine readable binary code is called 'HEX
File Creation’. (Machine Language)
For beginners, High Level Language (HLL) is recommended, because:
1. Writing codes in a high level language is easy.
2. HLLs are not developer dependent: Any skilled programmer can trace out the

24
 I.RAVI KUMAR
functionalities of the program by just having a look at the program.
3. HLL is highly portable: You can use the same code to run on different processor/
controller with little or less modification.
Other System Components
The other system components refer to the components/circuits/ICs which are necessary for
the proper functioning of the embedded system. Some of these circuits may be essential for
the proper functioning of the processor/controller and firmware execution.
1. Reset Circuit
The reset circuit is essential to ensure that the device is not operating at a voltage level
where the device is not guaranteed to operate, during system power ON. The reset signal
brings the internal registers and the different hardware systems of the processor/ controller
to a known state and starts the firmware execution from the reset vector. (Normally from
vector address 0x0000 for conventional processors/controllers)
The reset signal can be either active high (Processor undergoes reset when the reset
pin of the processor is at logic high) or active low (Processor undergoes reset when the reset
pin of the processor is at logic low). The reset signal to the processor can be applied at
power ON through an external passive reset circuit comprising a Capacitor and Resistor or
through a standard Reset IC like MAX810.

Some microprocessors /controllers contain built-in internal reset circuitry and they
don't require external reset circuitry. Figure illustrates a resistor capacitor based passive
reset circuit for active high and low configurations. The reset pulse width can be adjusted
by changing the resistance value R and capacitance value C.
2. Brown-out Protection Circuit
Brown-out protection circuit prevents the processor/ controller from unexpected program
execution behavior when the supply voltage to the processor/ controller falls below a
25
 I.RAVI KUMAR
specified voltage. It is essential for battery powered devices since there are greater chances
for the battery voltage to drop below the required threshold. A brown-out protection circuit
holds the processor/ controller in reset state, when operating voltage falls below the
threshold, until it rises above the threshold voltage.
Figure illustrates a brown-out for Vcc. The values of Rl, R2, and R3 can
circuit implementation using Zener diode be selected based on the electrical
and transistor for processor/ controller characteristics of the transistor in use.
with active low Reset logic. The Zener
Vcc
diode, Dz, and transistor, Q, forms the
R1
heart of this circuit. The transistor
conducts always when the supply voltage V BE
R2
Vcc is greater than that of the sum of VBE Q
and Vz (Zener voltage). The transistor Reset Pulse
stops conducting when the supply voltage DZ Active Low

Vz
falls below the sum of VBE and Vz. R3

Select the Zener diode with required

GND
voltage for setting the low threshold value
3. Oscillator Unit
A microprocessor/ microcontroller is a digital device and its instruction execution occurs in
synchronization with a clock signal. The oscillator unit of the embedded system is
responsible for generating the precise clock for the processor. Certain processors/
controllers integrate a built-in oscillator unit and simply require an external ceramic
resonator/ quartz crystal for producing the necessary clock signals. Certain devices may
not contain a built-in oscillator unit and require the clock pulses to be generated and
supplied externally. Quartz crystal Oscillators are available in the form of chips and they
can be used for generating the clock pulses in such cases.

Microcontroller Microprocessor
C : Capacitor
Y : Resonator

Crystal Oscillator
Oscillator
Unit
Quartz Crystal Clock Input Pin
Resonator C C
Y Oscillator
Unit

26
 I.RAVI KUMAR
The speed of operation of a processor is primarily dependent on the clock frequency.
The total system power consumption is directly proportional to the clock frequency. The
power consumption increases with increase in clock frequency. The accuracy of program
execution depends on the accuracy of the clock signal.
4. Real Time Clock
RTC is a system component responsible for keeping track of time. RTC holds information
like current time (In hours, minutes and seconds) in 12 hours/24 hour format, date,
month, year, day of the week, etc. and supplies timing reference to the system. RTC is
intended to function even in the absence of power.
RTCs are available in the form of Integrated Circuits from different semiconductor
manufacturers like Maxim/Dallas, ST Microelectronics etc. RTC chip contains a microchip
for holding the time and date related information and backup battery cell for functioning in
the absence of power, in a single IC package. RTC chip is interfaced to the processor or
controller of the embedded system. For Operating System based embedded devices, a
timing reference is essential for synchronizing the operations of the OS kernel.
5. Watchdog Timer
A watchdog timer, is a hardware timer for monitoring the firmware execution and resetting
the processor/microcontroller when the program execution hangs up. A watchdog timer
increments or decrements a free running counter with each clock pulse and generates a
reset signal to reset the processor if the count reaches zero for a down counting watchdog,
or the highest count value for an up counting watchdog. If the firmware execution doesn't
complete due to malfunctioning, within the time required by the watchdog to reach the
maximum count, the counter will generate a reset pulse and this will reset the processor. If
the firmware execution completes before the expiration of the watchdog timer you can reset
the count by writing a 0 (for an up counting watchdog timer) to the watchdog timer register.
Most of the processors implement watchdog as a built-in component and provides
status register to control the watchdog timer and watchdog timer register for writing the
count value. If the processor/controller doesn't contain a built-in watchdog timer, the same
can be implemented using an external watchdog timer IC circuit.
In modern systems running on embedded operating systems, the watchdog can be
implemented in such a way that when a watchdog timeout occurs, an interrupt is
generated instead of resetting the processor.

27
 I.RAVI KUMAR
Figure illustrates the implementation of an external watchdog timer based
microprocessor supervisor circuit for a small scale embedded system.

Microoprocessor/
Controller
Watchdog
Free Running
Reset Pin
Counter

Watchdog Reset

System Clock

28
 I.RAVI KUMAR
INTRODUCTION TO EMBEDDED SYSTEMS

Unit-III : Embedded Firmware Design and Development: Embedded Firmware

Design Approaches, Embedded Firmware Development Languages, Programming in Embedded C.

EMBEDDED FIRMWARE DESIGN AND DEVELOPMENT

The embedded firmware is responsible for controlling the various peripherals of the
embedded hardware and generating response in accordance with the functional
requirements. Firmware is considered as the master brain of the embedded system. For
most of the embedded products, the firmware is stored at a permanent memory (ROM) and
they are non-alterable by end users.
Embedded firmware development process starts with conversion of the firmware
requirements into a program model using modelling tools. Once the program model is
created, the next step is the implementation of the tasks and actions by capturing the
model using a language which is understandable by the target processor/controller.
The firmware design approaches for embedded product is purely dependent on the
complexity of the functions to be performed, the speed of operation required, etc. Two basic
approaches are used for embedded firmware design are:
 Super Loop Based Approach (Conventional Procedural Based Design)
 Embedded Operating System (OS) Based Approach
Super Loop Based Approach
This approach is adopted for applications that are not time critical & where the response
time is not so important. This approach is similar to a conventional procedural
programming where the code is executed task by task. The task listed at the top of the
program code is executed first and the tasks just below the top are executed after
completing the first task.
In a multiple task based system, each task is executed in serial in this approach. The
firmware execution flow for this will be:
1. Configure the common parameters and perform initialization for various hardware
components memory, registers, etc.
2. Start the first task and execute it
3. Execute the second task
4. Execute the next task

1
 I.RAVI KUMAR
5. :
6. :
7. Execute the last defined task
8. Jump back to the first task and follow the same flow
The order in which the tasks to be
executed are fixed & they are hard coded
in the code itself. Also the operation is an
infinite loop based approach. We can
visualize the operational sequence listed
above in terms of a ‘C’ program code as
shown:
Almost all tasks in embedded applications are non-ending and are repeated infinitely
throughout the operation. This repetition is achieved by using an infinite loop. Hence this
approach is called as 'Super loop based approach’. The only way to come out of the loop is
either a hardware reset or an interrupt assertion.
Advantage of Super Loop Based Approach:
 It doesn't require an operating system.
 There is no need for scheduling which task is to be executed and assigning priority to
each task.
 The priorities are fixed and the order in which the tasks to be executed are also fixed.
 The code for performing these tasks will be residing in the code memory without an
operating system image.
Applications & Examples of Super Loop Based Approach:
This type of design is deployed in low-cost embedded products and products where
response time is not time critical. Some embedded products demands this type of approach
if some tasks itself are sequential. For example, reading/writing data to and from a card
using a card reader requires a sequence of operations
A typical example of a 'Super loop based’ product is an electronic video game toy
containing keypad and display unit.
Drawbacks of Super Loop Based Approach:
 Any failure in any part of a single task will affect the total system: If the program
hangs up at some point while executing a task, it will remain there forever and

2
 I.RAVI KUMAR
ultimately the product stops functioning. Watch Dog Timers (WDTs) can be used to
overcome this.
 Lack of real timeliness: If the number of tasks to be executed within an application
increases, the time at which each task is repeated also increases. This brings the
probability of missing out some events.
Embedded Operating System (OS) Based Approach
The operating system based approach contains operating systems, which can be either a
General Purpose Operating System (GPOS) or a Real Time Operating System (RTOS) to host
the user written application firmware.
The GPOS based design is similar to a conventional PC based application
development where the device contains an operating system and you will be creating and
running user applications on top of it. Example of a GPOS is Microsoft Windows XP
Embedded. Examples of Embedded products using Microsoft Windows XP OS are Personal
Digital Assistants (PDAs), Hand held devices/Portable devices. OS based applications also
require 'Driver software' for different hardware present on the board to communicate with
them.
Real Time Operating System (RTOS) based design approach is employed in embedded
products demanding Real-time response. RTOS responds in a timely and predictable
manner to events. RTOS contains a Real Time kernel responsible for performing pre-
emptive multitasking, scheduler for scheduling tasks, multiple threads, etc. A RTOS allows
flexible scheduling of system resources like the CPU and memory and offers some way to
communicate between tasks. 'Windows CE', 'pSOS', 'ThreadX', 'MicroC/OS-II’, 'Embedded
Linux', 'Symbian’, etc. are examples of RTOS employed in embedded product development.
Mobile phones, handheld devices, etc. are examples of 'Embedded Products' based on
RTOS.
Embedded Firmware Development Languages
For embedded firmware development, we can use either:
 a target processor/controller specific language (Generally known as Assembly
language or low level language) or
 a target processor/controller independent language (Like C, C++, JAVA, etc.
commonly known as High Level Language) or
 a combination of Assembly and High level Language.

3
 I.RAVI KUMAR
Assembly Language Based Development
Assembly language is human readable notation of 'machine language’, whereas ‘Machine
Language' is a processor understandable language. Machine Language is a binary
representation and it consists of 1s and 0s. Machine Language is made readable by using
specific symbols called ’mnemonics’. Machine Language can be considered as interface
between processor & programmer.
Assembly language and Machine Languages are processor/controller dependent and
an assembly program written for one processor/controller family will not work with others.
Assembly language programming is the task of writing processor specific machine code in
mnemonic form, converting the mnemonics into actual processor instructions (Machine
Language) and data using an assembler.
The general format of an assembly language instruction is an Opcode followed by
Operands. The Opcode tells the processor/ controller what to do and the Operands provide
the data and information required to perform the action specified by the opcode.
Example: MOV A, #30 // Here MOV A is the Opcode and 30 is the operand.
Assembly language instructions are written one per line. Each line of an assembly
language program is split into four fields as given below:
LABEL OPCODE OPERANDS COMMENT
LABEL is an optional field. A 'LABEL' is an identifier used extensively in programs to reduce
the reliance on programmers or remembering where data or code is located.
The sample code given below using 8051 Assembly language illustrates the
structured assembly language programming.
DELAY: MOV R0, #255 ; Load Register R0 with 255.
DJNE R0, DELAY ; Decrement R0 and loop till R0 = 0.
RET ; Return to calling program.
The Assembly program contains a main routine and it may or may not contain
subroutines. The example given above is a subroutine, which can be invoked by a main
program by the assembly instruction: LCALL DELAY. Executing this instruction transfers
the program flow to the memory address referenced by the 'LCALL DELAY'.
The Assembly language program written in assembly code is saved as .asm (Assembly
file) file or an .src (source) file. Any text editor like 'notepad' or 'WordPad' or the text editor
of an Integrated Development (IDE) tool can be used for writing the assembly instructions.

4
 I.RAVI KUMAR
When a program is too complex or too big; the entire code can be divided into sub-
modules and each module can be re-usable. This concept is called as Modular
Programming. Modular programs are usually easy to code, debug and alter.
Source File to Object File Translation
Translation of assembly code to machine code is performed by assembler. The assemblers
for different target machines are different. A51 Macro Assembler from Keil software is a
popular assembler for the 8051 family microcontroller. Various steps involved in the
conversion of a program written in assembly language to corresponding binary file/machine
language are shown below:

Each source module is written in Assembly and is stored as .src file or .asm file. Each
file can be assembled separately to examine the syntax errors and incorrect assembly
instructions. On successful assembling of each .src/.asm file a corresponding object file is
created with extension '.obj’. The object file does not contain the absolute address of where
the generated code needs to be placed on the program memory and hence it is called a re-
locatable segment. It can be placed at any code memory location and it is the
responsibility of the linker/locater to assign absolute address for this module.

5
 I.RAVI KUMAR
Library File Creation and Usage: Libraries are specially formatted, ordered program
collections of object modules that may be used by the linker at a later time. When the
linker processes a library, only those object modules in the library that are necessary to
create the program are used. Library files are generated with extension '.lib'. LIB51' from
Keil Software is an example for a library creator and it is used for creating library files for
A51 Assembler/ C51 Compiler for 8051 specific controller.
Linker and Locater: Linker and Locater is a software utility responsible for "linking the
various object modules in a multi-module project and assigning absolute address to each
module". Linker is a program which combines the target program with the code of other
programs (modules) and library routines. During the process of linking, the absolute
object module is created.
An absolute object file or module does not contain any re-locatable code or data. All
code and data reside at fixed memory locations. The absolute object file is used for creating
hex files for dumping into the code memory of the processor/ controller. BL51' from Keil
Software is an example for a Linker & Locater for A51 Assembler/ C51 Compiler for 8051
specific controller.
Object to Hex File Converter: This is the final stage in the conversion of Assembly
language (mnemonics) to machine understandable language (machine code). Hex File is the
representation of the machine code and the hex file is dumped into the code memory of the
processor/controller. The hex file representation varies depending on the target
processor/controller make.
HEX files are ASCII files that contain a hexadecimal representation of target
application. Hex file is created from the final 'Absolute Object File' using the Object to Hex
File Converter utility. 'OH51' from Keil software is an example for Object to Hex File
Converter utility for A51 Assembler/C51 Compiler for 8051 specific controller.
Advantages of Assembly Language Base Development:
 Efficient Code Memory and Data Memory Usage (Memory Optimization): Since
the developer is well versed with the target processor architecture and memory
organization, optimized code can be written for performing operations. This leads to
less utilization of code memory and efficient utilization of data memory.
 High Performance: Optimized code not only improves the code memory usage but
also improves the total system performance. Through effective assembly coding,

6
 I.RAVI KUMAR
optimum performance can be achieved for a target application.
 Low Level Hardware Access: Most of the code for low level programming like
accessing external device specific registers from the operating system kernel, device
drivers, and low level interrupt routines, etc. are making use of direct assembly
coding since low level device specific operation support is not commonly available
with most of the high-level language cross compilers.
 Code Reverse Engineering: Reverse engineering is the process of understanding the
technology behind a product by extracting the information from a finished product.
Reverse engineering is performed by 'hawkers' to reveal the technology behind
'Proprietary Products’.
Drawbacks of Assembly Language Based Development:
 High Development Time: Assembly language is much harder to program than high
level languages. The developer must have thorough knowledge of the architecture,
memory organization and register details of the target processor in use. Learning the
inner details of the processor and its assembly instructions is highly time consuming
and it creates a delay impact in product development.
 Developer Dependency: Unlike high level languages, there is no common written
rule for developing assembly language based applications. In assembly language
programming, the developers have the freedom to choose the different memory
location and registers. Also the programming approach varies from developer to
developer depending on his/ her taste.
 Non-Portable: Target applications written in assembly instructions are valid only for
that particular family of processors and cannot be re-used for another target
processors/ controllers. If the target processor/ controller changes, a complete re-
writing of the application using the assembly instructions for the new target
processor/ controller is required.
High Level Language (HLL) Based Development
Any high level language (like C, C++ or Java) with a supported cross compiler for the target
processor can be used for embedded firmware development. Commonly used HLL for
embedded firmware application development is 'C’. ‘C’ is well defined, easy to use HLL with
extensive cross platform development tool support. Nowadays embedded developers are
making use of cross-compilers of C++ for embedded application development.

7
 I.RAVI KUMAR
The various steps involved in high level language based embedded firmware
development is same as that of assembly language based development except that the
conversion of source file written in high level language to object file is done by a cross-
compiler. The various steps involved in the conversion of a program written in high level
language to corresponding binary file/machine language is illustrated in below figure:

The program written in any of the high level language is saved with the corresponding
language extension (.c for C, .cpp for C++ etc). Any text editor like 'notepad' or 'WordPad '
from Microsoft® or the text editor provided by an Integrated Development (IDE) tool
supporting the high level language can be used for writing the program. Most of the HLLs
support modular programming approach and hence can have multiple source files called
modules. Translation of high level source code to executable object code is done by a cross-
compiler. Cross-compilers for different HLLs for same target processor are different. C51 is
a popular Cross-compiler available for 'C' language for the 8051 family of micro controller.
Conversion of each module's source code to corresponding object file is performed by the
cross compiler. Rest of the steps are same as that of the steps involved in assembly
language based development.

8
 I.RAVI KUMAR
Advantages of High Level Language Based Development:
 Reduced Development Time: Developer requires less or little knowledge on the
internal hardware details and architecture of the target processor/ controller. Bare
minimal knowledge of the memory organization and register details of the target
processor in use and syntax of the HLL are the only pre-requisites for HLL based
firmware development.
With HLL, each task can be accomplished by lesser number of lines of code
compared to the target processor/ controller specific Assembly language based
development.
 Developer Independency: The syntax used by most of the HLLs are universal and a
program written in the high level language can easily be understood by a second
person knowing the syntax of the language.
 Portability: Target applications written in HLLs are converted to target processor /
controller understandable format (machine codes) by cross-compiler.
An application written in HLL for a particular target processor can easily be
converted to another target processor/ controller specific application, with no/little
modification.
Limitations of High Level Language Based Development
 Poor Optimization by Cross-Compilers: Some cross-compilers available for high
level languages may not be so efficient in generating optimized target processor
specific instructions.
 Not Suitable for Low Level Hardware: HLL based code may not be efficient in
accessing low level hardware where hardware access timing is critical (of the order of
nano or micro seconds).
 High Investment Cost: The investment required for HLL based development tools
(Integrated Development Environment incorporating cross-compiler) is high
compared to Assembly Language based firmware development tools.

9
 I.RAVI KUMAR
Embedded ‘C’ Programming
Definition: An embedded system is an application that contains at least one programmable computer
(typically in the form of a microcontroller, a microprocessor or digital signal processor chip) and which
is used by individuals who are, in the main, unaware that the system is computer-based.

Introduction to Embedded C
Looking around, we find ourselves to be surrounded by various types of embedded systems. Be
it a digital camera or a mobile phone or a washing machine, all of them has some kind of processor
functioning inside it. Associated with each processor is the embedded software. If hardware forms the
body of an embedded system, embedded processor acts as the brain, and embedded software forms its
soul. It is the embedded software which primarily governs the functioning of embedded systems.
During infancy years of microprocessor based systems, programs were developed using
assemblers and fused into the EPROMs. There used to be no mechanism to find what the program was
doing. LEDs, switches, etc. were used to check correct execution of the program. Some ‘very fortunate’
developers had In-circuit Simulators (ICEs), but they were too costly and were not quite reliable as
well.

As time progressed, use of microprocessor-specific assembly-only as the programming

language reduced and embedded systems moved onto C as the embedded programming language of
choice. C is the most widely used programming language for embedded processors/controllers.
Assembly is also used but mainly to implement those portions of the code where very high timing
accuracy, code size efficiency, etc. are prime requirements.

Advantages of C:
Use of C in embedded systems is driven by following advantages.
• It is small and reasonably simpler to learn, understand, program and debug. C Compilers are
available for almost all embedded devices in use today, and there is a large pool of experienced
C programmers.
• Unlike assembly, C has advantage of processor-independence and is not specific to any
particular microprocessor/ microcontroller or any system. This makes it convenient for a user
to develop programs that can run on most of the systems.
• As C combines functionality of assembly language and features of high level languages, C is
treated as a ‘middle-level computer language’ or ‘high level assembly language’. C language is
fairly efficient and supports access to I/O and provides ease of management of large embedded
projects.
• Well proven compilers are available for every embedded processor (8-bit to 32-bit).

• C x 51 Cross Compiler supports all of the ANSI Standard C directives.

 I.RAVI KUMAR
C Versus Embedded ‘C’

C Language Embedded ‘C’

‘C’ is a well structured, well defined and Embedded ‘C’ can be considered as a subset of ‘C’
standardized general purpose programming language.
language.

‘C’ is used for desktop computers Embedded ‘C’ is for microcontroller based
applications

‘C’ has the luxury to use resources of a desktop Embedded ‘C’ has to use with the limited resources
PC like memory, OS, etc. on desktop systems (RAM, ROM, I/Os) on an embedded processor

Compilers for ‘C’ (ANSI C) typically generate Embedded ‘C’ requires compilers (Cross Compilers)
OS dependant executables to create files to be downloaded to the
microcontrollers / microprocessors where it needs to
run

Compilers Vs Cross Compiler

Compiler is a software tool that converts a source code written in a high level language to machine
code. Generally compilers are used for desktop applications.

A cross compiler is a compiler capable of creating executable code for a platform other than the one on
which the compiler is run. Cross compiler tools are generally found in use to generate compiles for
embedded system

Storage Classes

A storage class decides scope, visibility and lifetime of a variable. ‘C’ supports the following storage
classes.
– Auto (automatic variables)
– Extern (external variables)
– Static (static variables)
– Register (register variables)

Auto: A variable declared inside a function without any storage class specification, is by default
an Auto (automatic) variable. They are created when a function is called and are
 I.RAVI KUMAR
destroyed automatically when the function exits. Automatic variables can also be called local variables
because they are local to a function. By default they are assigned garbage value by the compiler.

Extern (External or Global variable): A variable that is declared outside of any function is a Global
variable. Global variables remain available throughout the program. One important thing to remember
about global variable is that their values can be changed by any function in the program.
The extern keyword is used before a variable to inform the compiler that this variable is declared
somewhere else. The extern declaration does not allocate storage for variables.

Static: A static variable tells the compiler to persist the variable until the end of program. Instead of
creating and destroying a variable every time when it comes into and goes out of scope. Static is
initialized only once and remains into existence till the end of program. Static variables are assigned ‘0’
(zero) as default value by the compiler.

Register variable inform the compiler to store the variable in register instead of memory.
Register variable has faster access than normal variable. Frequently used variables are kept in register.
Only few variables can be placed inside register. Note that we can never get the address of such
variables.

Data Types
There are various type of Data types in C :

• unsigned char
• signed char
• unsigned int
• signed int
• sbit (single bit)
• bit and sfr

unsigned char:

The character data type is the most natural choice. 8051 is an 8-bit microcontroller and unsigned char
is also an 8-bit data type in the range of 0 –255 (00 –FFH).C compilers use the signed char as the
default data types if we do not put the keyword unsigned char.
We always use unsigned char in program until and unless we don’t need to represent signed numbers
for example Temperature.
signed char :

The signed char is an 8-bit data type. signed char use the MSB D7 to represent –or +. signed char give
us values from –128 to +127.
 I.RAVI KUMAR
Unsigned int :

• The unsigned int is a 16-bit data type.

• Takes a value in the range of 0 to 65535 (0000 –FFFFH)
• Define 16-bit variables such as memory addresses
• Set counter values of more than 256
• Since registers and memory accesses are in 8-bit chunks, the misuse of int variables will result
in a larger hex file.

Signed int:

• Signed int is a 16-bit data type.

• use the MSB D15 to represent –or +.
• We have 15 bits for the magnitude of the number from –32768 to +32767.

Bit :

• The bit data type allows access to single bits of bit-addressable memory spaces 20 –2FH

sfr :

• To access the byte-size SFR registers, we use the sfr data type.

Embedded C Programs

1. An embedded C program to load a number into Accumulator.

# include <reg51.h>
void main( )
{
Acc = 0x25;
}

2. Write a program to load three numbers into Accumulator and send them to port 1

# include <reg51.h>
void main( )
{
Acc = 0x25;
P1 = Acc;
Acc = 0x46;
P1 = Acc;
Acc = 0x92;
P1 = Acc;
}
 I.RAVI KUMAR
3. Write an 8051 C program to toggle all the bits of P1 continuously.

//Toggle P1 forever
#include <reg51.h>
void main( )
{
for ( ; ; )
{
P1=0 x 55;
P1=0 x AA;
}
}

4. Write an 8051 C program to send values 00 – FF to port P1.

#include <reg51.h>
void main( )
{
unsigned char z;
for (z = 0; z <= 255; z++)
P1=z;
}

5. Write an 8051 C program to send hex values for ASCII characters of 0, 1, 2, 3, 4, 5, 6, 7, 8,

9, A, B, C, D and E to port P1.

#include <reg51.h>
void main(void)
{
unsigned char mynum[ ] = “0123456789ABCDE”;
unsigned char z;
for (z = 0; z <= 15; z++)
P1 = mynum[z];
}
 I.RAVI KUMAR
6. Write an 8051 C program to toggle bits of P1 ports continuously with a 250 ms.

#include <reg51.h>
void MSDelay(unsigned int); //delay routine definition
void main( )
{
while (1) //repeat forever
{
P1= 0x55;
MSDelay(250);
P1= 0xAA;
MSDelay(250);
}
}

// delay routine implimentation

void MSDelay(unsigned int itime)
{
unsigned int i, j;
for (i = 0; i < itime; i++)
for (j = 0; j< 1275; j++);
}
 I.RAVI KUMAR
INTRODUCTION TO EMBEDDED SYSTEMS

Unit-IV : Real-time Operating System (RTOS) based Embedded System Design:

Operating System basics, Types of Operating Systems, Tasks, Process and Threads,
Multiprocessing and Multitasking, Task Scheduling Device Drivers, How to choose an RTOS.
OPERATING SYSTEM BASICS
Operating System (OS) acts as a bridge between the user applications/ tasks and the
underlying system resources through a set of system functionalities and services. Operating
system manages the system resources and makes them available to the user
applications/tasks on a need basis.
The primary functions of operating systems are:
 Make the system convenient to use
 Organize and manage the system resources efficiently and correctly.
Figure below gives an insight into the basic components of an operating system and their
interfaces with rest of the world.

Kernel: The kernel is the core of the operating system. It is responsible for managing the
system resources and the communication among the hardware and other system services.
Kernel acts as the abstraction layer between system resources and user applications.
Kernel contains a set of system libraries and services. For a general purpose OS, the kernel
contains different services like:
 Process management
 Memory management
 Time management
 File system management
 I/O system management.
1
 I.RAVI KUMAR
1. Process management: Process management deals with managing the process/ tasks.
Process management includes:
 setting up a memory for the process
 loading process code into memory
 allocating system resources
 scheduling and managing the execution of the process
 setting up and managing Process Control Block (PCB)
 inter process communication and synchronization
 process termination/ deletion, etc.
2. Primary Memory Management: Primary memory refers to a volatile memory (RAM),
where processes are loaded and variables & shared data are stored. The Memory
Management Unit (MMU) of the kernel is responsible for:
 Keeping a track of which part of the memory area is currently used by which process.
 Allocating and De-allocating memory space on a need basis.
3. File System Management: File is a collection of related information. A file could be a
program (source code or executable), text files, image files, word documents, audio/ video
files, etc. A file system management service of kernel is responsible for:
 The creation, deletion and alteration of files
 Creation, deletion, and alteration of directories
 Saving of files in the secondary storage memory
 Providing automatic allocation of file space based on the amount of free running
space available
 Providing flexible naming conversion for the files.
4. I/O System (Device) Management: Kernel is responsible for routing the I/O requests
coming from different user applications to the appropriate I/O devices of the system. The
direct access to I/O devices is not allowed; access to them is establish through Application
Programming Interface (API). The kernel maintains list of all the I/O devices of the system.
The service “Device Manager‟ of the kernel is responsible for handling all I/O related
operations. The Device Manager is responsible for:
 Loading and unloading of device drivers
 Exchanging information and the system specific control signals to and from the
device.

2
 I.RAVI KUMAR
5. Secondary Storage Management: The secondary storage management deals with
managing the secondary storage memory devices (if any) connected to the system.
Secondary memory is used as backup medium for programs and data, as main memory is
volatile. In most of the systems secondary storage is kept in disks (hard disks). The
secondary storage management service of kernel deals with:
 Disk storage allocation
 Disk scheduling
 Free disk space management
6. Protection Systems: Modern operating systems are designed in such way to support
multiple users with different levels of access permissions. The protection deals with
implementing the security policies to restrict the access of system resources and particular
user by different application or processes and different user.
7. Interrupt Handler: Kernel provides interrupt handler mechanism for all external/
internal interrupt generated by the system.
The important services offered by the kernel of an OS:
1. Kernel Space and User Space: The program code corresponding to the kernel
applications/ services are kept in a contiguous area of primary (working) memory and is
protected from the un-authorized access by user programs/ applications.
 The memory space at which the kernel code is located is known as “Kernel Space‟. All
user applications are loaded to a specific area of primary memory and this memory
area is referred as “User Space‟.
 The partitioning of memory into kernel and user space is purely OS dependent.
 Most of the operating systems keep the kernel application code in main memory and
it is not swapped out into the secondary memory.
2. Monolithic Kernel and Microkernel: Kernel forms the heart of OS. Different
approaches are adopted for building an operating system kernel. Based on the kernel
design, kernels can be classified into “Monolithic‟ and “Micro‟.
Monolithic Kernel: In monolithic kernel architecture, all kernel services run in the kernel
space. All kernel modules run within the same memory space under a single kernel thread.
Allows effective utilization of the low-level features of the underlying system. The major
drawback is that any error or failure in any one of the kernel modules leads to the crashing
of the entire kernel application. LINUX, SOLARIS, MS-DOS kernels are the examples.

3
 I.RAVI KUMAR

Microkernel: The microkernel design iincorporates only essential set of OS services into
the kernel. The rest of the OS services are implemented in program known as “Servers‟
which runs in user space. The memory management, timer systems and interrupt handlers
are the essential services, which forms the part of the microkernel. The benefits of micro
kernel based designs are:
 Robustness: If a problem is encountered in any of the services, which runs as a
server can be reconfigured and restarted without the restarting the entire OS. Here
chances of corruption of kernel services are ideally zero.
 Configurability: Any services, which runs as a server application can be changed
without the need to restart the whole system.
TYPES OF OPERATING SYSTEMS
Depending on the type of kernel and kernel services, purpose and type of computing
systems where the OS is deployed and the responsiveness to applications, Operating
Systems are classified into:
 General Purpose Operating System (GPOS)
 Real Time Purpose Operating System (RTOS)
1. General Purpose Operating System (GPOS): Operating systems, which are deployed in
general computing systems. The kernel is more generalized and contains all the required
services to execute generic applications. Need not be deterministic in execution behaviour.
May inject random delays into application software and thus cause slow responsiveness of
an application at unexpected times. Personal Computer/Desktop system is typical example
for a system where GPOSs are deployed. Windows XP/MS-DOS are examples of GPOS.
4
 I.RAVI KUMAR
2. Real Time Operating System (RTOS): Operating Systems, which are deployed in
embedded systems demanding real-time response. Real Time implies deterministic in timing
behavior. RTOS services consumes only known and expected amounts of time regardless
the number of services. RTOS implements policies and rules concerning time-critical
allocation of a system’s resources. RTOS decides which applications should run in which
order and how much time needs to be allocated for each application. Windows Embedded
Compact, QNX, VxWorks MicroC/OS-II, etc., are examples of RTOSs.
Real-Time kernel: The kernel of a Real-Time OS is referred as Real-Time kernel. The
Real-Time kernel is highly specialized and it contains only the minimal set of services
required for running user applications/ tasks. The basic functions of a Real-Time kernel
are listed below:
 Task/ Process management  Memory management
 Task/ Process scheduling  Interrupt handling
 Task/ Process synchronization  Time management.
 Error/ Exception handling
i) Task/ Process management: Deals with setting up the memory space for the tasks,
loading the tasks code into the memory space, allocating system resources and setting up a
Task Control Block (TCB) for the task and task/process termination/deletion. A TCB is
used for holding the information corresponding to a task. TCB usually contains the
following set of information:
 Task ID: Task Identification Number
 Task State: The current state of the task.
 Task Type: Task type. Indicates what is the type for this task.
 Task Priority: Task priority
 Task Context Pointer: Context pointer. Pointer for context saving
 Task Memory Pointers: Pointers to the code memory, data memory and stack memory
 Task System Resource Pointers: Pointers to system resources
 Task Pointers: Pointers to other TCBs
ii) Task/ Process Scheduling: Deals with sharing the CPU among various tasks/
processes. A kernel application called “Scheduler‟ handles the task scheduling. Scheduler
is an algorithm implementation, which performs the efficient and optimal scheduling of
tasks to provide a deterministic behavior.

5
 I.RAVI KUMAR
iii) Task/ Process Synchronization: Deals with synchronizing the concurrent access of a
resource, which is shared across multiple tasks and the communication between various
tasks.
iv) Error/ Exception Handling: Deals with registering and handling the errors occurred/
exceptions raised during the execution of tasks. Insufficient memory, timeouts, deadlocks,
deadline missing, bus error, divide by zero, unknown instruction execution etc., are
examples of errors/exceptions. Errors/ Exceptions can happen at the kernel level services
or at task level. Deadlock is an example for kernel level exception, whereas timeout is an
example for a task level exception.
Deadlock is a situation where a set of processes are blocked because each process is
holding a resource and waiting for another resource acquired by some other process.
Timeouts and retry are two techniques used together. The tasks retries an event/ message
certain number of times; if no response is received after exhausting the limit, the feature
might be aborted.
v) Memory Management: The memory allocation time increases depending on the size of
the block of memory need to be allocated and the state of the allocated memory block.
RTOS achieves predictable timing and deterministic behavior, by compromising the
effectiveness of memory allocation. RTOS generally uses “block‟ based memory allocation
technique, instead of the usual dynamic memory allocation techniques used by the GPOS.
RTOS kernel uses blocks of fixed size of dynamic memory and the block is allocated
for a task on a need basis. The blocks are stored in a “Free buffer Queue‟. The memory
management function a block of fixed memory is always allocated for tasks on need basis
and it is taken as a unit. Hence, there will not be any memory fragmentation issues.
vi) Interrupt Handling: Interrupts inform the processor that an external device or an
associated task requires immediate attention of the CPU. Interrupts can be either
Synchronous or Asynchronous.
Interrupts which occurs in sync with the currently executing task is known as
Synchronous interrupts. Eg: Divide by zero, memory segmentation error etc. Interrupts
which occurs at any point of execution of any task, and are not in sync with the currently
executing task are Asynchronous interrupts. Eg: Timer overflow interrupts, serial data
reception/ transmission interrupts etc. Priority levels can be assigned to the interrupts and
each interrupts can be enabled or disabled individually.

6
 I.RAVI KUMAR
vii) Time Management: The time reference to kernel is provided by a high-resolution Real
Time Clock (RTC) hardware chip (hardware timer). The hardware timer is programmed to
interrupt the processor/ controller at a fixed rate. This timer interrupt is referred as “Timer
tick‟. The Timer tick is taken as the timing reference by the kernel. Usually, the Timer tick
varies in the microseconds range. The System time is updated based on the Timer tick.
Types of Real Time System
Hard Real-Time: A Real Time Operating Systems which strictly adheres to the timing
constraints for a task is referred as hard real-time systems. A Hard RTS must meet the
deadlines for a task without any slippage. Missing any deadline may produce catastrophic
results for Hard RTS, including permanent data lose & irrecoverable damages to the
system/users. Most of the Hard Real Time Systems are automatic.
Eg: Air bag control systems and Anti-lock Brake Systems (ABS) of vehicles are typical
examples of Hard Real Time Systems.
Soft Real-Time: Real Time Operating Systems that does not guarantee meeting deadlines,
but, offer the best effort to meet the deadline are referred as soft real-time systems. Missing
deadlines for tasks are acceptable if the frequency of deadline missing is within the
compliance limit of the Quality of Service (QoS).
Automatic Teller Machine (ATM) is a typical example of Soft Real Time System. If the
ATM takes a few seconds more than the ideal operation time, nothing fatal happens.
TASKS, PROCESSES AND THREADS
The term “task‟ refers to something that needs to be done. In the Operating System
context, a task is defined as the program in execution and the related information
maintained by the Operating system for the program. Task is also known as “Job‟ in the
operating system context.
A program or part of it in execution is also called a “Process‟. The terms “Task‟, “Job‟
and “Process‟ refer to the same entity in the Operating System context and most often they
are used interchangeably.
Process: A Process is a program, or part of it, in execution. Process is also known as an
instance of a program in execution. A process requires various system resources like CPU
for executing the process, memory for storing the code corresponding to the process and
associated variables, I/O devices for information exchange etc.

7
 I.RAVI KUMAR
Structure of a Processes: The concept of Process leads to concurrent execution of
tasks and thereby, efficient utilization of the CPU and other system resources. Concurrent
execution is achieved through the sharing of CPU among the processes.
A process mimics a processor in properties and holds a set of registers, process
status, a Program Counter (PC) to point to the next executable instruction of the process, a
stack for holding the local variables associated with the process and the code
corresponding to the process. This can be visualized as shown in below figure.

Memory Organization of Process: The memory occupied by the process is

segregated into three regions namely: Stack memory, Data memory and Code memory.
 “Stack‟ memory holds all temporary data such as variables local to the process.
 “Data‟ memory holds all global data for the process.
 “Code‟ memory contains the program code corresponding to the process.
On loading a process into the main memory, a specific area of memory is allocated for the
process. The stack memory usually starts at the highest memory address from the memory
area allocated for the process.
Process States & State Transition
The process traverses through a series of states during its transition from the newly created
state to the terminated state. The cycle through which a process changes its state from
“newly created‟ to “execution completed‟ is known as “Process Life Cycle‟. The various
states through which a process traverses through during a Process Life Cycle indicates the
current status of the process with respect to time & also provides information on what it is
allowed to do next. The transition of a process from one state to another is known as “State
transition‟. The Process states & state transition representation are shown in below figure.

8
 I.RAVI KUMAR

Created State: The state at which a process is being created. The OS recognizes a process
in the “Created State‟ but no resources are allocated to the process.
Ready State: The state, where a process is incepted into the memory and awaiting the
processor time for execution. At this stage, the process is placed in the “Ready list‟ queue
maintained by the OS.
Running State: The state where in the source code instructions corresponding to the
process is being executed. Running state is the state at which the process execution
happens.
Blocked State/ Wait State: Refers to a state where a running process is temporarily
suspended from execution & does not have immediate access to resources.
Completed State: A state where the process completes its execution.
Thread: A thread is the primitive that can execute code. A thread is a single sequential flow
of control within a process. A thread is also known as lightweight process.
9
 I.RAVI KUMAR
A process can have many threads of
execution. Different threads, which are
part of a process, share the same address
space; meaning they share the data
memory, code memory and heap memory
area. Threads maintain their own thread
status (CPU register values), Program
Counter (PC) and stack. The memory
model for a process and its associated
threads are given in figure.
The Concept of Multithreading: The process is split into multiple threads, which
executes a portion of the process; there will be a main thread and rest of the threads will be
created within the main thread. The multithreaded architecture of a process can be
visualized with the thread-process diagram, shown.

Advantages of Multiple threads: Use of multiple threads to execute a process brings

the following advantage:
 Better memory utilization: Multiple threads of the same process share the address
space for data memory. This also reduces the complexity of inter thread
communication.
10
 I.RAVI KUMAR
 Speed: Since the process is split into different threads, when one thread enters a wait
state, the CPU can be utilized by other threads of the process. This speeds up the
execution of the process.
 Efficient CPU utilization: The CPU is engaged all time.
Differences between Threads and Processes

MULTIPROCESSING AND MULTITASKING

The ability to execute multiple processes simultaneously is referred as multiprocessing.
Systems which are capable of performing multiprocessing are known as multiprocessor
systems. Multiprocessor systems possess multiple CPUs and can execute multiple
processes simultaneously.
The ability of the Operating System to have multiple programs in memory, which are
ready for execution, is referred as multiprogramming. In a Uni-processor system, it is not
possible to execute multiple processes simultaneously. Multitasking refers to the ability of
an operating system to hold multiple processes in memory and switch the processor (CPU)
from executing one process to another process.
11
 I.RAVI KUMAR
Multitasking: Multitasking involves “Context switching‟, “Context saving‟ and “Context
retrieval‟. (shown in figure)
 The act of switching CPU among the processes or changing the current execution
context is known as "Context switching‟.
 The act of saving the current context (details like Register details, Memory details,
System Resource Usage details, Execution details, etc.) for the currently running
processes at the time of CPU switching is known as “Context saving‟.
 The process of retrieving the saved context details for a process, which is going to be
executed due to CPU switching, is known as “Context retrieval‟.

Types of Multitasking: Depending on how the task/ process execution switching act is
implemented, multitasking can is classified into –
 Co-operative Multitasking
 Preemptive Multitasking
 Non-preemptive Multitasking

12
 I.RAVI KUMAR
1. Co-operative Multitasking: Co-operative Multitasking is the most primitive form of
multitasking in which a task/ process gets a chance to execute only when the currently
executing task/ process voluntarily relinquishes the CPU.
In this method, any task/ process can avail the CPU as much time as it wants. Since
this type of implementation involves the mercy of the tasks each other for getting the CPU
time for execution, it is known as co-operative multitasking. If the currently executing task
is non-cooperative, the other tasks may have to wait for a long time to get the CPU.
2. Preemptive Multitasking: Preemptive multitasking ensures that every task/ process
gets a chance to execute. When and how much time a process gets is dependent on the
implementation of the preemptive scheduling.
As the name indicates, in preemptive multitasking, the currently running
task/process is preempted to give a chance to other tasks/process to execute. The
preemption of task may be based on time slots or task/ process priority.
3. Non-preemptive Multitasking: The process/ task, which is currently given the CPU
time, is allowed to execute until it terminates (enters Completed state) or enters Blocked/
Wait state, waiting for an I/O. The co-operative and non-preemptive multitasking differs in
their behaviour when they are in the Blocked/Wait state.
In co-operative multitasking, the currently executing process/task need not
relinquish the CPU when it enters the Blocked/ Wait sate, waiting for an I/O, or a shared
resource access or an event to occur whereas in non-preemptive multitasking the currently
executing task relinquishes the CPU when it waits for an I/O.
TASK SCHEDULING
Determining which task/process is to be executed at a given point of time is known as
task/process scheduling. Scheduling policies forms the guidelines for determining which
task is to be executed when. The kernel service/application which implements the
scheduling algorithm, is known as 'Scheduler. Process scheduling decision may take place
when a process switches its state to:
1. Ready state from Running state
2. Blocked/Wait state from Running state
3. Ready state from Blocked/Wait state
4. Completed state

13
 I.RAVI KUMAR
A process switches to Ready state from the Running state when it is preempted. Hence,
the type of scheduling in scenario 1 is pre-emptive. When a high priority process in the
Blocked/Wait state completes its I/O and switches to the Ready state, the scheduler picks
it for execution if the scheduling policy used is priority based preemptive. This is indicated
by scenario 3.
In preemptive/non-preemptive multitasking, the process relinquishes the CPU when
it enters the Blocked/Wait state or the Completed state and switching of the CPU
happens at this stage. Scheduling under scenario 2 can be either preemptive or non-
preemptive. Scheduling under scenario 4 can be preemptive, non-preemptive or co-
operative.
The selection of a scheduling criterion/algorithm should consider the following factors:
 CPU Utilisation: The scheduling algorithm should always make CPU utilisation high.
 Throughput: Gives an indication of the number of processes executed per unit of time
 Turnaround Time: Amount of time taken by a process for completing its execution.
 Waiting Time: It is the amount of time spent by a process in the 'Ready' queue
waiting to get the CPU time for execution.
 Response Time: It is the time elapsed between the submission of a process and the
first response.
The Operating System maintains various queues in connection with the CPU
scheduling, and a process passes through these queues during the course of its admittance
to execution completion. The various queues maintained by OS in association with CPU
scheduling are:
Job Queue: Job queue contains all the processes in the system
Ready Queue: Contains all the processes, which are ready for execution and waiting for
CPU to get their turn for execution. The Ready queue is empty when there is no process
ready for running.
Device Queue: Contains the set of processes, which are waiting for an I/O device. A
process migrates through all these queues during its journey from 'Admitted to 'Completed
stage.
Figure below illustrates the transition of a process through the various queues.

14
 I.RAVI KUMAR

Non-preemptive Scheduling
Non-preemptive scheduling is employed in systems, which implement non-preemptive
multitasking model. In this scheduling type, the currently executing task/process is
allowed to run until it terminates or enters the 'Wait' state waiting for an I/O or system
resource. The various types of non-preemptive scheduling adopted in task/process
scheduling are listed below:
1. First-Come-First-Served (FCFS)/ FIFO Scheduling
As the name indicates, the First-Come-First-Served (FCFS) scheduling algorithm allocates
CPU time to the processes based on the order in which they enter the 'Ready' queue. The
first entered process is serviced first. FCFS scheduling is also known as First In First Out
(FIFO) where the process which is put first into the 'Ready queue is serviced first.
Example 1: Three processes with process ID’s P1, P2, P3 with estimated completion time
10, 5, 7 milliseconds respectively enters the ready queue together in the order P1, P2, P3.
Calculate the waiting time and Turn Around Time (TAT) for each process and the average
waiting time and Turn Around Time (Assuming there is no 1/0 waiting for the processes).
15
 I.RAVI KUMAR
Solution: The sequence of execution of the processes by the CPU is represented as
P1 P2 P3
Assuming the CPU is readily available at the time of arrival of P1, P1 starts executing
without any waiting in the 'Ready' queue. Hence the waiting time for P1 is zero. Thus, the
waiting time for all processes are given as:
Waiting Time for P1 = 0
Waiting Time for P2 = 10ms (P2 starts executing after completing P1)
Waiting Time for P3 = 15ms (P3 starts executing after completing P1 and P2)
Average waiting time = (Waiting time for all processes) / No. of Processes
= (0 + 10 +15) / 4 = 8.33 milliseconds.
Turn Around Time (TAT) = Time spent in Ready Queue (Waiting time) + Execution Time
Turn Around Time (TAT) for P1 = 10ms (0 + 10)
Turn Around Time (TAT) for P2 = 15ms (10 + 5)
Turn Around Time (TAT) for P3 = 22ms (15 + 7)
Average Turn Around Time (TAT) = Average waiting time + Average execution time.
Average Execution Time = (Execution time for all processes)/No. of processes
= 10 + 5 + 7 / 3 = 7.33 milliseconds.
Average Turn Around Time (TAT) = 8.33 + 7.33 = 15.66 milliseconds.
NOTE: Average Turn Around Time (TAT) = TAT of all processes / No. of Processes
= (10+15+22)/3 = 15.66 milliseconds.
2. Last-Come-First Served (LCFS)/LIFO Scheduling
The Last-Come-First Served (LCFS) scheduling algorithm also allocates CPU time to the
processes based on the order in which they are entered in the 'Ready' queue. The last
entered process is serviced first. LCFS scheduling is also known as Last In First Out (LIFO)
where the process, which is put last into the 'Ready' queue, is serviced first.
Example 1: Three processes with process ID’s P1, P2, P3 with estimated completion time
10, 5, 7 milliseconds respectively enters the ready queue together in the order P1, P2, P3.
Now a new process P4 with estimated completion time 6ms enters the 'Ready' queue after
5ms of scheduling Pl. Calculate the waiting time and Turn Around Time (TAT) for each
process and the Average waiting time and Turn Around Time.
Solution: Initially there is only P1 available in the Ready queue and the scheduling
sequence will be P1, P3, P2. P4 enters the queue during the execution of P1 and becomes

16
 I.RAVI KUMAR
the last process entered the 'Ready' queue. Now the order of execution changes to P1, P4,
P3, and P2 as given below:
P1 P4 P3 P2
The waiting time for all the processes is given as:
Waiting Time for P1 = 0ms (P1 starts executing first)
Waiting Time for P4 = 5ms (P4 starts executing after completing Pl. But P4 arrived after
5ms of execution of P1. Hence it’s waiting time = Execution start time - Arrival Time = 5)
Waiting Time for P3 = 16ms (P3 starts executing after completing Pl and P4)
Waiting Time for P2 = 23ms (P2 starts executing after completing P1, P4 and P3)
Average waiting time = (Waiting time for all processes) / No. of Processes
= 0+5+16+23 / 4 = 11 milliseconds.
Turn Around Time (TAT) = Time spent in Ready Queue (Waiting time) + Execution Time
Turn Around Time (TAT) for P1 = 10ms (0 + 10)
Turn Around Time (TAT) for P4 = 11ms ((10-5) + 6)
Turn Around Time (TAT) for P3 = 23ms (16 + 7)
Turn Around Time (TAT) for P3 = 28ms (23 + 5)
Average Turn Around Time (TAT) = TAT of all processes / No. of Processes
= (10+11+23+28) / 4 = 18 milliseconds.
3. Shortest Job First (SJF) Scheduling
Shortest Job First (SJF) scheduling algorithm 'sorts the 'Ready' queue' each time a process
relinquishes the CPU to pick the process with shortest (least) estimated completion/run
time. In SJF, the process with the shortest estimated run time is scheduled first, followed
by the next shortest process, and so on.
Example 1: Three processes with process IDs P1, P2, P3 with estimated completion time
12, 6, 8 milliseconds respectively enters the ready queue together. Calculate the waiting
time and Turn Around Time (TAT) for each process and the Average waiting time and Turn
Around Time (Assuming there is no I/O waiting for the processes) in SJF algorithm.
Solution: The scheduler sorts the 'Ready' queue based on the shortest estimated
completion time and schedules the process with the least estimated completion time first
and the next least one as second, and so on. The order in which the processes are
scheduled for execution is represented as
P2 P3 P1

17
 I.RAVI KUMAR
The waiting time for all processes are given as:
Waiting Time for P2 = 0ms (P2 starts executing first)
Waiting Time for P3 = 6ms (P3 starts executing after completing P2)
Waiting Time for PI = 14ms (P1 starts executing after completing P2 and P3)
Average waiting time = (Waiting time for all processes) / No. of Processes
= (0+6+14) / 3 = 6.66 milliseconds
Turn Around Time (TAT) = Time spent in Ready Queue (Waiting time) + Execution Time
Turn Around Time (TAT) for P2 = 10ms (0 + 6)
Turn Around Time (TAT) for P3 = 14ms (6 + 8)
Turn Around Time (TAT) for P1 = 24ms (14 + 10)
Average Turn Around Time (TAT) = TAT of all processes / No. of Processes
= (10+14+24) / 3 = 16 milliseconds.
Example 2: Calculate the waiting time and Turn Around Time (TAT) for each process and
the Average waiting time and Turn Around Time for the above example if a new process P4
with estimated completion time 2ms enters the 'Ready' queue after 2ms of execution of P2.
Assume all the processes contain only CPU operation and no I/O operations are involved.
Solution: At the beginning, there are only three processes (P1, P2 and P3) available in the
'Ready' queue and the SJF scheduler picks up the process with the least execution
completion time (P2) for scheduling. The execution sequence is P2, P3, P1. Now process P4
with estimated execution completion time 2ms enters the 'Ready' queue after 2ms of start
of execution of P2. After 6ms of scheduling, P2 terminates and now the scheduler again
sorts the 'Ready' queue for process with least execution completion time. Since the
execution completion time for P4 (2ms) is less than that of P3 (8ms), which was supposed
to be run after the completion of P2 as per the 'Ready' queue available at the beginning of
execution scheduling, P4 is picked up for executing. Due to the arrival of the process P4
with execution time 2ms, the 'Ready' queue is re-sorted in the order P2, P4, P3, Pl. At the
beginning it was P2, P3, P1. The execution sequence now changes as per the following
diagram
P2 P4 P3 P1
The waiting time for all the processes are given as:
Waiting time for P2 = 0ms (P2 starts executing first)
Waiting time for P4 = 4ms (P4 starts executing after completing P2. But P4 arrived after

18
 I.RAVI KUMAR
2ms of execution of P2. Hence it’s waiting time = Execution start time - Arrival Time = 3)
Waiting time for P3 = 8ms (P3 starts executing after completing P2 and P4)
Waiting time for P1 = 16ms (P1 starts executing after completing P2, P4 and P3)
Average waiting time = (Waiting time for all processes) / No. of Processes
= (0+4+8+16) / 4 = 7 milliseconds.
Turn Around Time (TAT) = Time spent in Ready Queue (Waiting time) + Execution Time
Turn Around Time (TAT) for P2 = 6ms (0 + 6)
Turn Around Time (TAT) for P4 = 6ms ((6-2) + 2)
Turn Around Time (TAT) for P3 = 16ms (8 + 8)
Turn Around Time (TAT) for P1 = 28ms (16 + 12)
Average Turn Around Time (TAT) = TAT of all processes / No. of Processes
= (6+6+16+28) / 4 = 19 milliseconds.
4. Priority Based Scheduling: Priority based non-preemptive scheduling algorithm
ensures that a process with high priority is serviced at the earliest compared to other low
priority processes in the 'Ready' queue. While creating the process/task, the priority can be
assigned to it. The priority number associated with a task/process is the direct indication
of its priority. The non-preemptive priority based scheduler sorts the 'Ready' queue based
on priority and picks the process with the highest level of priority for execution.
Example 1: Three processes with process IDs P1, P2, P3 with estimated completion time
10, 5, 7 milliseconds and priorities 0, 3, 2 (0-highest priority, 3-lowest priority) respectively
enters the ready queue together. Calculate the waiting time and Turn Around Time (TAT)
for each process and the Average waiting time and Turn Around Time (Assuming there is no
I/O waiting for the processes) in priority based scheduling algorithm.
Solution: The scheduler sorts the 'Ready' queue based on the priority and schedules the
process with the highest priority (P1 with priority number 0) first and the next high priority
process (P3 with priority number 2) as second, and so on. The order in which the processes
are scheduled for execution is represented as
P1 P3 P2
The waiting time for all the processes are given as:
Waiting time for P1 = 0ms (P1 starts executing first)
Waiting time for P3 = 10ms (P3 starts executing after completing PI)
Waiting time for P2 = 17ms (P2 starts executing after completing P1 and P3)

19
 I.RAVI KUMAR
Average waiting time = (Waiting time for all processes) / No. of Processes
= (0+10+17)/3 = 9 milliseconds
Turn Around Time (TAT) = Time spent in Ready Queue (Waiting time) + Execution Time
Turn Around Time (TAT) for P1 = 10ms (0+10)
Turn Around Time (TAT) for P3 = 17ms (10+7)
Turn Around Time (TAT) for P2 = 22ms (17+5)
Average Turn Around Time (TAT) = TAT of all processes / No. of Processes
= (10+17+22)/3 = 16.33 milliseconds
Example 2: Calculate the waiting time and Turn Around Time (TAT) for each process and
the Average waiting time a Turn Around Time for the above example if a new process P4
with estimated completion time 6ms priority 1 enters the 'Ready' queue after 5ms of
execution of P1. Assume all the processes contain only CP operation and no I/O operations
are involved.
Solution: At the beginning, there are only three processes (P1, P2 and P3) available in the
'Ready' queue and the scheduler picks up the process with the highest priority (P1) for
scheduling. The execution sequence is P1, P3, P2. Now process P4 with estimate execution
completion time 6ms and priority 1 enters the 'Ready' queue after 5ms of execution of P1.
After 10ms of scheduling, Pl terminates and now the scheduler again sorts the 'Ready
queue for process with highest priority. Since the priority for P4 (priority 1) is higher than
that of P3 (priority 2 which was supposed to be run after the completion of P1 as per the
'Ready' queue available at the beginning of execution scheduling, P4 is picked up for
executing. Due to the arrival of the process P4 with priority the 'Ready' queue is resorted in
the order P1, P4, P3, P2. At the beginning it was P1, P3, P2. The execution sequence now
changes as per the following diagram
P1 P4 P3 P2
The waiting time for all the processes are given as:
Waiting time for P1 = 0ms (P1 starts executing first)
Waiting time for P4 = 5ms (P4 starts executing after completing P1. But P4 arrived after
5ms of execution of P1. Hence it’s waiting time=Execution start time - Arrival Time=10-5=5)
Waiting time for P3 = 16ms (P3 starts executing after completing PI and P4)
Waiting time for P2 = 23ms (P2 starts executing after completing P1, P4 and P3)
Average waiting time = (Waiting time for all processes) / No. of Processes

20
 I.RAVI KUMAR
= (0+5+16+23) / 4 = 11 milliseconds
Turn Around Time (TAT) = Time spent in Ready Queue (Waiting time) + Execution Time
Turn Around Time (TAT) for P1 = 10ms (0+10)
Turn Around Time (TAT) for P4 = 11ms (5+6)
Turn Around Time (TAT) for P3 = 23ms (16+7)
Turn Around Time (TAT) for P2 = 28ms (23+5)
Average Turn Around Time (TAT) = TAT of all processes / No. of Processes
= (10+11+23+28)/ 4 = 18 milliseconds
Preemptive Scheduling
In preemptive scheduling, every task in the 'Ready’ queue gets a chance to execute. When
and how often each process gets a chance to execute is dependent on the type of
preemptive scheduling algorithm used for scheduling the processes. In this kind of
scheduling, the scheduler can preempt (stop temporarily) the currently executing
task/process and select another task from the 'Ready' queue for execution.
A task which is preempted by the scheduler is moved to the 'Ready queue. The act of
moving a 'Running process/task into the "Ready' queue by the scheduler, without the
processes requesting for it is known as 'Preemption’.
1. Preemptive SJF Scheduling/Shortest Remaining Time (SRT)
The preemptive SJF scheduling algorithm sorts the 'Ready’ queue when a new process
enters the 'Ready’ queue and checks whether the execution time of the new process is
shorter than the remaining of the total estimated time for the currently executing process.
If the execution time of the new process is less, the currently executing process is
preempted and the new process is scheduled for execution Preemptive SJF scheduling is
also known as Shortest Remaining Time (SRT) scheduling
Example 1: Three processes with process IDs P1, P2, P3 with estimated completion time
10, 5, 7 milliseconds respectively enters the ready queue together. A new process P4 with
estimated completion time 2ms enters the 'Ready' queue after 2ms. Calculate the waiting
time and Turn Around Time (TAT) for each process and the Average waiting time and Turn
Around Time in preemptive SJF/SRT based scheduling algorithm.
Solution: At the beginning, there are only three processes (P1, P2 and P3) available in the
'Ready' queue and the SRT scheduler picks up the process with the shortest remaining time
for execution completion for scheduling. Now process P4 with estimated execution

21
 I.RAVI KUMAR
completion time 2ms enters the 'Ready' queue after 2ms of start of execution of P2. Since
the SRT algorithm is preemptive, the remaining time for completion of process P2 is
checked with the remaining time for completion of process P4. The remaining time for
completion of P2 is 3ms which is greater than that of the remaining time for completion of
the newly entered process P4 (2ms). Hence P2 is preempted and P4 is scheduled for
execution. P4 continues its execution to finish since there is no new process entered in the
'Ready' queue during its execution. After 2ms of scheduling P4 terminates and now the
scheduler again sorts the 'Ready' queue based on the remaining time for completion of the
processes present in the 'Ready' queue. The execution sequence now changes as per the
following diagram
P2 P4 P2 P3 P1
The waiting time for all the processes are given as:
Waiting time for P2 = 0ms + (4-2) ms = 2ms (P2 starts executing first and is interrupted by
P4 and has to wait till the completion of P4 and has to wait till the completion of P4)
Waiting time for P4 = 0ms (P4 starts executing after preempting P2)
Waiting time for P3 = 7ms (P3 starts executing after completing P4 and P2)
Waiting time for P1= 14ms (P1 starts executing after completing P2, P4 and P3)
Average waiting time = (Waiting time for all processes) / No. of Processes
= (0+2+7+14) / 4 = 5.75 milliseconds
Turn Around Time (TAT) = Time spent in Ready Queue (Waiting time) + Execution Time
Turn Around Time (TAT) for P2 = 7ms (2+5)
Turn Around Time (TAT) for P4 = 2ms (0+2)
Turn Around Time (TAT) for P3 = 14ms (7+7)
Turn Around Time (TAT) for P2 = 24ms (14+10)
Average Turn Around Time (TAT) = TAT of all processes / No. of Processes
= (7+2+14+24)/ 4 = 11.75 milliseconds
2. Round Robin (RR) Scheduling: In Round Robin scheduling, each process in the 'Ready'
queue is executed for a pre-defined time slot. The execution starts with picking up the first
process in the 'Ready' queue (see Fig.). It is executed for a pre-defined time and when the
pre-defined time elapses or the process completes (before the pre-defined time slice), the
next process in the ‘Ready' queue is selected for execution. This is repeated for all the
processes in the 'Ready' queue. Once each process in the 'Ready' queue is executed for the

22
 I.RAVI KUMAR
pre-defined time period, the scheduler comes back and picks the first process in the
"Ready' queue again for execution. The sequence is repeated.
Example 1: Three processes with process IDs P1, P2, P3 with estimated completion time 6,
4, 2 milliseconds respectively enters the ready queue together in the order P1, P2, P3,
Calculate the waiting time and Turn Around Time (TAT) for each process and the Average
waiting time and Turn Around Time in RR algorithm with Time slice = 2 ms.
Solution: The scheduler sorts the 'Ready' queue and picks up the first process PI from the
‘Ready' queue and executes it for the time slice 2ms. When the time slice is expired, PI is
preempted and P2 is scheduled for execution. The Time slice expires after 2ms of execution
of P2. Now P2 is preempted and P3 is picked up for execution. P3 completes its execution
within the time slice and the scheduler picks P1 again for execution for the next time slice.
This procedure is repeated till all the processes are serviced. The order in which the
processes are scheduled for execution is represented as
P1 P2 P3 P1 P2 P1
The waiting time for all the processes are given as:
Waiting time for P1 = 0 + (6 - 2) + (10 - 8) = 6ms (P1 starts executing first and waits for two
time slices to get execution back and again 1 time slice for getting CPU time)
Waiting time for P2 = (2 - 0) + (8 - 4) = 6ms (P2 starts executing after P1 executes for 1 time
slice and waits for two time slices get the CPU time)
Waiting time for P3 = (4 – 0) = 4ms (P3 starts executing after completing the first time slices
for P1 and P2 and completes its execution in a single time slice)
Average waiting time = (Waiting time for all processes) / No. of Processes
= (6+6+4) / 3 = 5.33 milliseconds
Turn Around Time (TAT) = Time spent in Ready Queue (Waiting time) + Execution Time
Turn Around Time (TAT) for P1 = 12ms (6+6)
Turn Around Time (TAT) for P2 = 10ms (6+4)
Turn Around Time (TAT) for P3 = 6ms (4+2)
Average Turn Around Time (TAT) = TAT of all processes / No. of Processes
= (12+10+6)/ 3 = 9.33 milliseconds
3. Priority Based Scheduling: Priority based preemptive scheduling algorithm is same as
that of the non-preemptive priority based scheduling except for the switching of execution
between tasks. In preemptive scheduling, any high priority process entering the 'Ready'

23
queue is immediately scheduled for execution whereas in the non-preemptive scheduling
I.RAVI KUMAR
any high priority process entering the 'Ready’ queue is scheduled only after the currently
executing process completes its execution or only when it voluntarily relinquishes the CPU.
Example 1: Three processes with process IDs P1, P2, P3 with estimated completion time
10, 5, 7 milliseconds and priorities 1, 3, 2 (0-highest priority, 3 lowest priority) respectively
enters the ready queue together. A new process P4 with estimated completion time 6 ms
and priority O enters the 'Ready' queue after 5 ms of start of execution of Pl. Calculate the
waiting time and Turn Around Time (TAT) for each process and the Average waiting time
and Turn Around Time in preemptive priority based scheduling algorithm.
Solution: At the beginning, there are only three processes (P1, P2 and P3) available in the
'Ready' queue and the scheduler picks up the process with the highest priority (P1) for
scheduling. Now process P4 with estimated execution completion time 6 ms and priority 0
enters the 'Ready' queue after 5 ms of start of execution of P1. Since the scheduling
algorithm is preemptive, P1 is preempted by P4 and P4 runs to completion. After 6 ms of
scheduling, P4 terminates and now the scheduler again sorts the 'Ready' queue for process
with highest priority. Since the priority for P1 (priority 1), which is preempted by P4 is
higher than that of P3 (priority 2) and P2 ((priority 3), Pl is again picked up for execution by
the scheduler. The execution sequence is as per the following:
P1 P4 P1 P3 P2
The waiting time for all the processes are given as:
Waiting time for P1 = 0ms + (11-5) ms = 6ms (P21starts executing first and gets preempted
by P4 after 5ms and again gets CPU after completion of P4)
Waiting time for P4 = 0ms (P4 starts executing immediately after preempting P1)
Waiting time for P3 = 16ms (P3 starts executing after completing P1 and P4)
Waiting time for P2= 23ms (P2 starts executing after completing P1, P4 and P3)
Average waiting time = (Waiting time for all processes) / No. of Processes
= (6+0+16+23) / 4 = 111.25 milliseconds
Turn Around Time (TAT) = Time spent in Ready Queue (Waiting time) + Execution Time
Turn Around Time (TAT) for P1 = 16ms (6+10)
Turn Around Time (TAT) for P4 = 6ms (0+6)
Turn Around Time (TAT) for P3 = 23ms (16+7)
Turn Around Time (TAT) for P2 = 28ms (23+5)

Average Turn Around Time (TAT) = TAT of all processes / No. of Processes
= (16+6+23+28)/ 4 = 18.25 milliseconds
I.RAVI KUMAR
I.RAVI KUMAR
I.RAVI KUMAR
 lOMoARcPSD|42822176

I.RAVI KUMAR
Unit - V
INTEGRATION AND TESTING OF EMBEDDED HARDWARE AND FIRMWARE
Integration and Testing of Embedded Hardware and Firmware:
Integration of Hardware and Firmware, Boards Bring up
The Embedded System Development Environment:
The Integrated Development Environment (IDE), Types of files generated on Cross-Compilation,
Disassembler/Decompiler, Simulators, Emulators and Debugging, Target Hardware Debugging,
Boundary Scan.

Integration of Hardware and Firmware

Integration of hardware and firmware deals with the embedding of firmware into the target
hardware board. It is the process of 8Embedding Intelligence9 to the product. A variety of
techniques are used for embedding the firmware into the target board. The commonly used
firmware embedding techniques for a non-OS based embedded system are given below:
1. Out of circuit programming
2. In System Programming
3. In Application Programming
1. Out-of-Circuit Programming
Out-of-circuit programming is performed outside the target board. The
processor or memory chip into which the firmware needs to embedded is taken out of
the target board and it is programmed with the help of programming device. The
programming device is dedicated unit when contains the necessary hardware circuit to
generate the programming signals. The programmer contains a ZIF socket with locking
pin to hold the device to be programmed. The programming device will be under the
control of a utility program running on a PC. The programmer is interfaced to the PC
through RS-232C/USB/Parallel Port Interface. The commands to control the
programmer are sent from the utility program to the programmer through the interface.
Operations for embedding the firmware with a programmer.
 Connect the programming device to the specified port of PC
(USB/COM port/parallel port)
 Power up the device.(Ensure that the power indication LED is ON)
 Execute the programming utility on the PC and ensure proper connectivity is
established between the PC and programmer. In case of error turn off device
power and try connecting it again.
 Unlock the ZIF socket by turning the lock pin.
 lOMoARcPSD|42822176

I.RAVI KUMAR
 Insert the device to be programmed into the open socket as per the insert
diagram shown on the programmer.
 Lock the ZIF socket.
 Select the device name from the list of supported devices.
 Load the hex file which is to be embedded into the device.
 Program the device by 8Program9 option of utility program.
 Wait till the completion of programming operation.(Till busy LED of
programmer is off)
 Ensure that programming is successful by checking the status LED on the
programmer (Usually 8Green9 for success and 8Red9 for error condition) or by
noticing the feedback from the utility program.
 Unlock the ZIF socket and take the device out of programmer.
Drawbacks:
 High development time.
Whenever the firmware is changed, the chip should be taken out of the board
for reprogramming. This tedious and prone to chip damages due to frequent insertion
and removal. Better use a socket on the board side to hold the chip till the firmware
modifications are over.
 Not suitable for batch production.
2. In System Programming (ISP)
In ISP, programming is done within the system. The firmware is embedded into
the target device without removing it from the target board. It is the flexible and easy
way of firmware embedding. The only pre-requisite is that the device must have an ISP
support. A part from target board, PC, ISP utility and ISP cable, no other additional
hardware is required for ISP. In order to perform ISP operations the target device should
be powered up in a special 8ISP mode9. ISP mode allows the device to communicate
with an external host through a serial interface, such as a PC or terminal. The device
receives commands and data from the host, erases and reprograms code memory
according to the received command. Once the operations are completed, the device is
re-configured so that it will operate normally.
In System Programming with SPI Protocol
Devices with SPI In System Programming support contains a built-in interface and a
on-chip EEPROM or FLASH memory is programmed through this interface.
 lOMoARcPSD|42822176

I.RAVI KUMAR
The primary I/O lines involved in SPI-In System Programming are listed below,
a. MOSI – Master Out Slave In
b. MISO – Master In Slave Out
c. SCK – System Clock
d. RST – Reset of Target Device
e. GND – Ground of Target Device
The power up sequence for In System Programming for Atmel9s AT89S series
microcontroller:
 Apply supply voltage between VCC and GND pins of target chip.
 Set RST pin to <HIGH= state.
 If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to
24MHz clock to XTAL1 pin and wait for at least 10 milliseconds.
 Enable serial programming by sending the Programming Enable serial
instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin
SCK/P1.7 needs to be less than the CPU clock at XTAL1 divided by 40.
 The Code or Data array is programmed one byte at a time supplying the address
and data together with the appropriate Write instruction. The selected memory
location is first erased before the new data is written. The write cycle is self –
timed and typically takes less than 2.5 ms at 5V.
 Any memory location can be verified by using the Read instruction which
returns the content at the selected address at serial output MISO/P1.6.
 After successfully programming the device, set RST pin low or turn off the chip
power supply and turn it ON to commence the normal operation.
3. In Application Programming (IAP)
In Application Programming (IAP) is a technique used by the firmware running
on the target device for modifying a selected portion of the code memory. It is not a
technique for first time embedding of user written firmware. It modifies the program
code memory under the control of embedded application. Updating calibration data,
look-up tables, etc., which are stored in the code memory, are typical examples of IAP.
The Boot ROM resident API instructions which perform various functions such as
programming, erasing and reading the Flash memory during ISP mode are made
available to the end-user written firmware for IAP.
 lOMoARcPSD|42822176

I.RAVI KUMAR
Firmware Loading for Operating System based Devices
It is possible to embed the firmware into the target processor/controller memory
at the time of chip fabrication itself. Such chips are known as 8Factory Programmed
Chips9. The OS based embedded systems are programmed using the In System
Programming (ISP) technique. OS based embedded systems contain a special piece of
code called 8Boot loader9 program which takes control of the OS and application
firmware embedding and copying of the OS image to the RAM of the system for
execution.
EMBEDDED SYSTEM DEVELOPMENT ENVIRONMENT
Components of Embedded development environment
 Host Computer
Acts as the heart of development environment.
 IDE Tools
Tools for firmware design and development
 Electronic Design Automation Tools
Embedded Hardware Design
 Emulator hardware
Debugging target board
 Signal Sources(function generator)
Simulates inputs to target board
 Target Hardware Debugging tools
CRO, Multimeter ,Logic Analyser
For debugging hardware
 Target Hardware
IDE
In Embedded System, IDE stands for an integrated environment for developing
and debugging the target processor specific embedded firmware. An IDE is also known
as integrated design environment or integrated debugging environment. IDE is a
software package which bundles a <Text Editor=, <Cross-compiler=, =Linker= and a
<Debugger= IDE is a software application that provides facilities to computer
programmers for software development. IDEs can either command line based or GUI
based. IDE consists of
1. Text Editor or Source code editor
2. A compiler and an interpreter
 lOMoARcPSD|42822176

I.RAVI KUMAR
3. Build automation tools
4. Debugger
5. Simulators
6. Emulators and logic analyzer
An example of IDE is Turbo C/C++ which provides platform on windows for
development of application programs with command line interface. The other category
of IDE is known as Visual IDE which provides the platform for visual development
environment, ex- Microsoft Visual C++. IDEs used in Embedded firmware are slightly
different from the generic IDE used for high level language based development for
desktop applications. In Embedded applications, the IDE is either supplied by the target
processor/controller manufacturer or by third party vendors or as Open source.
Cross Compilation
Cross compilation is the process of converting a source code written in high
level language to a target processor/controller understandable machine code. The
conversion of the code is done by software running on a processor/controller which is
different from the target processor. The software performing this operation is referred
as the Cross-compiler. In other words cross-compilation the process of cross platform
software/firmware development. A cross complier is a compiler that runs on one type
of processor architecture but produces object code for a different type of processor
architecture.
Need for Cross Compiler
There are several advantages of using cross compiler. Some of them are as
below:
-By using cross compliers we can not only develop complex Embedded System but
reliability can be improved and maintenance is easy.
- Knowledge of the processor instruction set is not required.
-Register allocation and addressing mode details are managed by the compiler.
-The ability to combine variable selection with specific operations improves program
readability.
-Keywords and operational functions that more nearly resemble the human thought
process can be changed.
-Program development and debugging time will be dramatically reduced when
compared to assembly language programming.
 lOMoARcPSD|42822176

I.RAVI KUMAR
-The library files that are supplied provide may standard routines that may be
incorporated into our application.
-Existing routine can be reused in new programs by utilizing the modular programming
techniques available with C.
-The C language is very portable and very popular.
Types of Files generated on Cross compilation
The various files generated during cross- compilation process are:
1. List File
2. Pre-processor Output file
3. Hex File (.hex)
4. Map File (File extension linker dependent)
5. Object File (.obj)
1.List Files (.lst files)
 Generated at the time of cross compilation
 Contain information about cross compilation process like
– Cross compiler details
– Formatted source text
– Assembling code generated from the source file
– Symbol table
– Errors and warning detected by the cross compiler system
2.Preprocessor output file
 generated during cross compilation
 contain preprocessor output for the preprocessor instructions used in the source
file
 This file is used for verifying the operation of macros and conditional
preprocessor directives is a valid C file
 file extension is cross compiler dependent
3.Hex file
 The Hex file is an ASCII text file with lines of text that follow the Intel Hex file
format.
 Intel Hex files are often used to transfer the program and data that would be
stored in a Rom or EPROM.
 lOMoARcPSD|42822176

I.RAVI KUMAR
4.Map Files
 Object file created contains relocatable codes i.e their location in memory is not
fixed.
 It is the responsibility of linker to link these object modules. The locator is
responsible for locating the absolute address to each module in the code
memory. Map files are generated by the linker and loader. These files are used
to keep the information of linking and locating process. Map files use extensions
.H,.HH,.HM depends on linker or loader
5. Object files
 It is the lowest level file format for any platform.
 Cross compiling each source module converts the various Embedded
instructions and other directives present in the module to an object (.OBJ) file.
 The object file is specially formatted file with data records for symbolic
information, object code, debugging information etc.
 OMF 1 & OMF2 are the 2 object files supported by C51 Cross compiler
List of details included in object file are
1. Reserved memory for global variables
2. Public symbol(variable or function)names
3. External symbol(variable or function)references
4. Library files with which to link
5. Debugging information to help synchronize source lines with object files

DISASSEMBLER/DECOMPILER
 Both are reverse engineering tools.
 Reverse engineering is a technology used to reveal the technology behind the
working of a product
-used to find out the secret behind popular proprietary product
-helps the reverse engineering process by translating embedded
firmware to assembly /high level instruction
-Powerful tools for analyzing the presence of malicious contents
DISASSEMBLER
-utility program that convert machine code into assembly code.
-It is complementary to assembly or cross assembly
 lOMoARcPSD|42822176

I.RAVI KUMAR
DECOMPILER
-is a utility program that convert machine language instruction to high level
language instruction.
- Performs reverse operation of compiler or cross compiler.
SIMULATORS, EMULATORS AND DEBUGGING
Simulators
-Simulator is a software tool for simulating various functionality of the application
software.IDE provides simulator support. Simulator simulates target hardware and
firmware execution can be simulate using simulators
Features of simulator:
1. Purely software based
2. Doesn9t require a real target system
3. Very primitive
4. Lack of real time behavior
Limitations:
1. Deviation from real behavior
2. Lack of real timeliness
Advantage of simulator based debugging
1. No need of target board
- Purely software oriented, IDE simulates the target board
- Since real hardware is not needed we can start immediately after the device interface
and memory maps are finalized this saved development time
2. Simulated I/O peripherals
- It eliminates the need for connecting IO devices for debugging the firmware
3. Simulates abnormal conditions
- Can input any parameter as input during debugging hence can check for abnormal
conditions easily
EMULATOR
• It is a piece of hardware that exactly behaves like the real microcontroller chip with all
its integrated functionality.
• It is the most powerful debugging of all.
• A microcontroller9s functions are emulated in real-time and non-intrusively.
• All emulators contain 3 essential function:
1. The emulator control logic, including emulation memory
 lOMoARcPSD|42822176

I.RAVI KUMAR
2. The actual emulation device
3. A pin adapter that gives the emulator9s target connector the same <package= and pin
out as the microcontroller to be emulated.
• An emulator is a piece of hardware that looks like a processor, has memory like a
processor, and executes instructions like a processor but it is not a processor.
• The advantage is that we can probe points of the circuit that are not accessible
inside a chip.
• It is a combination of hardware and software.
DEBUGGERS
What is Debugging?
• Debugging in embedded application is the process of diagnosing the firmware
execution, monitoring the target processor9s registers and memory while the
firmware is running and checking the signals from various buses of embedded
hardware.
• Classified as
o Hardware Debugging
o Firmware Debugging
• Hardware Debugging:
o Deals with monitoring of various bus signals and checking the status lines
of target hardware.
• Firmware Debugging:
o Deals with examining the firmware execution, execution flow, changes
to various CPU registers and status registers on execution of the firmware
to ensure that the firmware is running as per the design
Why is Debugging required?
• Firmware Debugging is performed to figure out the bug or the error in the firmware
which creates the unexpected behavior.
Debugging Techniques
1. Incremental EEPROM Burning Technique:
• Most primitive technique
• Code is separated into different functional code units.
• Code is burned into EEPROM in incremental order.
• LED or BUZZER provided to indicate correct functioning
• Time Consuming but is a onetime process.
 lOMoARcPSD|42822176

I.RAVI KUMAR
2. Inline Breakpoint Based Firmware Debugging
• An inline debug code is inserted within the firmware at a point where we want to
ensure correct execution
• Debug code is printf() function.
• View debug code generated data on the <Hyper Terminal=
o Configure serial communication setting of the Hyper Terminal
connection to the same as that of serial communication setting
configured in the firmware (Baudrate, Polarity, Stop Bit, Flow Control).
o Connect target board9s serial port to development PC9s COM port using
RS232 cable.
3. Monitor Program Based Firmware Debugging
• Monitor Program which acts as supervisor is developed.
• It controls the downloading of user code into code memory, inspect and modifies
register/memory locations, allow single stepping of source code etc.
• It always listen to serial port of target device and according to command received it
performs command specific actions.
• The first step in any monitor program development is determining a set of
commands for performing various operations like firmware downloading, memory
register inspection/modification, single stepping, etc. Once the commands for each
operation is fixed write the code for performing the actions corresponding to these
commands.
• The commands may be received through any of the external interface of the target
processor (e.g. RS-232C serial interface/parallel interface/USB, etc.).
• The monitor program should query this interface to get commands or should handle
the command reception if the data reception is implemented through interrupts. On
receiving a command, examine it and perform the action corresponding to it.
• The entire code handling the command reception and corresponding action
implementation is known as the "monitor program<.
• After the successful completion of the monitor program development, it is
compiled and burned into the FLASH memory or ROM of the target board. The
code memory containing the monitor program is known as the Monitor ROM
The Monitor program contains the following set of minimal features:
o Command set interface to establish communication with the dubbing application
o Firmware download option to code memory
 lOMoARcPSD|42822176

I.RAVI KUMAR
o Examine and modify processor registers and working memory(RAM)
o Single step program execution
o Set breakup points in firmware execution
o Send debug info to debug application running on host machine
• The monitor program usually resides at the reset vector (code memory 0000H) of
the target processor
• The actual code memory is downloaded into a RAM chip which is interfaced to the
processor in the Von Neumann architecture model.
• The von Neumann architecture model is achieved by ANDing the PSEN and RD
signals of the target processor (In case of 8051) and connecting the output of AND
Gate to the Output Enable (RD) pin of RAM chip. WR signal of the target processor
is interfaced to the WR signal of the Von Neumann RAM.
• An address decoder circuit maps the address range allocated to the monitor ROM
and activate the Chip Select (CS) of the ROM if the address is within the range
specified for the Monitor ROM.
• A user program is normally loaded at location 0x4000 or 0x8000. The address
decoder Circuit ensures the enabling of the RAM chip (CS) when the address range
is outside that allocated to the ROM monitor.
The major drawbacks of monitor based debugging system are
• The entire memory map is converted into a Von Neumann model and it is shared
between the monitor ROM, monitor program data memory, monitor program
trace buffer, user written firmware and external user memory. For 8037, the
original Harvard architecture supports 64K code memory and 64K external data
memory (Total 128K memory map). Going for a monitor based debugging
shrinks the total available memory to 64K Von Neumann memory and it needs
to accommodate all kinds of memory requirement
• The communication link between the debug application running on Development
PC and monitor program residing in the target system is achieved through a serial
link and usually the controller's On-chip UART is used for establishing this link.
Hence one serial port of the target processor becomes dedicated for the monitor
application and it cannot be used for any other device interfacing.
Wastage of serial port! It is a serious issue in controllers or processors with single
UART
 lOMoARcPSD|42822176

I.RAVI KUMAR
4. In Circuit Emulator Based Firmware Debugging
Functional Units
• Emulation Device
• Emulation Memory
• Emulator Control Logic
• Device Adaptors
Emulation Device: replica of target CPU
• Standard Chip
• Programmable Logic Device(PLD)
Emulation Memory: Replacement for EEPROM of target device
• It is the RAM incorporated in the emulator device
• Acts as Trace Buffer. Trace buffer is a memory pool holding the instructions
executed/registers modified/related data by the processor while debugging. The
common features of trace buffer memory and trace buffer data viewing are listed
below. Trace buffer records cache bus cycle in frames. Trace data can be viewed
in the debugger application as Assembly/Source code. Trace buffering can be
done on the basis of a Trace trigger (Event). Trace buffer can also record signals
from target board other than CPU signals. Trace data is a very useful information
in firmware debugging
Device adaptors
• Act as an interface between the target board and emulator POD.
• Normally pin-to-pin compatible sockets which can be inserted/plugged into the
target board for routing the various signals from the pins assigned for the target
processor.
• The device adaptor is usually connected to the emulator POD using ribbon
cables. The adaptor type varies depending on the target processor chip package.
• The above mentioned emulators are almost dedicated ones, meaning they are built
for emulating a specific target processor and have little or less support for emulating
the derivatives of the target processor for which the emulator is built. This type of
emulators usually combines the entire emulation control logic and emulation device
in a single board. They are known as Debug Board Modules (DBMs).
• An alternative method of emulator design supports emulation of a variety of target
processors. Here the emulator hardware is partitioned into two
o Base Terminal
o Probe Card.
 lOMoARcPSD|42822176

I.RAVI KUMAR
• The Base terminal contains all the emulator hardware and emulation control logic
except the emulation chip (Target board CPUs replica). The base terminal is
connected to the Development PC for establishing communication with the debug
application. The emulation chip is mounted on a separate PCB and it is connected
to the base terminal through a ribbon cable.
• The Probe Card board contains the device adaptor sockets to plug the board into the
target development board. The board containing the emulation chip is known as the
Probe Card. For emulating different target CPUs the Probe Card will be different
and the base terminal remains the same.
5. On Chip Firmware Debugging
• Today almost all processors incorporate built in debug modules called On Chip
Debug (OCD) support.
• Though OCD adds silicon complexity and cost factor, from a developer perspective
it is a very good feature supporting fast and efficient firmware debugging.
• The On Chip Debug facilities integrated to the processor/controller are chip vendor
dependent and most of them are proprietary technologies like Background Debug
Mode. Some vendors add 'on chip software debug support through JTAG (Joint Test
Action Group) port.
• Processors/controllers with OCD support incorporate a dedicated debug module to
the existing architecture
• Usually the on-chip debugger provides the means to set simple breakpoints, query
the internal state of the chip and single step through code.
• OCD module implements dedicated registers for controlling debugging.
• An On Chip Debugger can be enabled by setting the OCD enable bit
• BDM and JTAG are the two commonly used interfaces to communicate between
the Debug application running on Development PC and OCD module of target
CPU.
• Background Debug Mode (BDM) interface is a proprietary On Chip Debug solution
from Motorola
• BDM defines the communication interface between the chip resident debug core
and host PC where the BDM compatible remote debugger is running.
• BDM makes use of 10 or 26 pin connector to connect
to the target board.
 lOMoARcPSD|42822176

I.RAVI KUMAR
• Serial data in (DSI), Şerial data out (DS0) and Serial clock (DSLR) are the three
major signal lines used in BDM.
• DSI sends debug commands serially to the target processor from the
remote debugger application
• DSO sends the debug response to the debugger from the processor
• Synchronisation of serial transmission is done by the serial clock DSCLK generated
by the debugger application. Debugging is controlled by BDM specific debug
commands. The debug commands are usually 17-bit wide. 16 bits are used for
representing the command and I bit for status/control.
• Chips with JTAG debug interface contain a built-in JTAG port for communicating
with the remote debugger application.
The signal lines of JTAG protocol are explained below
• Test Data In (TDI): It is used for sending debug commands serially from remote
debugger to the target processor
• Test Data Out (TDO): Transmit debug response to the remote debugger from
target CPU.
• Test Clock (TCK): Synchronizes the serial data transfer
• Test Mode Select (TMS): Sets the mode of testing.
• Test Reset (TRST): It is an optional signal line used for resetting the target CPU.

TARGET HARDWARE DEBUGGING

Firmware is bug free and everything is intact with the board. Still embedded product
need not function as per the expected behavior in the first attempt. This is due to hardware
related reasons like :
• Dry soldering of components
• Missing connections in PCB due to un-noticed error in PCB layout design
• Misplaced components
• Signal corruption due to noise
Hardware Debugging
• The monitoring of various signals of the target board like address/data lines,
checking the inter connection among various components, circuit continuity
checking etc.
• Not similar to firmware debugging
 lOMoARcPSD|42822176

I.RAVI KUMAR
Hardware Debugging Tools
• Magnifying Glass
• Multimeter
• Digital CRO
• Logic Analyser
• Function Generator
Magnifying Glass
• It is a powerful visual inspection tool.
• Used for examining the target board for :
• Dry soldering components
• Missing components
• Improper placement of components
• Improper soldering
• Tracks PCB damage
• Short of track
Multimeter
• Used for measuring various electrical quantities like Voltage, Currents,
Resistance, Capacitance, Continuity checking, Transistor checking, Cathode and
Anode identification of diode etc.
• Primary debugging tool for physical contact based hardware debugging.
• It is mainly used in embedded hardware debugging for:
 Checking the circuit continuity between different points on the board
 Measuring the supply voltage
 Checking the signal value, polarity etc.
 Both analog and digital version are available
Digital Cathode Ray Oscilloscope
Used for
• Waveform capturing and analysis
• Measurement of signal strength
• Analysing interference noise in the power supply line and other signal
lines
• Connecting point under observation on the target board to the channels
of the oscilloscope, waveform can be captured and analysed for
expected behavior.
 lOMoARcPSD|42822176

I.RAVI KUMAR
• Digital CRO are available for high frequency support and incorporates modern
technique for recording waveform over a period
of time, capturing the waves on the basis of a configurable event for target board.
Logic Analyser
• It is similar to CRO
• Used to capture digital data (logic 1 or 0) from digital circuitry, whereas CRO is
used to capture all kind of waves.
• The total no of logical signals that can be captured using CRO is limited to the
no of channels. Logical analyser contain special connectors and chips which can
be attached to the target board for capturing the digital data.
• In target board debugging applications, a logic analyser captures the states of
various port pins, address bus and data bus of the target processor/controller, etc.
• Logic analysers give an exact reflection of what happens when a particular line
of firmware is running.
Function Generator
• Function generator produce various periodic waveforms like sine wave,square
wave, saw-tooth wave etc. with different frequency and amplitude.
• It is not a debugging tool, it is an input stimulator tool.
• The target board requires periodic waveform with particular frequency as input
to some part of the board.