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 INTRODUCTION TO 8096 MICROCONTROLLERS

SALIENT FEATURES :

INTEL 8096 , a second generation processor belongs to 1' CS 96 family. T his is a high
perfonnan ce 16 bit microcontroller witl1 register to register architecture. T his is designed to
handle high speed calcu lations and fast input/output operations which is preferred in high speed
modern c ontrol applications. TI1e 8096 with 16-bit CPU horse power ,high speed math
processing and high speed 1/ 0 is ideal for complex motor control and axis control systems.
Hence it is used in 3 phase large horse power AC motors and robotics TI1e 10-bit ADC option
makes it most suitable candidate for data acquisition systems and closed loop analog controllers.

8096 can be configured in two modes . ( i ) Single chip mode and (ii) Expand ed mode.
Jn the single chip mode the internal ROM or EPROM is accessed by making the pin EA (Active
low) HIGH. For ROl\1 less c hip to access the extemal memory the pin EA is made low. Jn the
expanded mode both internal and ex ternal (OFF CHIP) memory can be accessed using the
multiplexed bus architecture.It has nearly 230 b)1es of on-chip RAl\1 and one 10-bit AID
converter with sample hold circuit. T here are five on chip 1/0 ports each of 8-bit width T he 8096
bit micmcontroller has a complete set of 16-bit arithmetic instructions including multiply and
divide operations. It has Pulse \Vidth 1' odulation Output with dedicated Baud Rate Generator It
has one on c hip Full Duplex S erial Port TI1ere are 20 interrupt sources and 8 interrupt vecrors on
8096. It has two 16-bit Timers Timer I and Timer 2 and one 16 bit watch dog tim er T his 8096 is
available as 48 pin DIP(Dual Jn-line Pac kage) and 68 pin PLCC and also 68 pin leadless c hip
carrier JC. It is also available as a 68 pin PGA(P in Grid Array) package .

ARCIUTECTURE :
8096 is a 16-bit microcontroUer in which the data path for operand s is 16 bits wide i.e when data
is tran sferred between RAl\1 or ROM and the CPU, it is transferred 16 bits per internal memory
cycle. T he 8096 has an internal 8-bit address bu s and can access 2 8 addresses.T he 8096 performs
most of the c alculations in RALU. TI1e RAW conta ins A 17 bit AW One 16 bit program status
word (PS\V) One program c ounter(P C) A loop c ounter and 3 temporary registers. All registers
are 16 bit or 17 bit wide. A separate incre mentor is used for the Program Counter .

PS\V Register :

PS \V Register JS A 16 bit Register, whose lower byte can act as INT_MASK register . Z is the
zero flag N is the negative flag V is the overflow flag VT i the overflow Trap flag C is the c arry
llag I is the global interrupt enable flag S T is the sticky bit, it is set during a right shift
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Two of t he tempor ary r egist e r s have their own shif t logic. The addressable memory space on t he 8096
T
is 64 kB, most of w hich are available to the user fo r pr ogra m or da ta m emory .The loca tions w hich have
special purpose ar eOOOOH through OOFFH and FFFH thr ough 2010 H.A ll ot her locat ions can be used
eit her for progr am or fo r data st o rag e or for memory m apped peripherals .

Memory Mapping: The 64kB memory space mapping is shown in the diagram

EXTERNA L MEMORY F FF F H

OR

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10
INTERNAL PROGRA M

STORAGE ROM

FACTORY TE.ST COOE

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EXTERNAL M EMOR Y RESERVED
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FOR USE BY INT£1. DEVELOPMENT
tHTEAHA L RAM SYSt t MS
R EGISTER FILE: (W HEN A CCESSEO A S PROGAAM
STACK POINTER MEMOAY)
00 SPECIAL FUNCTION REGISTERS OOOOH
CWHEN A CCESSED AS
OATA MEMORY)
Fig. I Memory Mapping

The 8096 has been design ed for high speed /high performan ce control applications. Because tl1e
8096 architectu re is different from that of the 8048 or 805 I The architecture of 8096 has two
major sections one is the CPU section and the other is tl1e 1/ 0 section.T he block diagram is
shown in the figure 2
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Fig.2.Block diagram of 8096 Microcontro ller

CPU O F 8096:

111e 8096 CPU has a 16-bit ALU which operates on a 256-byte re gister me instead of an
accumulator. Any of the locations in the register file c an be used for sources or destinations for
most of the instructions. Hence this is c alled a register to register architecture. Many of the
instructions c an also use bytes or words from anywhere in the 64K byte address space as
operands. Locations OOh through 17H are the 1/ 0 control re gisters or special fun ction
registers(SFRs) Locations I 8H and ! 9H contain the stack pointer which serves as gen eral
purpose RAM when not performing the stack operations. 111e remaining b)1es of the re gister file
serves as general purpose RAM ,accessible as bytes,won:J s or double-words. Calculations
perfom1ed by the CPU takes place in the RALU .T his RALU contains a 17 bit ALU ,the program
status won:I (PS \V),the program Counter(PC),a loop counter and three temporary registers. 111e
RALU operates directly on the register files, thus eliminating the problem with Accumulator and
providing direct control of 1/0 operations through the SFRs.

IIO FEATURES :

Most of the 1/0 features on the 8096 are designed to operate with linle CPU intervention. The
\Vatchdog Timer is an internal timer which c an be used to reset the system if the software fails to
operate properly. The Pulse-\Vidth-Modulation (P \VM) output can be used as a rough D to A, a
motor driver, or for many other pu rposes. . The A to D conve rter (ADC) has 8 multiplexed inputs
and 10-bit resolution. The serial port has several modes and its own baud rate generator. The
High Speed 1/0 section includes a 16-bit timer, a 16-bit cou nter, a 4-input programmable e dge
detector, 4 software timers, and a 6-output programmable event generator

P\VM OUTPUT:

Analog outputs are ju st as important as analog in puts when connecting to a peripheral device.
True digital to analog converters are difficult to make on a roicrocontroller because of all of the
digital noise and the necessity of providing an on chip, relatively high current, rail to rail driver.
TI1ey also take up a fair amount of silicon area which can be bener u sed for other features. The A
to D converter does use a D to A, but the currents involve d are very small. The P \VM signal is a
variable duty cycle, fixe d frequency waveform that c an be integrated IO provide an
approximation to an analog ou tput. The frequ ency is fixed at a period of 64 microseconds for a
12 MHz clock speed. Controlling the P \VM simply requires writing tl1e desired duty cycle value
(an 8-bit value) to the P \VM Register.

General Purp ose J/O PORTS :

TI1ere are five 8-bit 1/0 Ports namely Port 0, Port I, Port 2, Port 3 and Port 4 .

PORT O
Port 0 is only an Input port which i also used as the analog input port for the on chip ADC. So,
if the analog input features are not used ,the Port 0 Can be used as in put port only .Port 0 is
shown in Fig 3

PORT 1:
This is a q uasi bidirectional port which c an be used either as input or as the out port. It is
mapped It is mapped at the memory address OFH. If any of the port I pin is to be used as input
port the corresponding pin rou st be made high by writing the data I . The weak internal pullu p is
designed to be ove rridden by the e xternal device which drives the line. \Vhen the ou tput drive
capability is sufficient to drive a 74 LSxx Input a CMOS device driven by port I will require a
pullup resistor of around IOK to +5V in order to bring the output up well above the normal
CMOS threshold voltage of 2.S volts.Portl inputs c an be driven by either CMOS or I T L devices
with no e xtra parts. Port I is shown in Fig 4 .

PORTO (OOOF)
ACH7 7 ,'
ACH6 6 6
ACH5 5 5 ,
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8096 8096
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Fig 3 . PORT 0 Fig 4.Port 1

PORT Z:
The Port 2 has four input lines, two output lines andtwoquasi bidirectional 1/ 0 lines a.s shown in the Fig.
One or more of these six lines can be used f or alternate purpose of PWM ,RXD,TXD, Timer 2 Inputs etc..

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PORT3 & PORT 4:
The Port3 & Port4 are similar in use.Both of them have open drain outputs. By writing I to any
line it c an be used as an input and other lines can serve as output lines. Eac h output line require a
pullup resistor of about ISK.In the e xpansion mode ,tl1e bus lines can gain the ability to drive
both high and low ,forming the expansion bu s without the need of pullup resistors.

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RESETS AND SELFPROT ECTION OPTIONS:

RESETS AND SELFPROTECTION OPTIONS \Vhen the reset pin is driven to low the 8096,
regardless of what it is doing will reset and start executing from tl1e address 2080H.The reset pin
is a bidirectional line with a strong internal pullup.T his line may also be driven by internal
watchdog timer also.The INTEL 8096 microcontroller is provided with on chip self protection
circuitary , to protect the chip from large currents. The chip is automatically reset when the Vdd
deviates from the prescribed levels. Diode circuits are provided on the chip itself ,which gives
self protection.

JUGH SPEED INPUT UNIT:

HIGH SPEED INPUT UNIT This unit is used to record the time at which an external event
occu rs with respect to timer I . It can monitor four in depen dently configu rable HSI lines and
capture the value of Timer I when an eve nt takes place. There are 4 lines (HIS.O-HIS.3)available
in this unit .The HIS u nit can store upto 8 entries(Timer I values) . The HSI unit can generate an
interru pt when loading an entry into the HIS holding register or loading the six th e ntry into the
FIFO. Th e fou r types o f events that c.an trigger captures include "rising edges only", " falling
edges only'',"rising or falling edges" or every eighth rising edge.

JUGH SPEED OUTPUT UNIT:

TI1is HSO u nit is used to trigger eve nts at specified tim es based on Timer I or Timer 2 with
minimal CPU over-head. The 4 events are Starting an AID conversion Resening of Timer2
Sening four software llags Switching six output li nes (HS0 .0-HS 0.5). TI1e HSO unit stores
pending events and the specified time s in a Content Addressable Memory(CAM) file. TI1is
CAM file stores u p to 8 commands. E.ach command specifies the action time,the nature of the
action ,whether an interrupt is to occur and whether Tim er I or Timer 2 is the reference Timer.
For every 8 state times the HSO compares the CAM locations for the time matches. The HSO unit
ca n gener ate two types of interrupts ( i ) HSO execution interrupt (Vector = 2006H) (ii) Software Tim er
interrupt(Vecto r =200BH )

TIMERS:
INTEL 8096 controller has two on chip 16-bit timers TIMER I & TIMER 2 Tlli1ER I can act as
a 16-bit counter also and can be clocked at every 2 ms. i.e for every 8-internal clock cycles. This
Timer is used in conj un ction with high speed 1/0 system. \Vhen Timer I is over flown ,the
interru pt bit is e nabled or disabled .. TIMER 2 c an be used as a 16-bit even counter which is
clocked by a signal coming into the chip on either of the two pinsPort2.3 or HIS. I TI1e choice
between the two clock sou rces is made by sening or clearing bit 7 of the JOC.OTimer 2 is
counted on both the rising edges and falling e dges of the in put signal and the minimum time
between edges is 2 micro seconds.

\VATCH DOGTIMER:
An on c hip 16-bit watch dog timer is available in 8096 which helps to recover the controller
from the software upsets. This 16-bit \VDT is a counter which is incremented every state time.
TI1is counter is cleare d by program after periodic interval and not allowed to overflow . However
, if the program does not progr ess properly by any r eason such as Electrostat ic Discharge(ESD) or due
to any hardware related problems ,tl1e overflow occurs. And the hardware reset is initiated to
restart the microcontroller . This process avoids the system from having a malfunction for longer
than 16mS under 12MHz frequency operation \Vhen the \VDT overflows ,it pulls down the
RESET pin for at least two state times resening 8096 and also any other devices connected to the
RESET line.

INTERRUPT STRUCTURE:

TI1ere are 20 different interru pt sources tl1at can be used on the 8096. The 20 sources vector
through 8 locations or interrupt vectors. All these interrupts are enabled or disabled using the 9 th
bit of PS \V register. If this bit is set to I all the interru pts are enabled and disabled when reset to
zero.Control of the interrupts is handled through the Interrupt Pend ing Register
(INT_PENDING), the Interrupt Ma k Register (INT_MASK), and the I bit in the PSW (PS \V.9).
TI1e content of the interrupt ma k register determine whether the pending interrupt is serviced or
not. If it is to be serviced , the CPU pushes the contents of the program cou nter on to the stack
and reloads it with the vector corresponding to the desired interrupt. \Vhen the hardware detects
one of the 8 interrupts , it sets tl1e correspond ing bit in the interrupt pending register .TI1is
register can be read or modified as a b)t e register. Individual interrupts can be enabled or
disabled by sening or clearing the bits in the Interrupt mask register. The INT_MASK register
can be accessed as the lower bits of the PS \V register.

SERIAL PORT:

TI1e 8096 has an on-chip full duplex serial port to reduce the total number of c hips required in
the system.TI1e serial port is similar to that on the 805 1controller. . It has one synchronous and
three asynchronous modes. Jn the asynchronous modes baud rates of up to 187 .S K baud c an be
used, while in the synchronous mode rates up to 1.5 M bau d are available. The c hip has a baud
rate generator which is independent of Timer I and Timer 2, so using the serial port does not
take away any of the HSI, HSO or timer flexibility or functionality. Control of the serial port is
provided through the SPCON/SPSTAT (Serial Port CONtrol /Serial Port STATus ) regL ter. TI1e
serial port is configured in four modes. The four modes of the serial port are referred to as modes
0, I, 2 and 3. f.1ode 0 is the synchronous mode, and is commonly used to interface IO shift
registers for 1/ 0 ex pansion. Jn this mode the port outputs a pulse train on the TXD pin and either
transmits or receives data on the RXD pin. Mode I is the standard asynchronous mode, 8 bits
plus a stop and start bit are sent or received .. Modes 2 and 3 han dle 9 bits plus a stop and start
bit. The difference between the two is, that in Mode 2 the serial port interrupt will not be
activated unless the ninth data bit is a one; in Mode 3 the interru pt is activated whenever a byte L
received. These two modes are comm only used for interprocessor communication. Baud rates
for all of the modes are controlled through the Baud Rate register. This is a b)te wide register
which is loaded sequentially with two bytes, and intemally stores the value as a word. The least
significant byte is loaded to the register followed by the most significant. The most significant bit
of the baud value determines the clock source for tl1e baud rate generator. lfthe bit is a one, the
XTAL I pin is used as the source, if it is a zero, the T2 CLK pin is used .

ADDRESSING MODFS:

TI1e 8096 instruction set suppotts six addressing modes. TI1ey are

Immediate addressing mode

Register direct addressing mode

Indirect addressing mode

Indirect with auto increment mode

Short indexed mode and

Long indexed mode.

TI1ese addressing modes increase the flexibility and overall execution speed of 8096 controller.
Each instruction uses at least one of the addressing modes. The register , direct and immediate
addressing modes e xecute faster than the other addressing modes. Both of the indirect addressing
modes use the value in a word register as the address of the operand. The indirect auto increment
mode ,increments a word address by one after a byte operation and two after a word operation.

A to D CONVERTER :
Analog in puts are frequen tly required in every microcontroller application . TI1e 8096 controller
has one 10 bit on chip AID converter that can use any one of eight input c hannel . The
conversions are done using the successive approx imation method, and requ ire 168 state times (42
microseconds with a 12 MHz clock.). The main compon ents of the AID conve tter are 8-analog
input chann els One 8 to I multiplexe r. A sample and hold c apacitor and Resistor ladder TI1e AID
convetter perf orms a conversion in 88 time states .Upon the completion of eac h conversion the
C0£1verter cart generate a cor1versior1complete ir1terrupt .

REFERENCES:
1. Design w ith M icrocont rollers - John . B. Peatman - M c .Graw -Hill International Ed.

2.lntel Application note & da ta sheet .