An Autonomous Institution

Approved by AICTE, Affiliated to Anna University, Chennai.

ISO 9001:2015 Certified Institution, Accredited by NBA (BME, CSE, ECE, EEE, IT & MECH),
Accredited by NAAC with 'A' Grade with CGPA of 3.49.
#42, Avadi-Vel Tech Road, Avadi, Chennai- 600062, Tamil Nadu, India.

191EC21B DIGITAL SYSTEM LABORATORY

NAME :
REGISTER NO :
ROLL NO : VM -
BRANCH : B.Tech – INFORMATION TECHNOLOGY
YEAR :
SEMESTER :
REGULATION : 2019
 DEPARTMENT OF INFORMATION TECHNOLOGY

VISION

• To emerge as center for academic eminence in the field of information technology

through innovative learning practices.

MISSION
• To provide good teaching and learning environment for quality education in the field of
information technology.
• To propagate lifelong learning.
• To impart the right proportion of knowledge, attitudes and ethics in students to enable
them take up positions of responsibility in the society and make significant
contributions.

1
 DEPARTMENT OF INFORMATION TECHNOLOGY

Program Outcomes (POs): Based on these Graduate Attributes Program Outcomes (POs)
POs Program Outcomes
1 Engineering Knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals and an engineering specialization to the solution of complex engineering
problems.
2 Problem Analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.
3 Design / Development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs
with appropriate consideration for the public health and safety, and the cultural,
societal, and environmental considerations
4 Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
5 Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
6 The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
7 Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.

9 Individual and team work: Function effectively as an individual and as a member or

leader in diverse teams, and in multidisciplinary settings.

10 Communication: Communicate effectively on complex engineering activities with

the engineering community and with society at large, such as, being able to
comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
11 Project management and finance: Demonstrate knowledge and understanding of the
engineering management principles and apply these to one’s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
12 Life-long learning: Recognize the need for and have the preparation and ability to
engage in independent and lifelong learning in the broadest context of technological
change.
have been framed by NBA:

2
PROGRAMME SPECIFIC OUTCOMES (PSOs):

PROGRAMME SPECIFIC OUTCOMES

PSO’s
(PSOs)

An ability to apply design and development principles in the construction of

PSO1
software systems of varying complexity.

The use of current application software, the design and use of operating
PSO2 systems and the analysis, design, testing, and documentation of computer
programs for the use in information engineering technologies.

The design techniques, analysis and the building, testing, operation and
PSO3 maintenance of networks, databases, security and computer systems (both
hardware and software).

PROGRAMME EDUCATIONAL OBJECTIVES (PEOs):A graduate of the Electronics and

Communication Engineering Program will have:

PEOs Topic of PEO Programme Educational Objectives (PEOs)

The graduates of Information Technology Engineering
Program should be able to Excel in professional carrier and or
PEO1 Preparation
higher education by acquiring knowledge in mathematical,
computing and engineering principles.
The Graduates of Information Technology Engineering
Program should have an exposure to emerging cutting edge
PEO2 Expertise technologies, adequate training and opportunities to work as
teams on multidisciplinary projects with effective
communication skills
The Graduates of Information Technology Engineering
Program should be able to establish an understanding of
PEO3 Professionalism
professionalism, ethics, public policy and aesthetics that
allows them to become good professional Engineers.
The graduates should be able to advance professionally
PEO4 Learning through organized training or self-learning in areas related to
computer science and information technology.
The graduates of Information Technology Engineering
Program should be able to develop an ability to analyze the
PEO5 Breadth requirements, understand the technical specifications, design
and provide novel engineering solutions and produce efficient
product designs.

3
191EC21B / DIGITAL SYSTEM DESIGN LABORATORY COURSE
OUTCOMES:At the end of the course

Course Course Outcome statements

Outcome
CO1 Design and Implement Simplified combinational circuits using logic gates and MSI Devices
CO2 Design and Implement sequential circuits like Register and counter
CO3 Simulate Combinational and Sequential circuits using HDL.

CO’S –PO’S MATRICES

Course MAPPING CO’S WITH PO’S

Outcome
PO 1

PO 2

PO 3

PO 4

PO 5

PO 6

PO 7

PO 8

PO 9

PO

PO

PO
10

11

12
CO1 3 2 3 - 2 - - - 2 2 - 2
CO2 3 2 3 - 2 - - - 2 2 - 2
CO3 3 2 3 - 2 - - - 2 2 - 2

*NOTE : 1- Slight (low) 2- Moderate (Medium) 3- Substantial (High)

CO’S –PSO’S MATRICES

Course MAPPING CO’S

Outcome WITH PSO’S
PSO 1

PSO 2

PSO 3

CO1 3 2 2
CO2 3 2 2
CO3 3 2 2

4
191EC21B / DIGITAL SYSTEM DESIGN LABORATORY L:T:P:C
0:0:2:1

OBJECTIVES:

• To understand the various basic logic gates

• To design and implement the various combinational circuits
• To design and implement combinational circuits using MSI devices.
• To design and implement sequential circuits
• To understand and code with HDL programming

LIST OF EXPERIMENTS:

1. Verification of truth tables of logic gates and theorems of Boolean algebra.

2. Design of half adder, full adder and parallel binary adder.
3. Design of BCD adder
4. Design of 8 to 1 multiplexer and make use of it to implement a full adder.
5. Design of decimal to binary encoder.
6. Design of 2-bit magnitude converter.
7. Design of 4-bit ripple up and down counters
8. Design of 4-bit shift register, ring counter and Johnson counter.
9. Simulation of a 4-bit parallel binary adder using HDL.
10. Simulation of a multiplexer and decoder using HDL.

OUTCOMES:
Upon Completion of the course, the students will be able to:
• Implement simplified combinational circuits using basic logic gates.
• Implement combinational circuits using MSI devices.
• Implement sequential circuits like registers and counters.
• Simulate combinational and sequential circuits using HDL.

5
EX.NO: 1 VERIFICATION OF TRUTH TABLES OF LOGIC GATES
DATE: AND THEOREMS OF BOOLEAN ALGEBRA

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

S. No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

FORMULA REQUIRED:

INVOLUTION
COMMUTATIVE X+Y=Y+X
ASSOCIATIVE X+(Y+Z)=(X+Y) +Z
X (YZ)= (XY) Z
ABSORPTION X+XY=X

DEMORGAN’S LAW

6
THEORY
Circuit that takes the logical decision and the process is called logic gates. Each gate has
one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR are
known as universal gates. Basic gates are derived from these gates.
AND GATE
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs
is low.

OR GATE
The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.
NOT GATE
The NOT gate is called an inverter. The output is high when the input is low. The output is low
when the input is high.
NAND GATE
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR GATE
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
X-OR GATE
The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.
Boolean algebra is defined as a Set of Elements, a Set of Operations and a Number of Approved
Axioms and Postulate.
A Set of Elements in any collection of object having a Common Property. It is a Set X
and Y are Certain Objects then they belong to S, denotes that X is a Member Of Set S and Y
belong To S denotes that X is A Member Of Set S. A Set is a Denumerable to Elements is
specified by Braces A= {1, 2, 3, 4}.
The elements of the Set A are No’s 1,2,3,4. A Binary Variable takes any Value from 0 to 1. A
Boolean Function is an Expression formed with Binary Variable that consists of two Binary
Variable, the binary Operator Or and And, the Unary Operator Value.
Boolean algebra is an Algebraic Function defined on a Set of Elements together with 2
Binary Operator ‘.’ and ‘+’ Boolean algebra Manipulation.
7
AND GATE
SYMBOL PIN DIAGRAM

OR GATE

8
NOT GATE

SYMBOL PIN DIAGRAM

X-OR GATE
SYMBOL PINDIAGRAM

9
2-INPUT NAND GATE

SYMBOL PIN DIAGRAM

3-INPUT NAND GATE

10
NOR GATE

INVOLUTION LAW TRUTH TABLE

X= (X’)’
X X’ (X’)’
IC7404 IC7404
0 1 0
1 0 1

COMMUTATIVE LAW

X+Y=Y+X

RHS

LHS
11
 0 0 0 0
0 1 1 1
TRUTH TABLE 1 0 1 1
1 1 1 1

X Y X+Y Y+X

ASSOCIATIVE LAW
TRUTH TABLE X Y Z X+Y Y+Z X+(Y+Z) (X+Y)+Z
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 1 1 1 1
X+(Y+Z) =(X+Y) +Z 0 1 1 1 1 1 1
1 0 0 1 0 1 1
RHS 1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1

LHS

DEMORGAN’S LAW

(i) (X+Y)=X. Y

RHS LHS

2
TRUTH TABLE

X Y X’ Y’ (X+Y) (X+Y)’ X’.Y’

0 0 1 1 1 0 0
0 1 1 0 1 0 0
1 0 0 1 1 0 0
1 1 0 0 0 1 1

(ii) (XY)’ =X’+Y’

RHS

LHS
TRUTH TABLE

X Y X’ Y' X’+Y’ XY (XY)’

0 0 1 1 1 0 1
0 1 1 0 1 0 1
1 0 0 1 1 0 1
1 1 0 0 0 1 0

ABSORPTION LAW TRUTH TABLE:

X Y XY X+XY
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1

2
PROCEDURE

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT
Thus the truth tables of basic gates are verified.

2
EX.NO: 2 DESIGN AND IMPLEMENTATION OF HALF ADDER

DATE: FULL ADDER AND SUBTRACTOR USING BASIC GATES

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor circuits
and verify the truth table using logic gates.

APPARATUS REQUIRED:

S.No COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - AS PER
CIRCUIT
DIAGRAM

THEORY:
HALF ADDER

A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ C’ into the higher adder position. Above circuit is called as a
carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out
from the AND gate.

FULL ADDER

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken
from OR Gate.

3
HALF SUBTRACTOR

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.

FULL SUBTRACTOR

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half subtractor put
together gives a full subtractor .The first half subtractor will be C and A B. The output will be
difference output of full subtractor. The expression AB assembles the borrow output of the half
subtractor and the second term is the inverted difference output of first X-OR.

LOGIC DIAGRAM

HALF ADDER

TRUTH TABLE

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

4
 K-Map for SUM K-Map for CARRY

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:FULL ADDER

FULL ADDER USING TWO HALF ADDER

TRUTH TABLE

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM

5
 SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY

CARRY = AB + BC + AC

LOGIC DIAGRAM

HALF SUBTRACTOR

TRUTH TABLE

A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

6
K-Map for DIFFERENCE K-Map for BORROW

DIFFERENCE = A’B + AB’ BORROW = A’B

LOGIC DIAGRAM
FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

7
TRUTH TABLE

A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow

2
Borrow = A’B + BC + A’C

3
PROCEDURE

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT

Thus the truth table of half adder and half subtractor, full adder and full subtractor have
been verified using basic gates.

4
EX.NO: 3 DESIGN &IMPLIMENTATION OF BCD ADDER

DATE:

AIM
To design and implement 4-bit adder and subtractor using basic gates and MSI devices.

APPARATUS REQUIRED

S.No. COMPONENT SPECIFICATION QTY

1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - AS PER
CIRCUIT
DIAGRAM

THEORY

4 BIT BINARY ADDER

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry from
each full adder connected to the input carry of next full adder in chain. The augends bits of ‘A’
and the addend bits of ‘B’ are designated by subscript numbers from right to left, with subscript
0 denoting the least significant bits. The carries are connected in chain through the full adder.
The input carry to the adder is C0 and it ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR
The circuit for subtracting A-B consists of an adder with inverters, placed between each
data input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1
when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is
adder circuit. When M=1, it becomes subtractor.
5
PIN DIAGRAM FOR IC 7483

LOGIC DIAGRAM

4-BIT BINARY ADDER

6
7
LOGIC DIAGRAM

4-BIT BINARY SUBTRACTOR

8
TRUTH TABLE

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

9
PROCEDURE

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table.

(iii) Observe the logical output and verify with the truth tables.

RESULT

Thus the truth table of 4-bit adder and 4-bit subtractor has been verified using MSI
devices.
10
EX.NO:4 DESIGN OF 8 TO 1 MULTIPLEXER AND MAKE USE OF IT TO
IMPLEMENT A FULL ADDER

DATE:

AIM
To design and implement Realization of Boolean expression using 8:1 Multiplexer
74151

APPARATUS REQUIRED

S.No. COMPONENT SPECIFICATION QTY

1. IC IC 74151, IC 7404, IC 1
7432,
2. DIGITAL TRAINER - 1
BOARD
3. PATCH CORDS - AS PER
CIRCUIT
DIAGRAM
4 POWER SUPPLY +5V 1

THEORY
What is multiplexer?
Multiplexer is a digital switch which allows digital information from several sources to be
routed onto a single output line. Basic multiplexer has several data inputs and a single output
line.The selection of a particular input line is controlled by a set of selection line.
n
There are 2 input lines & n is the number of selection line whose bi combinations determines
which input is selected .It is ―Many into One‖.
Strobe: - It is used to enable/ disable the logic circuit OR ‗E‘ is called as enable
I/P which is generally active LOW. It is used for cascading MUX is a single
pole multiple way switch.

8:1 MUX:
The block diagram of 8:1 MUX & its TT is shown. It has eight data
I/P & one enable input, three select lines and one O/P.

Operating principle:

11
When the Strobe or Enable input is active low, we can select any
one of eight data I/P and connect to O/P.
DESIGN:

PIN DIAGRAM OF 8:1 MULTIPLEXER:

12
13
FIG 8:1 MULTIPLEXER:

14
 SELECTION STROBE
LINES OUTPUTS
_
C B A E Y Y
X X X 1 0 1
0 0 0 0 D0 D0
0 0 1 0 D1 D1
0 1 0 0 D2 D2
0 1 1 0 D3 D3
1 0 0 0 D4 D4
1 0 1 0 D5 D5
1 1 0 0 D6 D6
1 1 1 0 D7 D7

PROCEDURE

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table.

(iii) Observe the logical output and verify with the truth tables.

RESULT

Thus the truth table of 8:1 Multiplexer 74151 has been verified .
15
EX.NO:5 DESIGN OF DECIMAL TO BINARY ENCODER

DATE:

AIM
To design and implement Realization of Decimal to Binary Encoder using 74147

COMPONENTS REQUIRED:

Serial No. Component Description IC No. Required No.

1 10-line to 4-line Priority Encoder 7447 1
2 8-line 3-line priority encoder LT 542 1
3 Patch Chords ---- 20
4 IC Trainer Kit ---- 1

DECIMAL TO BCD PRIORITY ENCODER.

16
TRUTH TABLE
Inputs Outputs
I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A1 A0
X X x x X x x x 0 0 1 1 0
X X x x X x x 0 1 0 1 1 1
X X x x X x 0 1 1 1 0 0 0
X X x x X 0 1 1 1 1 0 0 1
X X x x 0 1 1 1 1 1 0 1 0
X X x 0 1 1 1 1 1 1 0 1 1
X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1

PROCEDURE:

1.Verify all the components and patch chords whether

they are in good condition.
2.Make connections as shown in the circuit diagram.
3.Give supply to the trainer kit & feed active low input
bit combinations.
4.Verify the truth table sequence and observe the
outputs.

RESULT

Thus the truth table of decimal to binary encoder of 74147 has been verified .

17
 EX. NO: 6 DESIGN AND IMPLEMENTATION OF 2 BIT MAGNITUDE
COMPARATOR
DATE:

AIM
To design and implementation of 2 – bit magnitude comparator using basic gates.
APPARATUS REQUIRED

S.No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY
The comparison of two numbers is an operator that determines one number is greater
than, less than (or) equal to the other number. A magnitude comparator is a combinational
circuit that compares two numbers A and B and determines their relative magnitude.
The outcome of the comparator is specified by three binary variables that indicate
whether A>B, A=B (or) A<B.

A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational circuit
designated by the symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of pairs of
significant digits starting from most significant position. A is 0 and that of B is 0.

We have A<B, the sequential comparison can be expanded as

18
 A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0

The same circuit can be used to compare the relative magnitude of two BCD digits.
Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

   
x3 x2 x1 x0

LOGIC DIAGRAM
2 BIT MAGNITUDE COMPARATOR

19
K –MAP FOR A> B

K –MAP FOR A<B

20
K –MAP FOR A= B

21
TRUTH TABLE

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

22
PROCEDURE

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT

Thus the truth table of 2-bit magnitude comparator has been verified using basic gates
and MSI devices.

23
 EX.NO: 7 DESIGN AND IMPLEMENTATION OF 4 BIT RIPPLE UP AND
DOWN COUNTER

AIM
To design and verify 4 bit ripple up and down counters.

APPARATUS REQUIRED

S.No. COMPONENT SPECIFICATION QTY

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - As per circuit
diagram

THEORY

A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There
are two types of counter, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then
each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of
second stage is triggered by output of first stage. Because of inherent propagation delay time all
flip flops are not activated at same time which results in asynchronous operation.

PIN DIAGRAM FOR IC 7476

24
LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER

TRUTH TABLE

25
 CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1

BINARY RIPPLE UP-COUNTER:

We will consider a basic 4-bit binary up counter, which belongs to the class of asynchronous
counter circuits and is commonly known as a ripple counter. Since a flipflop has two states, a
counter having n flip-flops will have 2n states. Hence, in this case the counter will have 24 or 16
states.
The schematics below shows a 4-bit up-counter implemented with four JK flipflops. It can be
noticed that the normal output of each flip-flop is connected to the clock input of next flip-flop.
Please recall that in case of JK flip-flop, with J=K=1, if an input clock pulse is supplied, the
output toggles during the positive or negative (which is the case here, i.e. transition of pulse
from 1 to 0) edge of the pulse. The count held by this counter is read in the reverse order from
the order in which the flip-flops are triggered. Thus, output Q3 is the highest order of the count,
while output Q0 is the lowest order. The binary count held by the counter is then
Q=Q3Q2Q1Q0.
Let us start from the reset condition of all the flip-flops so that counter reads 0000 (decimal 0).
When the trailing or negative end of the first pulse arrives, the first flip-flop gives an output
Q0=1, which does not affect the second flip-flop and the counter reads 0001. The counting
sequence corresponding to each input pulse is summarized in the table below. On supplying
26
15th pulse the counter reads 1111 (decimal 15). The next clock pulse after count 1111 will
cause the counter to try to increment to 10000 (decimal 16). However, that 1 bit is not held by
any flip-flop and is therefore lost. As a result, the counter actually reverts to 0000, and the count
begins again.
Circuit Diagram:

Binary ripple Down-counter: The binary ripple down-counter decreases the count by one each
time a pulse occurs at the input. The only difference it has from the up-counter is that the
complement output of one flip-flop is connected to the clock input of the subsequent flip-flop.
Here the complement output toggles at each negative edge of the clock pulse (1 to 0 transition),
which is equivalent to a normal output toggling for positive edge of the clock pulse (0 to 1
transition). The counter starts from 1111 with the first pulse after it is reset and reverts back to
0000 after 15 pulses.

27
28
PROCEDURE

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT

Thus the truth table of 4 bit Ripple Up and Down counter has been verified.

29
EX.NO:8 DESIGN AND IMPLEMENTATION OF SHIFT REGISTER,RING

COUNTER AND JOHNSON COUNTER.

DATE:

AIM
To design and implement
ring counter and Johnson counter.

(i) Serial in serial out

(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED

S.No. COMPONENT SPECIFICATION QTY

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - AS PER
CIRCUIT
DIAGRAM

THEORY

A register is capable of shifting its binary information in one or both directions is known
as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop. The simplest possible shift register is
one that uses only flip flop. The output of a given flip flop is connected to the input of next flip
flop of the register. Each clock pulse shifts the content of register one bit position to right.

30
PIN DIAGRAM

LOGIC DIAGRAM

SERIAL IN SERIAL OUT

31
TRUTH TABLE
Serial in Serial out
CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

LOGIC DIAGRAM
SERIAL IN PARALLEL OUT

32
TRUTH TABLE
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGIC DIAGRAM
PARALLEL IN SERIAL OUT

TRUTH TABLE

CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

33
LOGIC DIAGRAM
PARALLEL IN PARALLEL OUT

TRUTH TABLE

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

Circuit Diagram: - Ring Counter

34
Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 0 1 0 0
0 3 0 0 1 0
0 4 0 0 0 1
0 5 1 0 0 0
0 6 repeats

Johnson Counter:-

Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 1 1 0 0
0 3 1 1 1 0
0 4 1 1 1 1
0 5 0 1 1 1
0 6 0 0 1 1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0
0 10 repeats

35
PROCEDURE

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT

Thus the truth tables of shift registers have been verified.

36
.

EX.NO:9 SIMULATION OF A 4 BIT PARALLEL BINARY ADDER USING HDL

DATE:

AIM
To design and construct 4bit parallel circuits using HDL coding and verify the truth
table.

SOFTWARE USED

• PC with Windows XP
• XILINX 8.2 i SOFTWARE

THEORY
HALF ADDER

A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a
carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out
from the AND gate.
FULL ADDER

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken
from OR Gate.

HALF SUBTRACTOR
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.
FULL SUBTRACTOR:

37
 The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half subtractor put
together gives a full subtractor .The first half subtractor will be C and A B. The output will be
difference output of full subtractor. The expression AB assembles the borrow output of the half
subtractor and the second term is the inverted difference output of first X-OR.
PROGRAM
HALF ADDER
module HalfAddr(sum, c_out, i1, i2);
output sum;
output c_out;
input i1;
input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule
TRUTH TABLE
Half Adder
------------------------------------------------------------------
Input1 Input2 Carry Sum
------------------------------------------------------------------
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
------------------------------------------------------------------

OUTPUT WAVE

38
FULL ADDER

PROGRAM
module FullAddr(i1, i2, c_in, c_out, sum);
input i1;
input i2;
input c_in;
output c_out;
output sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule

39
TRUTH TABLE
FULL ADDER
i1 i2 C_in C_out Sum
-----------------------------------------------------------------------------
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
-----------------------------------------------------------------------------
OUTPUT WAVE

HALFSUBTRACTOR

PROGRAM
module HalfSub(i0, i1, bor, dif);
input i0;
input i1;
output bor;
40
 output dif;
wire i0n;
not(i0n,i0);
xor(dif,i0,i1);
and(bor,i0n,i1);
endmodule
TRUTH TABLE
HALF SUBTRACTOR
------------------------------------------------------------------------
Input1 Input2 Borrow Difference
-------------------------------------------------------------------------
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
------------------------------------------------------------------------
OUTPUT WAVE

FULL SUBTRACTOR

41
PROGRAM
module FullSub(b_in, i1, i0, b_out, dif);
input b_in;
input i1;
input i0;
output b_out;
output dif;
assign {b_out,dif}=i0-i1-b_in;
endmodule
TRUTH TABLE
FULL SUBTRACTOR
B_in I1 i0 B_out Difference
-----------------------------------------------------------------------------
0 0 0 0 0
0 0 1 0 1
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 1 0
1 1 1 1 1
----------------------------------------------------------------------------
OUTPUT WAVE

42
MULTIPLIXER

TRUTH TABLE
4to1 Multiplexer
-----------------------------------------------
Input=1011
-----------------------------------------------
Selector Output
-----------------------------------------------
{0,0} 1
{1,0} 0
{0,1} 1
{1,1} 1
-----------------------------------------------
OUTPUT WAVE

PROGRAM :Using if statement

module mux (a, b, c, d, s, o);

43
 input a,b,c,d;
input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
if (s == 2’b00)
o = a;
else if (s == 2’b01)
o = b;
else if (s == 2’b10)
o = c;
else
o = d;
end
endmodule]
Using Case statement
module mux (a, b, c, d, s, o);
input a, b, c, d;
input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
case (s)
2’b00 : o = a;
2’b01 : o = b;
2’b10 : o = c;
default : o = d;
endcase
end
endmodule
44
DEMULTIPLEXER
PROGRAM
module Dux1to4(in, s0, s1, out0, out1, out2, out3);
input in;
input s0;
input s1;
output out0;
output out1;
output out2;
output out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule

45
TRUTH TABLE
DEMULTIPLEXER
-----------------------------------------------
Input=1
-----------------------------------------------
Status Output
-----------------------------------------------
{0,0} 1000
{0,1} 0100
{1,0} 0010
{1,1} 0001
OUTPUT WAVE

46
PROCEDURE
1) Open the project navigator.

2) Go to the file,open new project.

3) Type the program name and change the option to HDL

4) Click next to all other window that appear and finally finish

5) Go to the project and select new source

6) Type the file name and select HDL

7) Type the HDL coding in the window appears.

8) Go to the synthesis-XST and run the implementation design in the process window.

9) Click view RTL synthesis and verify the circuit diagram generated.

RESULT:
Thus simulation of 4bit parallel binary adder using HDL has been completed.

47
EX.NO:10 SIMULATION OF A MULTIPLEXER AND DECODER USING HDL
DATE:

AIM
To design sequential circuits using HDL coding and verify their truth tables.

SOFTWARE USED

• PC with Windows XP
• XILINX 8.2 i SOFTWARE

PROGRAM FOR 8:1 MULTIPLEXER:

module 8x1 mux(I,sel,y);

input[7:0]I;
input[3:0]sel;
output y;
reg y;
always @ (sel)
begin
case(sel)
3’b000:begin y=i[0]; end
3’b001:begin y=i[1]; end
3’b010:begin y=i[2]; end
3’b011:begin y=i[3]; end
3’b100:begin y=i[4]; end
3’b101:begin y=i[5]; end
3’b110:begin y=i[6]; end
3’b111:begin y=i[7]; end
endcase
end
endmodule

48
PROGRAM FOR 3:8 DECODER:
module decoder(d,x,y,z);
output [7:0] d;
input x,y,z;
assign d[0] = ~x & ~y & ~z;
assign d[1] = ~x & ~y & z;
assign d[2] = ~x & y & ~z;
assign d[3] = ~x & y & z;
assign d[4] = x & ~y & ~z;
assign d[5] = x & ~y & z;
assign d[6] = x & y & ~z;
assign d[7] = x & y & z;
endmodule

PROCEDURE

1) Open the project navigator.

2) Go to the file, open new project.

3) Type the program name and change the option to HDL

4) Click next to all other window that appear and finally finish

5) Go to the project and select new source

6) Type the file name and select HDL

7) Type the HDL coding in the window appears.

8) Go to the synthesis-XST and run the implementation design in the process window.

9) Click view RTL synthesis and verify the circuit diagram generated

RESULT:
Thus simulation of Multiplexer and Decoder using HDL has been completed.

49
 BEYOND THE SYLLABUS

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

Ex.No:

DATE:

AIM:
To design and implement encoder and decoder using logic gates and study of IC 7445
and IC 74147.

APPARATUS REQUIRED:

S.No COMPONENT SPECIFICATION QTY

1 3 I/P NAND GATE IC7410 2
2 OR GATE IC7432 3
3 NOT GATE IC7404 1
4 IC TRAINER KIT - 1
5 PATH CORDS - 27

THEORY:

ENCODER:

An encoder is a digital circuit that performs inverse operation of a decoder.

An encoder has 2n input lines and n output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight inputs, one
for each octal digit and three output that generate the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero
outputs can also be generated when D0 = 1.

DECODER:

A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code word i.e
there is one to one mapping can be expressed in truth table. In the block diagram of decoder
circuit the encoded information is present as n input producing 2n possible outputs. 2n output
values are from 0 through out 2n – 1.
BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 7445:

50
PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:

2
LOGIC DIAGRAM FOR DECODER:

2
TRUTH TABLE:

INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

3
RESULT:

Thus the design and implementation of encoder and decoder using logic gates and study
of IC 7445 and IC 74147 were done.

4
 DESIGN AND IMPLEMENTATION OF SEVEN SEGMENT DISPLAY

AIM:
To design and implement seven segment display using logic gates.

APPARATUS REQUIRED

S.NO COMPONENT SPECIFICATION QUANTITY

1. AND Gate IC 7408 2
2. OR Gate IC 7432 3
3. NOT Gate IC 7404 1
4. IC Trainer kit - 1
5. Patch cords - As per required level

THEORY:
A seven segment display (SSD) seven segment indicator is a form of electronic display
device for displaying decimal numerals that is an alternative to the more complex dot matrix
display.
Seven segment displays are widely used in digital clocks, electronic meters, basic
calculators and other electronic devices that display numerical information.
The seven segment of the display can be used in differential combination to represent the
Arabic numerals. Often the seven segment are arranged in an oblique arrangement, which aids
readability.
The seven segment are arranged as a rectangle of two vertical segments on each side with
one horizontal segment on the top,middle and bottom. Additionally the seven segement bisect
the rectangle horizontally. There are also 14 segments display and 16 segement display.
However these have mostly been replaced by dot matrix display.The segment of a seven
segment display is referred to by the letter ‘a’ to ‘g’ where the optional decimal point is used for
the display of non-integer numbers.

Digit Display gfedcba abcdefg a b c d e f g

0 0x3F 0x7E on on on on on on off

1 0x06 0x30 off on on off off off off

5
2 0x5B 0x6D on on off on on off on

3 0x4F 0x79 on on on on off off on

4 0x66 0x33 off on on off off on on

5 0x6D 0x5B on off on on off on on

6 0x7D 0x5F on off on on on on on

7 0x07 0x70 on on on off off off off

8 0x7F 0x7F on on on on on on on

9 0x6F 0x7B on on on on off on on

A 0x77 0x77 on on on off on on on

b 0x7C 0x1F off off on on on on on

C 0x39 0x4E on off off on on on off

d 0x5E 0x3D off on on on on off on

E 0x79 0x4F on off off on on on on

F 0x71 0x47 on off off off on on on

6
7-segment Display Truth Table

Individual Segments Illuminated

Decimal
Digit

a b c d e f g

0 × × × × × ×

1 × ×

2 × × × × ×

3 × × × × ×

4 × × × ×

7
 5 × × × × ×

6 × × × × × ×

7 × × ×

8 × × × × × × ×

9 × × × × ×

Driving a 7-segment Display using a 4511

8
Truth Table for a 7-segment display

Individual Segments Individual Segments

Display Display

a B c d e f g a b c d e f g

× × × × × × 0 × × × × × × × 8

× × 1 × × × × × × 9

× × × × × 2 × × × × × × A

× × × × × 3 × × × × × B

× × × × 4 × × × × C

× × × × × 5 × × × × × D

× × × × × × 6 × × × × × E

× × × 7 × × × × F

9
10
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the design and implementation of seven segment display using logic gates is
verified.

11
EX.NO: CODING SEQUENTIAL CIRCUITS USING HARDWARE DESCRIPTION
LANGUAGE
DATE:

AIM
To design sequential circuits using HDL coding and verify their truth tables.

SOFTWARE USED

• PC with Windows XP
• XILINX 8.2 i SOFTWARE

THEORY

A register is capable of shifting its binary information in one or both directions is known
as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop. The simplest possible shift register is
one that uses only flip flop. The output of a given flip flop is connected to the input of next flip
flop of the register. Each clock pulse shifts the content of register one bit position to right.

PROGRAM

REGISTERS

SISO

module siso(d,clk,rst,q);

input d,clk,rst;

output[3:0]q;

wire[3:0]q;

dff a1(d,clk,rst,q[0]);

dff a2(q[0],clk,rst,q[1]);

dff a3(q[1],clk,rst,q[2]);
12
 dff a4(q[2],clk,rst,q[3]);

endmodule

SISO WAVEFORM

PIPO

module pipo(q,d,clk,rst);

output[0:3]q;

input[0:3]d;

input clk,rst;

dff a1(d[0],clk,rst,q[0]);

dff a2(d[1],clk,rst,q[1]);

dff a3(d[2],clk,rst,q[2]);

dff a4(d[3],clk,rst,q[3]);

endmodule

PIPO WAVEFORM

13
D FLIP FLOP

module dff a1(d,clk,rst,q);

input d,clk,rst;

output q;

wire q;

always @ (posedge (clk))

begin

if(~rst)

q=1’b0;

else

q=d;

endmodule

PROGRAM

COUNTER

module Count2Bit(Clock, Clear, out);

input Clock;
14
input Clear;

output [1:0] out;

reg [1:0]out;

always@(posedge Clock, negedge Clear)

if((~Clear) || (out>=4))out=2'b00;

else out=out+1;

endmodule

WAVEFORM

OUTPUT

15
UP COUNTER

Module upcount (clk.N,a);

input clk;
input [3:0] N;
output reg [3:0] a;
initial a=4’b0000;
always @ (negedge clk)
a= (a==N)? 4’b0000: a+1’b1;
16
endmodule

WAVEFORM

PROCEDURE

1) Open the project navigator.

2) Go to the file, open new project.

3) Type the program name and change the option to HDL

4) Click next to all other window that appear and finally finish

5) Go to the project and select new source

6) Type the file name and select HDL

7) Type the HDL coding in the window appears.

8) Go to the synthesis-XST and run the implementation design in the process window.

9) Click view RTL synthesis and verify the circuit diagram generated.

RESULT
Thus simulation of sequentional circuits using HDL has been completed.
17
VIVA QUESTIONS AND ANSWERS:

1) What do you mean by literal?

In a Boolean Function the total number of variables in complemented or
uncomplemented form is called literals.
Ex: F (A,B,C,D)= A+ĀC+BCD contains four Literals.
2) What are the basic properties of Boolean algebra?
The basic properties of Boolean algebra are Commutative property, Associative property
and Distributive property.
3) State the two absorption properties of Boolean algebra.
1. A+ AB= A
2. A(A+B)= A
4) Name the two basic types of Boolean Expressions.
The two basic types of Boolean Expressions are:
1. Sum of Product form(SOP) and
2. Product of Sum form(POS)
5) Define Minterm and Maxterm.
Each individual term in standard SOP form is called Minterm and each individual term
in standard POS form is called Maxterm. The concept of minterms and maxterms
allows us to introduce a very convenient shorthand notation to express logical functions.
6) What are the methods adopted to reduce Boolean Function?
1. Boolean function simplification using Boolean laws and theorems.
2. Karnaugh map
3. Tabular method or Quine Mc-Cluskey method
4. Variable entered map technique.
7) What is Karnaugh map?
A Karnaugh map or K-map is a pictorial form of truth table, in which the map diagram
is made up of squares, with each squares representing one minterm of the function.
8) What are don’t care conditions and incompletely specified functions?
Sometimes, while designing a Digital circuit, certain conditions of input are of no use.
Ex: Consider an example of BCD input for a seven segment display. In this case, inputs
from 0 to 9 are valid inputs. Thus, rest of the inputs from 10 to 15 does not signify
anything at the output side. The outputs for which inputs are not specified are called
don’t care outputs. The Boolean function in which don’t care outputs exists is called
incomplete Boolean function or incompletely specified functions.
9) State the limitations of Karnaugh map.
1. As the number of variables increases it is difficult to make judgments about which
combinations form the minimum expression.
2. K-map simplification is manual technique and simplifying process depends on
human abilities.
10) Advantages of Karnaugh map method.
1. It is a fast method for simplifying expression up to four variables.

18
 2. It gives a visual method of logic simplification.
3. Prime implicants and essential prime implicants are identified fast.
4. Suitable for both SOP and POS forms of reduction.
11) Define Binary Logic.
Binary Logic consists of Binary variables and Logical operations. The variables are
designated by the alphabets such as A, B, C, x, y, z etc., with each variable having only two
distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT.
12) What is a Logic gate?
The Logic gate is an electronic circuit that has one or more input binary variables but only
one output. It is called logic gate because of its ability to operate on a number of binary
inputs to perform a logical function, i.e., its output is a logical function of inputs.
13) What are the basic digital logic gates?
The three basic logic gates are
1. AND gate
2. OR gate
3. NOT gate
14) What are the equivalent gates?
1. AND-Inverter gate equals to NAND gate.
2. OR-Inverter gate equals to NOR gate.
3. Bubbled OR gate equals to NAND gate
4. Bubbled AND gate equals to NOR gate

15) Application of XOR gate.

XOR function can be used as:
1. An inverter by connecting one input to logic 0.
2. It can also be used as a modulo-2- adder.
16) Write the names of Universal gates.
Universal gates are:
1. NAND gate
2. NOR gate
17) Why NAND and NOR gates are known as Universal Gates?
NAND and NOR are the gates that can be used alone to generate remaining gate such as
NOT, AND and OR. Thus, with only any of the two gates, we can implement the logic
circuit. Hence, they are called Universal gates.
18) Why digital circuits are more frequently constructed with NAND or NOR gates than
with AND and OR gates?
1. If any simple combinational circuit we build and we are not using universal gates then
we require several AND, OR and NOT gates. This demands a number of IC’s and
hence there is a possibility that all gates in each IC are not used and IC utility factor will
be poor.
2. Using universal gates it is possible reduce number of IC’s required to implement
combinational circuit.
19) What are the advantages of digital Integrated circuits?

19
 1. Highly reliable for designing complex circuits.
2. Digital IC’s reduce system cost.
3. Smaller in size.
4. Less power required for the system.
20) Define noise margin.
1. The voltage difference between the lowest possible HIGH output, 𝑉𝑂𝐻(𝑚𝑖𝑛) and the
minimum input voltage, 𝑉𝐼𝐻(𝑚𝑖𝑛) required for a HIGH input is called high-state noise
margin.
2. The voltage difference between the largest possible low output, 𝑉𝑂𝑙(𝑚𝑎𝑥) and the
maximum input voltage, 𝑉𝐼𝐿(𝑚𝑎𝑥) required for a LOW input is called low-state noise
margin.
3. The noise margin allows the digital circuit to function properly if noise voltages are
within the noise margin.
21) What is fan-out of a gate?
It is the maximum number of inputs of the same family that the gate can drive maintaining
its output levels within the specified limits.
Ex: If an inverter’s output can drive maximum 10 inputs of any logic gates from the same
family, the fan-out of inverter is 10.
22) What is fan-in of a gate?
Fan-in of a gate is said to be the number of inputs in a digital logic gate.
Ex: 2 input NOR has fan-in of 2.
23) What is logic level?
The two voltage levels used to represent two logic states in a digital logic system are called
logic levels.
24) Explain positive logic systems.
The system in which the higher of the two voltage levels represent a 1 and the lower
voltage represents a 0 is called a positive logic system.
Positive Logic HIGH = 1 (i.e. + 5 v)
LOW = 0 (i.e. 0v)
25) Explain negative logic systems.
The system in which the lower of the two voltage levels represent a 1 and the higher
voltage represents a 0 is called a negative logic system.
Negative Logic HIGH = 0 (i.e. + 5 v)
LOW = 1 (i.e. 0v)
26) Mention the important characteristics of digital IC’s.
1. Fan-out
2. Power dissipation
3. Propagation delay
4. Noise margin
5. Fan-in
6. Operating temperature
7. Power supply requirements
27) What is Operating temperature?
20
 All the gates or semiconductor devices are temperature sensitive in nature. The temperature
in which the performance of the IC is effective is called operating temperature. Operating
temperature of the IC vary from 00c to 700c.
28) Define combinational circuit.
When logic gates are connected together to produce a specified output for certain specified
combinations of input variables, with no storage involved, the resulting circuit is called
combinational logic circuit. A combinational circuit consists of input variables, logic gates
and output variables.
29) Enumerate some of the combinational circuits.
Combinational circuits are:
1. Adders
2. Subtractors
3. Multiplexers
4. Demultiplexers
5. Encoders
6. Decoders
30) Define Half adder
Half adder: The logic circuit which performs the arithmetic sum of two bits is called a half
adder.
31) Define Full adder
Full adder: The logic circuit which performs the arithmetic sum of 3 bits (bit 1: input 1, bit
2: input 2, bit 3: carry from the previous addition) is a called a full adder.
32) Define half subtractor
Half subtractor: It is a combinational circuit that subtracts two bits and produces their
difference and borrow.
33) Define Full subtractor
Full subtractor: It is a combinational circuit that performs a subtraction between 2 bits. It
also takes into account borrow of the lower significant stage.
34) Suggest a solution to overcome the limitation on the speed of an adder.
It is possible to increase speed of an adder by eliminating inter-stage carry delay. This
method utilizes logic gates to look at the lower-order bits of augend and addend to see if a
higher order carry to be generated.
35) What is a multiplexer?
Multiplexer is a digital switch. Particularly, it has 2n input lines and n selection lines whose
bit combinations determine which input line is selected and routed onto available only
single output line. Also called as ‘many into one’ and ‘data selector’
36) What is the function of the enable input in a multiplexer?
The function of the enable input in a MUX is to control the operation of the unit.
37) List out the applications of the multiplexer.
1. Used as a data selector to select one out of many data inputs.
2. Used to implement combinational logic circuit
3. In time and frequency multiplexing systems.
4. Used in A/D and D/A converters.
38) Mention differences between MUX and DEMUX.

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 Parameter Multiplexer Demultiplexer
Definition Is a digital switch which Is a circuit that receives
allows digital information information on a single line
from several sources to be and transmits this
routed onto a single output information on one of the 2n
line possible output lines
Number of data inputs 2n 1
Number of data outputs 1 2n
Relationship of input and Many to one One to many
output
Applications Data selector Data distributor

39) Application of demultiplexer

1. Used as a decoder
2. As a data distributor
3. It is used in time division multiplexing at the receiving end as a data separator.
40) What is demultiplexer?
A demultiplexer is a circuit that receives information on a single line and transmits this
information on one of 2n possible output lines. The selection of specific output line is
controlled by the values of n selection lines.
41) Why parity generator/ checker are needed?
A parity bit is used for detecting errors during transmission of binary information. A parity
bit is an extra bit included with a binary message to make the number is either even or odd.
The message including the parity bit is transmitted and then checked at the receiver ends
for errors. An error is detected if the checked parity bit doesn’t correspond to the one
transmitted. The circuit that generates the parity bit in the transmitter is called a ‘parity
generator’ and the circuit that checks the parity in the receiver is called a ‘parity checker’.
42) What is code conversion?
If two systems working with different binary codes are to be synchronized in operation,
then we need digital circuit which converts one system of codes to the other. The process of
conversion is referred to as code conversion.
43) What is code converter?
It is circuit that makes the two systems compatible even though each uses a different binary
code. It is a combinational circuit that converts vinary signals from source code to its output
code.
Ex: BCD to Excess-3 converter.
44) What is Magnitude comparator?
A comparator is a special combinational circuit designed primarily to compare the relative
magnitude of two binary numbers. It receives two n-bit numbers A and B as inputs and the
outputs are A>B, A=B and A<B.
45) List out applications of comparators.
1. Comparators are used as a part of the address decoding circuitry in computers to select
a specific input/ output device for storage of data.
2. Used in control applications
3. In digital locking systems.

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46) What is a sequential circuit?
Sequential circuit is a broad category of digital circuit whose logic gates depend on a
specified time sequence. A sequential circuit consists of combinational circuit to which
memory are connected to form a feedback path.
47) What are the classifications of sequential circuits?
1. Synchronous sequential circuit.
2. Asynchronous sequential circuit.
48) What is Synchronous sequential circuit?
A synchronous sequential circuit is a system whose behavior can be defined from the
knowledge of its signal at discrete instants of time.

49) Comparison between combinational and sequential circuit.

Combinational circuit Sequential circuit
The output variables are at all times The output variables depend not only on the
dependent on the combination of input present input variables but they also depend
variables upon the past history of these input variables
Memory unit is not required Memory unit is required to store the past
history of input variables
Easy to design Are comparatively harder to design

50) Define flip-flop.

The basic unit for storage is flip-flop. A flip-flop maintains its output state either at 1 or 0
until directed by an input signal to change its state.
51) What is counter?
A counter is capable of counting the number of clock pulses arriving at its clock input.
Counter represents the number of clock pulses arrived. On arrival of each clock pulse, the
counter is incremented by one. In case of down counter, it is decremented by one.
52) What is synchronous / ripple counter?
When counter is clocked such that each flip-flop in the counter is triggered at the same
time, the counter is called synchronous counter.
53) What is asynchronous counter?
A binary asynchronous/ripple counter consists of a series connection of complementing
flip-flops, with the output of each flip-flop connected to the input of the next higher-order
flip-flop.
54) Name the different types of counter.
1. Synchronous counter
2. Asynchronous counter
a) Up counter
b) Down counter
c) Modulo- N counter
d) Up/down counter
55) What is up counter?
A counter that increments the output by one binary number each time a clock pulse is
applied.
56) What is down counter?
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 A counter that decrements the output by one binary number each time a clock pulse is
applied.
57) What is up/down counter?
A counter, which capable of operating as an up counter or down counter, depending on a
control input applied.
58) What are the applications of counter?
Applications of counter:
1. Frequency division
2. Digital clock
3. Stop watch
4. Programmable logic controllers
59) Define registers
A registers is a group of flip-flops. So an n-bit register has a group of n- flip flops and is
capable of storing any binary information/ number containing n-bits.
60) Define shift registers.
The binary information in a register can be moved from stage to stage within the register or
into or out of the register upon application of clock pulses, this type of bit movement or
shifting is essential for certain arithmetic and logic operations used in microprocessors.
This gives rise to group of registers called shift registers.
61) What are the different types of shift registers?
1. Serial in serial out shift register
2. Serial in parallel out shift register
3. Parallel in serial out shift register
4. Parallel in parallel out shift register
5. Bidirectional shift register
62) What is the difference between serial and parallel transfer?
When data is transferred one bit at a time, the process of transfer is known as serial transfer.
When multiple bits of data are transferred at a time, the process is known as parallel
transfer. For a parallel transfer, we can use parallel in and parallel out register. For serial
transfer we can use left shift or right shift register.
63) What is parallel shifting?
In a shift register all the data are moved simultaneously and then the technique is called
parallel shifting.
64) Define universal shift register.
The register which has both shifts (left-shift and right-shift) and parallel load capabilities is
referred to as universal shift register.
65) What are the applications of a shift register?
1. Delay line
2. Serial to parallel converter
3. Parallel to serial converter
4. Sequence detector
66) Define HDL
The basic steps involved in this process are;
a. Specify the desired behavior of the circuit
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 b. Synthesize the circuit
c. Implement the circuit
d. Test the circuit to check whether the desired specifications meet.
As the size and complexity increases, the system becomes highly complex, so
Computer Aided Design (CAD) tools are used.
One such tool is a Hardware Description Language (HDL).
67) Prominent modern HDL’s.
1. Verilog
2. VHDL
Verilog is one of the two major Hardware Description Languages (HDLs)
used by hardware designers in industry and academia.

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