First name, last name, id ..........................................................................................................................................................

Testing and fault tolerance

Exam of January 31, 2024
Time: 90 minutes
Students are NOT allowed to use any material during the exam,
nor to communicate in any manner among them or with the outside, nor to use any electronic device.
Please write on these sheets of papers, only.

Question 1 – 5 points
Let us consider the combinational circuit shown below.
You are requested to
1. Compute the number of faults in the full stuck-at fault list for the circuit (we suggest reporting in the answer the list of
fault locations) and the number of faults in the collapsed stuck-at fault list, using local fault equivalences.
2. Identify a test vector (if any) for the fault p/1
3. Identify a test vector (if any) for the fault l/0
4. Identify a test vector pair (if any) for the fault C STR
5. Compute the number of Path Delay Faults (we suggest reporting in the answer the list of paths).
Question 2 – 5 points

A sequential circuit has the following characteristics:

 Number of primary inputs: 56
 Number of primary outputs: 180
 Number of flip flops: 60.
The circuit is tested adopting the scan technique; flip flops are included in 2 balanced chains. The ATPG generated 100 vectors
for the test of the stuck-at faults in the combinational part.
You are requested to
1. describe the changes to be performed to the circuit netlist and circuit pinout (i.e., the input/output signals) in order to
support the test
2. describe in details the sequence of steps to be performed during the test
3. compute the duration (in clock cycles) of the test addressing all possible stuck-at faults in it.
Question 3 – 5 points

Let us consider a sequential circuit having 250 Primary Inputs, 50 Primary Outputs, and 2,000 flip flops. We want to test it
using the STUMPS technique. You are requested to
1. List the changes to the circuit structure required by STUMPS, detailing the type and size (in bits) of any added module and
its connections. Flip flops must be organized in 4 chains of the same length.
2. Describe the steps required to test the circuit
3. Estimate the aliasing probability
4. Compute the duration of the test (in clock cycles), assuming that 2,000 random vectors are required to achieve a sufficient
stuck-at Fault Coverage.
Question 4 – 5 points

Let us consider the typical inductive flow for evaluating the risk in an electronic system.
In particular, you are requested to
1. Define what we mean by “Risk”
2. Describe the main steps for assessing the risk in an electronic system
3. For each step, list the source of information and the tools which are most commonly used.
Question 5 – 5 points

A board includes 5 digital devices (D0 to D4) supporting the IEEE 1149.1 standard; their TAP ports are connected to a 5 pin
Boundary Scan connector as shown in the figure below. You want to test the interconnections between devices D2 and D3,
resorting to 50 vectors. The key parameters for the 5 devices are reported in the following table.
D0 D1 D2 D3 D4
IR length 6 8 10 5 6
BS register 120 250 315 65 210
You are requested to describe in detail the steps to be performed, specifying their duration.

1 Test-Logic-Reset
0
1 1 1
0 Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0
1 1 Capture-IR
Capture-DR
0 0
Shift-DR 0 Shift-IR 0
1 1
Exit1-DR 1 Exit1-IR 1
0 0 0 0
Pause-DR Pause-IR
1 1
0 0 Exit2-IR
Exit2-DR
1 1
1
Update-DR Update-IR
0 1 0