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UNIT IV
INPUT-OUTPUT ORGANIZATION:
Input-Output Interface, Asynchronous data transfer, Modes of Transfer, Priority Interrupt,
Direct memory Access

PERIPHERAL DEVICES:

Input and output devices attached to the computer are also called peripherals.

Ex: keyboards, display units, and printers.

Peripherals that provide auxiliary storage for the system are magnetic disks and tapes. Peripherals are
electromechanical and electromagnetic devices of some complexity.

Monitor and keyboard: There are different types of video monitors, but the most popular use a cathode
ray tube (CRT). The CRT contains an electronic gun that sends an electronic beam to a phosphorescent
screen in front of the tube. The beam can be deflected horizontally and vertically.

A characteristic feature of display devices is a cursor that marks the position in the screen where the next
character will be inserted. The cursor can be moved to any position in the screen, to a single character,
the beginning of a word, or to any line. Edit keys add or delete information based on the cursor position.
The display terminal can operate in a single-character mode where the computer simultaneously.

Printer: Printer provides permanent record on paper of computer output data or text.

There are three basic types of character printers:

1. Daisy wheel

2. dot matrix, and

3. laser printers.

Daisy wheel: The daisywheel printer contains a wheel with the characters placed along the
circumference. To print a character, the wheel rotates to the proper position and an energized magnet
then presses the letter against the ribbon.

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dot matrix: The dot matrix printer contains a set of dots along the printing mechanism.

Example: A 5*7 dot matrix printer that prints 80 character per line has seven horizontal lines, each
consisting of 5*80=400 dots.

laser printers: The laser printer uses a rotating photographic drum that is used to imprint the character
images.

Magnetic tape: Magnetic tapes are used mostly for storing files of data. It is one of the cheapest and
slowest methods for storage and has the advantage that tapes can be removed when not in use.

Magnetic disks: Magnetic disks have achieved by moving a read-write mechanism to attract in the
magnetized surface. Disks are used mostly for bulk storage of programs and data.

INPUT – OUTPUT INTERFACE:

Input-output interface provides a method for transferring information between internal storage and
external I/O devices. Peripherals connected to a computer need special communication links for
interfacing them with the central processing unit. The purpose of the communication link is to resolve
the differences that exist between the central computer and each peripheral.

The major differences are:

1. Peripherals are electromechanical and electromagnetic devices and their manner of operation is
different from the operation of the CPU and memory, which are electronic devices. Therefore, a
conversion of a signal values may be required.
2. The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, and
consequently, a synchronization mechanism may be needed.
3. Data codes and formats in peripherals differ from the word format in the CPU and memory.
4. The operating modes of peripherals are different from each other and each must be controlled so as
not to disturb the operation of other peripherals connected to the CPU.

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To resolve these differences, computer systems include special hardware components between
the CPU and peripherals to supervise and synchronize all input and output transfers. These
components are called interface units.

I/0 Bus and Interface Modules:

 The I/O bus consists of data lines, address lines, and control lines.

 The magnetic disk, printer, and terminal are employed in practically any general-purpose computer.
The magnetic tape is used in some computers for backup storage.

 Each peripheral device has associated with it an interface unit.

 Each interface decodes the address and control received from the I/O bus, interprets them for the
peripheral and processor.

 Each peripheral has its own controller that operates the particular electromechanical device.

 The I/O bus from the processor is attached to all peripheral interfaces. To communicate with a
particular device, the processor places a device address on bus, an address decoder that monitors the
address lines.

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 When the interface detects its own address, it activates the path between the bus lines and the device
that it controls. All peripherals whose address does not correspond to the address in the bus are
disabled by their interface.

I/O Commands: There are four types of commands that an interface may receive. They are classified
as control, status, data output, and data input.

1. Control command: A control command is issued to activate the peripheral and to inform it what
to do.

Example: A magnetic tape unit may be instructed to backspace the tape by one record, to rewind
the tape, or to start the tape moving in the forward direction.

2. Status: A status command is used to test various status conditions in the interface and the
peripheral.

Example: The computer may wish to check the status of the peripheral before a transfer is initiated.

3. Output data: A data output command causes the interface to respond by transferring data from the
bus into one of its registers.

4. Input data: The data input command is the opposite of the data output. In this case the interface
receives an item of data from the peripheral and places it in its buffer register.

I/O versus Memory Bus: There are three ways that computer buses can be used to communicate with
memory and I/O:

1. Use two separate buses, one for memory and the other for I/O.
2. Use one common bus for both memory and I/O but have separate control lines for each.
3. Use one common bus for memory and I/O with common control line.

Example of I/O Interface:

 It consists of two data registers called ports, a control register, a status register, bus buffers, and
timing and control circuits.

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 The interface communicates with the CPU through the data bus. The chip select and register select
inputs determine the address assigned to the interface.
 I/0 read and write are two control lines that specify an input or output, respectively.
 The four registers communicate directly with the I/O device attached to the interface.
 The I/O data to and from the device can be transferred into either port A or port B.
 The interface may operate with an output device or with an input device, or with a device that
requires both input and output.
 A magnetic disk unit transfers data in both directions but not at the same time, so the interface can
use bidirectional lines.
 Control is send to the control register, status information is received from the status register, and
data are transferred to and from ports is always via the common data bus.
 The control register receives control information from the CPU. By loading appropriate bits into
the control register, the interface and the I/O device attached to it can be placed in a variety of
operating modes.
 Port A may be defined as an input port and port B as an output port.

 The bits in the status register are used for status conditions and for recording errors that may occur
during the data transfer.
Example:
 A status bit may indicate that port A has received a new data item from the I/O device.
 Another bit in the status register may indicate that a parity error has occurred during the transfer.

 The circuit enables the chip select (CS) input when the interface is selected by the address bus.
The two register select inputs RS1 and RS0 are usually connected to the two least significant lines
of the address bus.

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 These two inputs select one of the four registers in the interface.
 The content of the selected register is transfer into the CPU via the data bus when the I/O read
signal is enabled.
 The CPU transfers binary information into the selected register via the data bus when the I/0 write
input is enabled.

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I/O mapping: there are two types

Memory-mapped I/O:
 Single address space for both memory and I/O devices
disadvantage – uses up valuable memory address space
 I/O module registers treated as memory addresses
 Same machine instructions used to access both memory and I/O devices
advantage – allows for more efficient programming
 Single read line and single write lines needed
 Commonly used
Isolated I/O:
 Separate address space for both memory and I/O devices
 Separate memory and I/O select lines needed
 Small number of I/O instructions
 Commonly used

ASYNCHRONOUS DATA TRANSFER:

 If the registers in the interface share a common clock with the CPU registers, the transfer between
the two units is said to be synchronous.
 In most cases, the internal timing in each unit is independent from the other in that each uses its own
private clock for internal registers. It is called asynchronous.
 Asynchronous data transfer between two independent units requires that control signals be
transmitted between the communicating units.
There are two methods are used to supply control signals.
1. Strobe control
2. Handshaking

Strobe Control: A strobe pulse supplied by one of the units to indicate to the other unit when the
transfer has to occur. The strobe may be activated by either the source or the destination unit. Figure (a)
shows a source-initiated transfer. The data bus carries the binary information from source unit to the
destination unit. The strobe is single line that informs the destination unit when a valid data word is
available in the bus.

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The following figure shows a data transfer initiated by the destination unit. In this case the
destination unit activates the strobe pulse, informing the source to provide the data. The source unit
responds by placing the requested binary information on the data bus. The data must be valid and remain
in the bus long enough for the destination unit to accept it.

Disadvantage: The source unit that initiates the transfer has no way of knowing whether the destination
unit has actually received the data item that was placed in the bus.

Handshaking: The handshake method solves this problem (disadvantage of strobe control) by
introducing a second control signal that provides a reply to the unit that initiates the transfer.
The following figure shows the data transfer procedure when initiated by the source.

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The two handshaking lines are data valid, which is generated by the source unit, and data
accepted, generated by the destination unit. The source unit initiates the transfer by placing the data on
the bus and enabling its data valid signal. The data accepted signal is activated by the destination unit
after it accepts the data from the bus. The source unit then disables its data valid signal, which
invalidates the data on the bus. The destination unit then disables its data accepted signal and the system
goes into its initial state. The source does not send the next data item until after the destination unit
shows its readiness to accept new data by disabling its data accepted signal.
The source unit in this case does not place data on the bus until after it receives the ready for data
signal from the destination unit. From there on, the handshaking procedure follows the same pattern as
in the source-initiated case. (see the below figure)

Timeout: if one unit is faulty, the data transfer will not be completed. Such an error can be detected by
means of a timeout mechanism, which produces an alarm if the data transfer is not completed within a
predetermined time. The timeout is implemented by means of an internal clock that starts counting time
when the unit enables one of its handshaking control signals.
ASYNCHRONOUS SERIAL TRANSFER:

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The transfer of data between two units may be done in parallel or serial.

Parallel data transmission: In parallel data transmission, each bit of the message has its own path and
the total message is transmitted at the same time. This means that an n-bit message must be transmitted
through n separate conductor paths.

Advantage: it is faster and it is used for short distances and where speed is important.

Disadvantage: it requires many wires.

Serial data transmission: In serial data transmission, each bit in the message is sent in sequence one at
a time. This method requires the use of one pair of conductors or one conductor and a common ground.

Advantage: it is less expensive since it requires only one pair of conductors. It is used for long
distances.

Disadvantage: Serial transmission is slower.

Serial transmission can be synchronous or asynchronous.

Synchronous: In synchronous transmission, the two units share a common clock frequency and bits are
transmitted continuously at the rate dictated by the clock pulses.

Asynchronous: In asynchronous transmission, binary information is sent only when it is available and
the line remains idle when there is no information to be transmitted.

A serial asynchronous data transmission technique used in many interactive terminals employs special
bits that are inserted at both ends of the character code. With this technique, each character consists of
three parts: a start bit, the character bits and stop bits.

Start bit: start bit is always a 0 and is used to indicate the beginning of a character.

Stop bit: The stop bit is always a 1 and is used to indicate the beginning of a character.

An example of this format is shown in fig.11-7.

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A transmitted character can be detected by the receiver from knowledge of the transmission rules:

1. When a character is not being sent, the line is kept in the 1-state.

2. The initiation of a character transmission is detected from the start bit, which is always 0.

3. The character bits always follow the start bit.

4. After the last bit of the character is transmitted, a stop bit is detected when the line returns to the 1-
state for at least one bit time.

Using these rules, the receiver can detect the start bit when the line goes from 1 to 0.

Asynchronous Communication Interface:

 The interface is initialized for a particular mode of transfer by means of a control byte that is loaded
into its control register.

 The transmitter register accepts a data byte from the CPU through data bus. This byte is transferred
to a shift register for serial transmission.

 The receiver portion receives serial information into another shift register and when a complete data
byte is accumulated, it is transferred to the receiver register.

 The CPU can select the receiver register to read the byte through the data bus.

 The CPU can read the status register to check the status of the flag bits and to determine if any
errors have occurred.

 The chip select and the read & write control lines communicate with the CPU.

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 The chip select (CS) input is used to select the interface through the address bus.

 The register select (RS) is associated with the read (RD) and write (WR) controls.

 Two registers are write-only and two are read-only. The register selected is a function of the RS
value and the RD and WR status, as listed in the table accompanying the diagram.

 Two bits in the status register are used as flags. One bit is used to indicate whether the transmitter
register is empty and another bit is used to indicate whether the receiver register is full.

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 The CPU reads the status register and checks the flag to see if the transmitter register is empty. If it
is empty, the CPU transfers a character to the transmitter register and the interface clears the flag to
mark the register full. The first bit in the transmitter shift register is set to 0 to generate a start bit.

 The flag in the status register is set to indicate that the receiver register is full. The CPU reads the
status register and checks the flag, and if set, reads the data from the receiver register.

 The CPU can read the status register at any time to check if any errors have occurred. There are
three possible errors.

1. Parity error

2. Framing error

3. Overrun error

1. Parity error: Parity error occurs if the number of 1’s in the received data is not correct parity.

2. Framing error: Framing error occurs if the right number of stop bits is not detected at end of the
received character.

3. Overrun error: An Overrun error occurs if the CPU does not read the character from the receiver
register before the next one becomes available in the shift register.

First-In, First-Out Buffer: (FIFO buffer)

Definition: A first-in, first-out (FIFO) buffer is a memory unit that stores information in such a manner
that the item first in is the item first out. A FIFO buffer comes with separate input and output terminals.

 The important feature of this buffer is that it can input data and output data at two different rates and
the output data are always in the same order in which the data entered the buffer.

 FIFO buffer can be useful in some or all the applications when data are transferred asynchronously.

 It consists of four 4-bit registers RI,I=1,2,3,4, and a control register with flip-flops Fi ,i=1,2,3,4, one
for each register.

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 The FIFO can store four words of four bits each. The number of bits per word can be increased by
increasing the number of bits in each register and the number of words can be increased by
increasing the number of registers.

 A flip-flop Fi in the control register that I set to 1 indicates that a 4-bit data word is stored in the
corresponding register RI. A 0 in Fi indicates that the corresponding register does not contain valid
data.

 Whenever the Fi bit of the control register is set (Fi=1) and the Fi+1 bit is reset (F1i+1 = 1), a clock is
generated causing register R (I+1) to accept the data from register RI.

 Data are inserted into the buffer provided that the input ready signal is enabled. This occurs when
the first control flip-flop F1 is reset, indicating that register R1 is empty.

 Data are loaded from the input lines by enabling the clock in R1 through the insert control line. The
same clock sets F1, which disables the input ready control, indicating that the FIFO is now busy and
unable to accept more data.

 The ripple-through process begins provided that R2 is empty. The data in R1 are transferred into R2
and F1 is cleared. This enables the input ready line, indicating that the inputs are now available for
another data word.

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 If the FIFO is full, F1 remains set and the input ready line stays in the 0 state. Note that the two
control lines input ready and insert constitute a destination-initiated pair of handshake lines.

 The output ready control line is enabled when the last control flip-flop F4 is set, indicating that there
are valid data in the output register R4.

 The output data from R4 are accepted by a destination unit, which then enables the delete control
signal. This resets F4, causing output ready to disable, indicating that the data on the out are no
longer valid. Only after the delete signal goes back to 0 can the data from R3 and F4 will remain in
the reset state.

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MODES OF TRANSFER:

Data transfer to and from peripherals may be handled in one of three possible modes:

1. Programmed I/O

2. Interrupt-initiated I/O

3. Direct memory access (DMA)

Programmed I/O:

The programmed I/O method is particularly useful in small low-speed computers. An example of data
transfer from an I/O device through an interface into the CPU is shown in fig.

The device transfers bytes of data one at a time as they are available. When a byte of data is available,
the device places it in the I/O bus and enables its data valid line.

The interface accepts the byte into data register and enables the data accepted line. The interface sets a
bit (F or “flag” bit) in the status register.

The device can now disable the data valid line, but it will not transfer another byte until the data
accepted line is disabled by the interface.

A program is written for the computer to check the flag in the status register to determine if a byte has
been placed in the data register by the I/O device. This is done by reading the status register into a CPU
register and checking the value of the flag bit.

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If the flag is equal to 1, the CPU reads the data from the data register. The flag bit is then cleared to 0 by
either the CPU or the interface. Once the flag is cleared, the interface disables the data accepted line and
the device can then transfer the next data byte.

The transfer of each byte requires three instructions:

1. Read the status register.

2. Check the status of the flag bit and branch to step 1 if not set or to step 3 if set.

3. Read the data register.

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Interrupt initiated I/O:

Why: Programmed I/O is a time consuming
process, so in order to keep CPU on a busy state
introduce an interrupt and special commands to
inform the interface to issue an interrupt request
signal to CPU, when data are available from the
device. In the meantime, the CPU can proceed to
execute another program.

 When the device is ready for data transfer, it

generates an interrupt request to the computer.

 When there is an external interrupt signal is

generated, the CPU will stops the execution of
the original program and branches to service
program to process the I/O transfer and then
returns back to the original program.

 The CPU responds to the interrupt signal by

storing the return addresses from program
counter into a memory stack and then control
branches to a service routine that processes the required I/O transfer.

The way the processor chooses the branch address of the service routine varies from one unit to another.
There are two methods for using this:

1. Vectored interrupt
2. Non vectored interrupt

In a vectored interrupt, the source that interrupts supplies the branch information to the computer. This
information is called the interrupt vector.

In a Non vectored interrupt, the branch address is assigned to fixed location in memory.

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PRIORITY INTERRUPT:

 A priority interrupt is a system that establishes a priority over the various sources to determine
which condition is to be serviced first when two or more requests arrive simultaneously.

 Devices with high-speed transfers such as magnetic disks are given high priority, and slow devices
such as keyboards receive low priority.

 A polling procedure is used to identify the highest-priority source.

Daisy-Chaining Priority:

 The daisy-chaining method of establishing priority consists of a serial connection of all devices that
request an interrupt.

 The device with the highest priority is placed in the first position, followed by lower-priority
devices up to the device with the lowest priority, which is placed last in the chain.

 The interrupt request line is common to all devices and forms a wired logic connection.

 If any device has its interrupt signal in the low-level state, the interrupt line goes to the low-level
state and enables the interrupt input in the CPU.

 When no interrupts are pending, the interrupt line stays in the high-level state and no interrupts are
recognized by the CPU.

 The CPU responds to an interrupt request by enabling the interrupt acknowledge line. This signal is
received by device 1 at its PI (priority in) input.

 The acknowledge signal passes on to the next device through the PO ( priority output) output only if
device 1 is not requesting an interrupt.

 If device 1 has a pending interrupt, it blocks the acknowledge signal from the next device by placing
a 0 in the PO output. It then proceeds to insert its own interrupt vector address (VAD) into the data
bus for the CPU to use during the interrupt cycle.

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 A device with a 0 in its PI input generates a 0 in its PO output to inform the next-lower priority
device that the acknowledge signal has been blocked.

 A device that is requesting an interrupt and has a 1 in its PI input will interrupt the acknowledge
signal by placing a 0 in its PO output.

 If the device does not have pending interrupts, it transmits the acknowledge signal to the next
device by placing a 1 in its PO output. Thus the device with PI=1 and PO=0 is the one with the
highest priority that is requesting an interrupt, and this device places its VAD on the data bus.

 The daisy chain arrangement gives the highest priority to the device that receives the interrupt
acknowledge signal from the CPU.

 The device sets its RF flip-flop when it wants to interrupt the CPU.

 If PO=0, both PO and the enable line to VAD are equal to 0, irrespective of the value of RF.

 If PI=1 and RF=0, then PO=1 and vector address is disabled. This condition passes the acknowledge
signal to the next device through PO. The device is active when PI=1 and RF=1.

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Parallel Priority Interrupt:

 The parallel priority interrupt method uses a interrupt register whose bits are set separately by the
interrupt signal from each device. Priority is establishing according to the position of the bits in the
register.

 Mask register purpose is to control the status of each interrupt request. The mask register can be
programmed to disable lower-priority interrupts while a higher-priority device is being serviced. It
can also provide a facility that allows a high-priority device to interrupt the CPU while a lower-
priority device is being serviced.

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 Each interrupt bit and its corresponding mask bit are applied to an AND gate to produce the four
inputs to a priority encoder. In this way, an interrupt is recognized only if its corresponding mask bit
is set to 1 by the program.

 If IEN set to 1, indicates that the interrupt facility will be used while the current program is running.
If both IEN and IST are equal to 1, the CPU goes to an interrupt cycle.
 The priority encoder generates two bits of the vector address, which is transferred to the CPU.

Priority Encoder:

The x’s in the table designate don’t-care conditions.

 Input I0 has the highest priority; so regardless of the values of other inputs, when this input is 1, the
output generates an output xy=00.

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 I1 has next priority level. The output is 01 if I1=1 provided that I0=0, regardless of the values of the
other two lower-priority inputs.

 The output for I2 is generated only if higher-priority inputs are 0, and so on down the priority level.

 The interrupt status IST is set only when one or more inputs are equal to 1. If all inputs are 0, IST is
cleared to 0 and the other outputs of the encoder are not used, so they are marked with don’t-care
conditions. This is because the vector address is not transferred to the CPU when IST=0.

DIRECT MEMORY ACCESS (DMA):

Definition: Removing the CPU from the path and letting the peripheral device manage the memory
buses directly would improve the speed of transfer. This transfer technique is called “direct memory
access (DMA)”.

 During DMA transfer, the CPU is idle and has no control of the memory buses. A DMA controller
takes over the buses to manage the transfer directly between the I/O device and memory.

 The bus request (BR) input is used by the DMA controller to request the CPU to relinquish control
of the buses.

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 When this input is active, the CPU terminates the execution of the current instruction and places the
address bus, the data bus, and the read and write lines into a high-impedance state.

 The CPU activates the bus grant (BG) output to inform the external DMA that the buses are in the
high-impedance state.

 The DMA that originated the bus request can now take control of the buses to conduct memory
transfers without processor intervention.

 When the DMA terminates the transfers, it disables the bus request line. The CPU disables the bus
grant, takes control of the buses, and returns to its normal operation. The transfer can be made in
several ways.

DMA burst transfer: A block sequence consisting of a number of memory words is transferred in a
continuous burst while the DMA controller is master of the memory buses.

cycle stealing: It allows the DMA controller to transfer on data word at a time, after which it must
return control of the buses to the CPU.

DMA Controller:

 The unit communicates with the CPU via the data bus and control lines.

 The registers in the DMA are selected by the CPU through the address bus by enabling the DS
(DMA select) and RS (register select) inputs. The RD (read) and WR (write) inputs are
bidirectional.

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 The DMA controller has three registers: an address register, a word count register, and a control
register.

 The address register contains an address to specify the desired location in memory. The address
bits go through bus buffers into the address bus. The address register is incremented after each word
that is transferred to memory.

 The word count register holds the number of words to be transferred. This register is decremented
by one after each word transfer and internally tested for zero.

 The control register specifies the mode of transfer.

The CPU initializes the DMA by sending the following information through the data bus:

1. The starting address of the memory block, where data are available (for read) or where data are
to be stored (for write).
2. The word count, which is the number of words in the memory block.
3. Control to specify the mode of transfer such as read or write.
4. A control to start the DMA transfer.

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DMA
Transfer:

 When the peripheral device sends a DMA request, the DMA controller activates the BR line,
informing the CPU to relinquish the buses.

 The CPU responds with its BG line, informing the DMA that its buses are disabled.

 The DMA then puts the current value of its address register into the address bus, initiates the RD or
WR signal, and sends a DMA acknowledge to the peripheral device.

 When the peripheral device receives a DMA acknowledge, it puts a word in the data bus (for write)
or receives a word from the data bus (for read).

 For each word that is transferred, the DMA increments its addresses register and decrements its
word count register.

 If the word count register reaches zero, the DMA stops any further transfer and removes its bus
request.

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 It is used for fast transfer of information between magnetic disks and memory. It is also useful for
updating the display in an interactive terminal.

MEMORY ORGANIZATION:

Memory hierarchy, Main memory, Auxiliary memory, Associative memory, Cache memory

BASIC CONCEPTS: Memory Hierarchy

 The memory unit is needed for storing programs and data. The memory unit that communicates
directly with the CPU is called the main memory.
 Devices that provide backup storage are called “auxiliary memory”. The most common
auxiliary memory devices used in computer systems are magnetic disks and tapes. They are
used for storing system programs, large data files and other backup information.
 Only programs and data currently needed by the processor reside in main memory. Other
information is stored in auxiliary memory & transferred to main memory when needed.
 The main memory occupies a central position by being able to communicate directly with the
CPU and with auxiliary memory devices through an I/O processor.
 When programs are not residing in main memory which are needed by the CPU are brought from
auxiliary memory. Programs are not currently needed in main memory are transferred into
auxiliary memory to provide space for currently used programs and data.
 A special very high speed memory called a cache is sometimes used to increase the speed of
processing by making current programs and data available to the CPU at a rapid rate.

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 The cache memory is employed in computer systems to compensate for the speed differential
between main memory access time and processor logic.
 The cache is used for storing segments of programs currently being executed in the CPU and
temporary data frequently needed in the present calculations.
 The storage capacity of the memory increases, the cost per bit for storing binary information
decreases and the access time of the memory becomes longer.
 The auxiliary memory has a large storage capacity, is relatively inexpensive, but has low access
speed compared to main memory.
 The cache memory is very small, relatively expensive, and has very high access speed. Thus the
memory access speed increases, so does its relative cost.
 The overall goal of using a memory hierarchy is to obtain the highest possible average access
speed while minimizing the total cost of the entire memory system.
Multi-programming:

 Many operating systems are designed to enable the CPU to process a no of independent
programs concurrently. This is called “multiprogramming” refers to the existence of two or
more programs in different parts of the memory hierarchy at the same time.

 In multiprogramming system, when one program is waiting for input or output transfer, there is
another program ready to utilize the CPU.

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 Computer programs are sometimes too long to be accommodated in the total space available in
the main memory. A computer system uses many programs and all the programs cannot reside in
main memory at all times.

 A program with its data normally resides in auxiliary memory. When the program or a segment
of the program is to be executed, it is transferred to main memory to be executed by the CPU.

 The part of the computer system that supervises the flow of information between auxiliary
memory and main memory is called the memory management system.

MAIN MEMORY:

 The main memory is a relatively large and fast memory used to store programs and data during the
computer operation.

 Main memory is made up of RAM integrated circuit chips, but a portion of the memory may be
constructed with ROM chips.

SEMICONDUCTOR RAM MEMORIES:

 RAM is used to designate read/write to distinguish it from a ROM.

 RAM is used for storing the bulk amount of the programs and data that are subject to change.

 The RAM portion of main memory is needed for storing an initial program called a bootstrap
loader. The Bootstrap loader is a program whose function is to start the computer software
operating when power is turned on.

 RAM is volatile; its contents are destroyed when power is turned off.

 A RAM chips is better suited for communication with the CPU. The feature is a bidirectional data
that allows the transfer of data either from memory to CPU during a read operation or from CPU to
memory during a write operation.

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 When CS1=1, and =0, the memory can be placed in a write or read mode.

 The RD & WR signals control the memory operation as well as the bus buffers associated with the
bidirectional data bus.

 When the WR input is enabled, the memory stores a byte from the data bus into a location
specified by the address input lines.

 When the RD input is enabled, the content of the selected byte is placed into the data bus.

 The capacity of the memory is 128 words of 8 bits (one byte) per word. This requires a 7-bit address
and an 8-bit bidirectional data bus.

 The read and write inputs specify the memory operation and the two chip select (CS) control inputs
are for enabling the chip only when it is selected by the microprocessor.

 The read and write inputs are sometimes combined into one line labeled R/W. When the chip is
selected, the two binary states in this line specify the two operations of read or write.

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 Integrated RAM chips are available in two possible operating modes, static and dynamic.

Static RAM:

 The static RAM consists essentially of internal flip-flops that store the binary information.

 The static RAM is easier to use and has shorter read and write cycles.

Dynamic RAM:

 The dynamic RAM stores the binary information in the form of electric charges that are applied to
capacitors. The capacitors are provided inside the chip by MOS transistors. The stored charges on
the capacitors tend to discharge with time and the capacitors must be periodically recharged by
refreshing the dynamic memory.

 The dynamic RAM offers reduced power consumption and large storage capacity in a single
memory chip.

Static RAM Dynamic RAM

1. The static RAM consists essentially of The dynamic RAM stores the binary information
internal flip-flops that store the binary in the form of electric charges that are applied to
information. capacitors. The capacitors are provided inside
the chip by MOS transistors. The stored charges
on the capacitors tend to discharge with time and
the capacitors must be periodically recharged by
refreshing the dynamic memory.

2. The static RAM is easier to use The dynamic RAM offers reduced power
consumption

3. It has shorter read and write cycles. It has large storage capacity in a single memory
chip.

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READ-ONLY MEMORIES (ROM CHIPS):

 ROM is used for storing programs that are permanently resided in the computer and that don’t
change.

 The contents of ROM remain unchanged after power is turned off and on again. (non volatile).

 A ROM can only read, the data bus only in an output made.

 For the same size chip, It is possible to have more bits of ROM than of RAM, because the internal
binary cells in ROM occupy less space than in RAM. For this reason, the diagram specifies a 512
byte ROM, while the RAM has 512bytes.

 The 9-address lines specify any one of the 512bytes stored in it. The two chips select inputs must be
CS1=1 & =0 for the unit operate. Otherwise, the data bus is in a high-impedance state.

Differences between RAM and ROM

RAM ROM

1. RAM is used to designate read/write to ROM is used to designate read operation

distinguish it from a ROM. only.

2. RAM is used for storing the bulk of the ROM is used for storing programs that are
programs and data that are subject to change. permanently resided in the computer and that
don’t change.

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3. RAM is volatile; its contents are destroyed ROM is nonvolatile; its contents are not
when power is turned off. destroyed when power is turned off.

4. It has a bidirectional data bus. It has a unidirectional data bus

5. The RAM portion of main memory is

needed for storing an initial program called a
bootstrap loader.

MEMORY ADDRESS MAP:

 The addressing of memory can be establish by the means of table that specifies the memory address
assigned to each clip. This is called memory address map.

 A computer system needs 512 bytes of RAM and 512 bytes of ROM. There are 16 lines in the
address bus, the table shows only 10 lines because the other 6 or not used in this example, and are
assumed to be zero.

 The small x’s under the address bus lines designates those lines that must be connected to the
address inputs in the each chip.

 The RAM chips have 128 bytes and need 7 address lines. The ROM chip has 512 bytes and needs 9
address lines.

 The x’s are always assign to the low – order bus lines 1 through 7 for the RAM and lines 1 through
9 for the ROM. It is necessary to distinguish between 4 RAM chips by assigning to each a different
address.

 When line 10 is 0, the CPU selects a RAM, and

 when this line is equal to 1, it selects the ROM

 The table clearly shows that the 9 low-order bus lines constitute a memory space for RAM equal to
29=512 bytes.

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 The first hexadecimal digit represent lines 13 to 16 and is always 0.

The next hexadecimal represent lines 9 to 12, but lines 11 and 12 are always 0.

These x’s represent a binary number that can range from all-0’s to an all -1’s value.

Memory connection to cpu:

 RAM AND ROM chips are connected to CPU through the data and address buses. This
configuration gives a memory capacity of 512 bytes of RAM and 512 bytes of ROM.

 Each RAM receives the 7 low –order bytes of the address bus to select the one of 128 possible
bytes. The particular RAM chip select is determined from lines 8 and 9 in the address bus. This is
done through a 2x4 decoder whose output goes to the CS1 input in each RAM chip.

 Thus, when address lines 8 and 9 are equal to 00, the first RAM chip is selected and when 01, the
second RAM chip is selected and so on. The RD &WR output from the microprocessor are applied
to the inputs of each RAM chip.

 The selection between RAM & ROM is achieved through bus line 10. The RAM’s are selected
when the bit in this line is 0, and the ROM when the bit is 1.

 The other chip selected input in the ROM is connected to the RD control line for the ROM chip to
be enabled only during a read operation.

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 Address bus lines 1 to 9 are applied to the input address of ROM without going through the
decoder. This assigns address 0 to 511 to RAM and 512 to 1023 to ROM.

 The data bus of the ROM has the only an output capability, where as the data bus connected to
RAM’s can transfer information in the both directions.

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Types of ROM:

PROM: Programmable Read-Only Memory

 It is a memory chip on which data can be written only once. Once a program has been written onto a
PROM, it remains there forever.

 Unlike RAM, PROMs retain their contents when the computer is turned off.

 The difference between a PROM and a ROM (read-only memory) is that a PROM is manufactured
as blank memory, whereas a ROM is programmed during the manufacturing process.

 To write data onto a PROM chip, you need a special device called a PROM programmer or
PROM burner. The process of programming a PROM is sometimes called burning the PROM.

EPROM: Erasable Programmable Read-Only Memory

 EPROM is a special type of memory that retains its contents until it is exposed to ultraviolet light.

 The ultraviolet light clears its contents, making it possible to reprogram the memory.

 To write to and erase an EPROM, you need a special device called a PROM programmer or
PROM burner.

EEPROM: Electrically Erasable Programmable Read-Only Memory

 EEPROM is a special type of PROM that can be erased by exposing it to an electrical charge.

 Like other types of PROM, EEPROM retains its contents even when the power is turned off. Also
like other types of ROM, EEPROM is not as fast as RAM.

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AUXILIARY MEMORY: (SECONDARY STORAGE)

 The most common auxiliary memory devices used in the computer systems are magnetic discs and
tapes. The most important characteristics of any devices are its access mode, access time, transfer
data, capacity and cost.
 The average time required to reach a storage location in memory and obtain its contents is called the
access time.
 In disks and tapes, the access time consists of seek time required to position the read-write head to a
location and a transfer time required to transfer data to are from the device.
 Because the seek time is usually much longer than the transfer time, auxiliary storage is organized
in records or blocks.

 A record is specified number of characters or words. Reading or writing is always done on entire
records. The transfer rate is the number of characters or words that the devices can be transfer for
second, after it has been positioned at the beginning of the record.
 The recording surface rotates at uniform speed and is not started or stopped during access
operations. bits are recorded as magnetic spots on the surface as it possess a stationary mechanism
called a write head.
 Stored bits are detected by change in the magnetic field produced by the record spot on the surface
as it passes through the read head.

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 Bits are stored in the magnetized surface in spots along concentric circles called tracks. The tracks
are commonly divided into sections called sectors. In the most systems, the min quantity of
information which can be transferred is a sector.
 The track address bits are used to move the head into the specified track position before reading or
writing.
 After the read/write heads are positioned in the specified track, the system has to wait until the
rotating disk reaches the specified sector under the R/w head.
 Information transfer is very fast once the beginning of the sector has been reached. Disks may have
multiple heads and simultaneous transfer of bits from several tracks at the same time.
 If bits are recorded with equal density, some tracks will contain more recorded bits than others. To
make all the records in a sector of all lengths, some disks use as a variable recording density with
higher density on tracks nearer the center than on tracks near the circumference.
 Disks that are permanently attached to the unit assemble and cannot be removed by the occasional
user called hard disk. A disk drive with removable disk is called a floppy disk.
 The disks used with a floppy disk drive are small removable disks made of plastic coated with
magnetic recording material.
Magnetic tape:
 A magnetic Tape transport consists of the electrical, mechanical, & electronic components to
provide the parts & control mechanisms for a magnetic tape unit.
 The tape itself is a strip of plastic coated with a magnetic recording medium for 9 bits are recorded
simultaneously to form a character together with a parity bit.
 Read/Write heads are mounted one in each track so that data can be recorded and read as as a
sequence of characters.
 Magnetic tape units can be stopped, started to more forward or in reverse or can be rewound.
RAID: Redundancy Array of Independent Disks

 This is an additional disk which can improve system performance.

 In RAID, we use an array of disks, these disks can operate independently.
 Multiple i/o requests can be handled in parallel if the requested data is distributed across multiple.
Benefits:

 RAID technology prevents data loss due to disk failure.

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 RAID technology can be implemented in hardware or software.

Applications: Servers make use of raid technology.

RAID levels: RAID0, RAID1, RAID2, RAID3, RAID4, RAID5, RAID6.

Common characteristics:

 A set of physical disk drives

 The operating system views these separating disks as a single logical disk.

 Redundant disk capacity is used to store parity information which can help in recovering data in
case of disk failure.

RAID level 0:

 It divides data into block units & writes them across a no of disks. This is called data stripping.
 There is no parity checking of data so, if one drive gets corrupted
then all the data would be lost. Thus RAID 0 does not support data
recovery.
Advantages:
 It increases speed

 Implementation is easy

 No overhead of parity calculation

RAID LEVEL 1:

 Same data is placed on multiple disks, it is also called data

mirroring.

 A read request can be executed by either of the two disks.

 A write request means that both the disks must be updated. This
can be done in parallel.

 Recovery from failure is simple. If one drive fails we just have to

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access data from the second drive.

 RAID 1 is used to store systems software.

Disadvantage: since data is duplicated, storage costs increase.

RAID LEVEL2:

 In RAID2 mechanism, all disks participate in the execution of every i/o request.
 Data stripping is used.
 Error connecting code is also calculated & stored with data.
 not implemented in practice due to high costs & overheads.

RAID LEVEL 3:

 Data is divided into byte units &written across

multiple disk drives.
 Parity information is stored for each disk section&
written to a dedicated parity drive.
 Thus disks can be accessed in parallel.
 Data can be transmitted in bulk. Thus high speed data
transmission is possible.
 In case of drive failure, the parity drive is accessed & data is reconstructed from the remaining
devices.

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RAID LEVEL 4:

 Data stripping size is large and the parity bits are stored
in the corresponding strip on the parity disk.

 For each read/write operation parity bits are checked

for data reliability

RAID LEVEL 5:

The data bits are organized in a similar fashion to

RAID level4. The difference is that RAID5 distributes
the parity strips across all disks.

ASSOCIATE MEMORY:
 The time required to find an item stored in memory can be reduced considered if stored data can be
identified for access by content of the data itself rather than by an address. A memory unit accessed
by its content is called an associative memory or content addressable memory (CAM).
 An Associate memory is more expensive than a RAM, because each cell must have storage
capacity. Associate memories are used in application where the search time is very critical and must
be very short.
Hardware organization:
The block diagram of associate memory is shown in fig. It consists of a memory array and logic form
words and n bits per word.

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 The argument register A and Key register K each have n bits, one for each bit of a word. The
matches register M has m bits, one for each memory word.
 Each word in memory is compared in parallel with the content of the argument register.
 The words that match the bits of the argument register set a corresponding bit in the match register.
 After the matching process, those bits in the register that have been set indicate the fact that their
corresponding word has been matched.
 The key register provides a mask for choosing a particular field or key in the argument word. The
entire argument is compared with each memory word if the key register contains all 1’s otherwise,
only those bits in the argument that have 1’s in their corresponding position of the key register are
compared.
example:

 Only the three left most bits of A are compared with memory words because k has 1’s in three
positions.
 Word2 matches the unmasked argument field because the three left most bits of the argument and
word are equal.

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 The cells in the array are marked by the letter C with two subscripts. The first subscript gives the
word number and the second specifies the bit position in the word.
 Thus cell Cij is the cell for bit j in the word i. A bit Aj in the argument register is compared with all
the bits in column j of the array provided that kj =1. This is done for all columns j=1,2,……….n.
 If a match occurs between all the unmasked bits of the arguments and the bits in the word i, the
corresponding bit Mi in the match register is set to 1.
 If one or more unmasked bits of the argument and the word don’t match M i is cleared to 0.

 The diagram consists of a flip-flop storage

elements Fij and circuits for reading, writing, and
matching the cell. The input bit is transferred into
the storage cell during a write operation.
 The bit stored is read out during read operation.
The match logic compares the content of the
storage cell with the corresponding unmasked bit
of argument and provides an output for the
decision logic that sets the bit in Mi.

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Match logic:
Match logic for each word can be derived from the comparison Algorithm for two binary numbers.
First, we neglect the key bits and compare the argument in A if Aj=Fij for j=1,2,……n.
Two bits are equal if they are both1 or both 0. The equality of two bits can be expressed logically by the
Boolean function.
xj = Aj Fij + Aj' Fij'
Where xj = 1 if the pair of bits in position j are equal;
xj = 0 otherwise
for a word i to be equal to the argument in A we must have all xj variables equal to 1. This is the
condition for setting the corresponding match bit Mi to 1. The Boolean function for this condition is
Mi = x1 x2 x3……………..n.
And constitutes the AND operation of all pairs of matched bits in a word.

We now include the key bit Kj in the comparison Logic.

If Kj = 0, the corresponding bits of Aj and Fij need no comparison
If Kj =1, they must be compared.
The requirement is achieved by ORing each term with Kj1
xj + kj1 = xj if kj=1
=1 if kj=0
When kj = 1, we have kj'=0 and xj + 0 = xj
When kj = 0, we have kj' = 1 and xj+1=1.
A term ( xj + kj' ) will be in the state 1 if its pair of bits is not compared. This is necessary because each
term is ANDed with all other terms so that output of 1 will have no effect. The comparison of the bits
has an effect only when kj = 1.
The match logic for word i in an associative memory can now be expressed by the following Boolean
function.
Mi = ( x1 + k1' ) ( x2 + K2' ) ( x3 + k3' )…………… ( xn + kn' )
A match will occur and Mi will be equal to 1 if all terms are equal to1. If we substitute the original
definition of xj, the Boolean function is

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Where ᴫ is a product symbol designating the AND operation of all n terms we need m such functions,
one for each word i=1, 2, 3……………m.

Note: Mi will be logic 1 if a match occurs and 0 if no matches occurs.

Read operation: If more than one word in memory matches the un masked argument field, all the
matched words will have 1’s in the corresponding bit position of the match register. It is then necessary
to scan the bits of the match register one at a time. The matched words are read in sequence by applying
a Read signal to each word line whose corresponding Mi bit is a 1.

Write operation:
If unwanted words have to be deleted and new words inserted one at a time, there is a need for special
register to distinguish between active and inactive words. This register sometimes called a Tag register
would have a many bits as there are words in memory.

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For every active word stored in memory, the corresponding bit in Tag register is set to 1. A word is
deleted from memory by clearing its tag bit to 0. If the Tag register is cleared to 0, then it is used to
specify an empty location.

CACHE MEMORY:
 If the active portions of the program and the data are placed in a fast small memory, the average
memory access time can be reduced, thus reducing the total execution time of the program. Such a
fast small memory is called cache memory. The cache memory access time is less than access time
of main memory by a factor 5 to 11.
 The cache is the only a small fraction of the size of main memory. It is placed between the CPU and
main memory.
 When the CPU needs to access memory, the cache is examined. If the word is found in the cache, it
is read from the fast memory. If the word addressed by the CPU in not found in the cache, the main
memory s accessed to read the word.
 The performance of cache memory is frequently measured in terms of quantity called hit ratio.
When the CPU refers to memory and finds the word in cache, it is said to produce a hit. If the word
is not found in cache, it is in main memory and it comets a miss.
 The ratio of the no of hits divided by the total CPU references to memory (hits plus misses) is the
hit ratio.
 The average memory access time of a computer system can be improved considerably by use of a
cache. If the hit ratio is high enough so that most of the time the CPU accesses the cache instead of
main memory, the average access time is closer to the access time of the fast cache memory.
 The Transformation of data from main memory to cache memory is referred to as mapping process.
Three types of mapping procedures.

1. Associative mapping
2. Direct mapping.
3. Set-associative mapping.

Example for three types of mapping:

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The main memory can store 32k words of 12 bits each. The cache is capable of storing 512 of these
words at any given time. For each word stored in cache, there is a duplicate copy in main memory.

The CPU communicates with both memories. It first sends a 15 bit address to cache. If there is a hit, the
CPU accepts the 12 bit data from cache. If there is a miss, the CPU reads the word from main memory
and the word is then transferred to cache.

Associative mapping:
 The fastest and most flexible cache organization uses an associative memory. The associative
memory stores both address and content (data) of the memory word. This permits any location in
cache to store any word from main memory.
 The diagram shows 3 words presently stored in the cache. The address value of 15 bits is shown as
5-digit octal number and its corresponding 12-bit word is shown as a 4-digit octal number.
 A CPU address of 15 bits is placed in the argument register and the associative memory is searched
for matching address. If the address is found, the corresponding 12-bit data is read and sent to the
CPU.

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 If no match occurs, the main memory is accessed for the word. The address data pair is then
transferred to the associative cache memory.
 If the cache is full, an address-data pair must be displaced to make room for a pair that is needed
and not presently in the cache. The decision as to what pair is replaced is determined from the
replacement algorithm that the designer chooses for the cache. For example first-in-first- out (FIFO)
replacement policy.

Direct mapping:
 The CPU address of 15 bits is divided into two fields. The 9 least significant bits constitute the
index field and the remaining 6 bits from the tag field.
 The main memory needs an address that includes both the tag and the indexed bits. The no of bits in
the indexed field is equal to the number of address bits required to access the cache memory.

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 For example, there are 2k words in the cache memory and 2n words in main memory. The n-bit
address is divided into two fields: k bits for the indexed field and n-k bits for tag field.
 The direct mapping cache organization uses the n-bit address to access the main memory and the k-
bit index to access cache. The internal organization of the words in the cache memory is shown in
fig.
 Each word in cache consists of the data word and its associated tag. When a new word is first
brought into the cache, the tag bits are stored along side the data bits.
 When the CPU generates a memory request, the indexed field is used for the address to access the
cache. The tag field of the CPU address is compared with the tag in the word read from the cache.
 If the two tags match, there is a hit and desired data word is in cache. If there is no match, there is a
miss and the required word is read from main memory. It is then stored in the cache together with
the new tag, replacing the previous value.

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 The word at address 0 is presently stored in the cache (index=000, tag=00, data=1200).
 Suppose that the CPU now wants to access the word at address 0200.The index address is 000, so it
is used to access the cache. The two tags are then compared. The cache tag is 00 but the address tag
is 02, Which does not produce a match.
 Therefore, the main memory is accessed and the data word 5670 is transferred to the CPU. The
cache word at index address 000 is then replaced with a tag of 0.2 and data of 5670.
Disadvantage:
The bit ratio can drop considerably if two or more words whose addresses have the same index but
different tags are accessed repeatedly.
Direct mapping cache with block size of 8 words:
 The index field is now divided into two fields: block field and word field. In a 512-word cache,
there are 64-blocks of 8-words each, since 64*8=512.
 The block number is specified with a 6-bit field and the word with in the block is specified with 3-
bit field. The tag field store with in the cache this common to all 8-words of the same block.

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 Every time a miss occurs, an entire block of 8-words must be transferred from main memory to
cache memory. Although this takes extra time, the bit ratio will likely improve with a larger block
size because the sequential nature of computer programs.

Set associative mapping:

 Why: The disadvantage of direct mapping is that two words with the same index in their address
but with different tag values cannot reside in cache memory at the same time.

 The set‒Associative mapping is an improvement over the direct mapping organization in that each
word of cache can store two or more words of memory under the same index address.

 Each data word is stored together with its tag and the number of tag‒data items in one word of
cache is said to form set.

Example:

Each index address refers to two data words and their associated tags. Each tag requires 6 bits and each
data word has 12 bits, so the word length is 2(6+12) = 36 bits.

An index address of 9 bits can accommodate 512 words. Thus the size of cache memory is 512x36. It
can accommodate 1024 words of main memory since each word of cache contains two data words.

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 The words stored at addresses 01000 and 02000 of main memory at index addresses 000. Similarly,
the words at addresses 02777 and 00777 are stored in cache at index address 777.

 When the CPU generates a memory request, the index value of the address is used to access the
cache. The tag field of the CPU address is then compared with both tags in the cache to determine if
a match occurs.

 The comparison logic is done by an associative search of the tags in the set similar to an associative
memory search. Thus the name “set‒associative”.

 The hit ratio will improve as the set size increases because more words with the same index but
different tags can reside in cache.

 An increase in the set size increases the number of bits in words of cache and requires more
complex comparison logic.

 When a miss occurs in a set‒associative cache and the set is full, it is necessary to replace one of the
tag‒data items with a new value. The most common Replacement Algorithms (FIFO, LRU) are
used.

 The FIFO procedure selects for replacement the item that has been in the set the longest.

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 The LRU (Least recently used) selects for replacement the item that has been least recently used by
the CPU. Both FIFO and LRU can be implemented by adding a few extra bits in each word of
cache.

Writing into cache:

When the CPU finds a word in cache during a read operation, the main memory is not involved in the
transfer. However, if the operation is a write, there are two ways that the system can proceed.

Write ‒Through method:

The simplest and most commonly used procedure is to update main memory with every memory write
operation, with the cache memory being updated in parallel if it contains the word at the specified
address. This is called write‒through method.

Advantage: Main memory always contains the same data as the cache. This characteristic is important
in systems with direct memory access transfers.

Write ‒ back: Only the cache location is updated during a write operation. The location is then marked
by a flag so that later when the word is removed from the cache it is copied into main memory.

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