Datasheet

MM32SPIN05x

32­Bit Microcontroller Based on Arm® Cortex®­M0

Version: 1.23_q

MindMotion reserves the right to change the relevant information without prior notification.
 Content
1 General Introduction 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Specification 3
2.1 Device contrast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
® ®
2.2.1 Arm Cortex ­M0 with embedded flash memory and SRAM . . . . . . . . . . . . . . . . . 4
2.2.2 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.4 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.5 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.8 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.9 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.10 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.11 Low­power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.13 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.14 Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . . . . . . . . . 11
2.2.15 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.16 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.17 General­purpose inputs/outputs (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.18 Analog­to­digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.19 Hardware Dvision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.20 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.21 Serial wire debug port (SWDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.22 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Pin definition 14

4 Memory mapping 24

5 Electrical characteristics 26
5.1 Test condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.1 Typical value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.2 Typical curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.3 Load capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.4 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.5 Power scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1.6 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1
 5.3.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.3 Operating conditions at power­up/power­down . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.4 Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 30
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.8 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3.10 Absolute Maximum (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.11 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.12 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.13 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.15 12­bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.17 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6 Package information 57
6.1 Packaging LQFP48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2 LQFP32 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3 Packaging QFN32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.4 QFN20 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.5 TSSOP20 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7 Ordering information 67

8 Revision history 68

2
 List of Figures
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 LQFP48 packet pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 LQFP32 packet pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 QFN32 packet pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 QFN20 packet pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 TSSOP20 packet pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Load condition of the pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10 Power scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12 Typical current consumption in standby mode vs. temperature at VDD = 3.3V . . . . . . . . . . . . 32
13 Typical current consumption in stop mode vs. temperature at VDD = 3.3V . . . . . . . . . . . . . . 33
14 High­speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 35
15 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
16 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
17 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
18 I2C bus AC waveform and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
19 SPI timing diagram­slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
20 SPI timing diagram­slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
21 SPI timing diagram­master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
22 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
23 Power supply and reference power supply decoupling circuit . . . . . . . . . . . . . . . . . . . . . 55
24 LQFP48 ­ 48­pin low­profile quad square flat package . . . . . . . . . . . . . . . . . . . . . . . . . 57
25 LQFP32 ­ 32­pin low­profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 59
26 QFN32 ­ 32­pin quad flat no­leads package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
27 QFN20 ­ 20­pin quad flat no­leads package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
28 TSSOP20 ­ 20­lead thin shrink small outline package outline . . . . . . . . . . . . . . . . . . . . . 65
29 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3
 List of Tables
1 MM32SPIN05x device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Low power mode list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Alternate functions for PA port AF0­AF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Alternate functions for PB port AF0­AF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Alternate functions for PC port AF0­AF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Alternate functions for PD port AF0­AF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14 Operating conditions at power­up/power­down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
15 Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . 31
16 Typical and maximum current consumption in stop and standby modes(2) . . . . . . . . . . . . . . 32
17 Typical current consumption in Run mode, code executing from Flash . . . . . . . . . . . . . . . . 33
18 Typical current consumption in sleep mode, code executing from Flash . . . . . . . . . . . . . . . 34
19 On­chip peripheral current consumption(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
20 High­speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
21 HSE 8∼ 24 oscillator characteristics(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
22 HSI oscillator characteristics(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
23 LSI oscillator characteristics(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
24 Low­power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
25 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
26 Flash memory endurance and data retention(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
27 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
28 MCU ESD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
29 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
30 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
31 I/O AC characteristics(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
32 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
33 TIMx(1) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
34 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
35 SPI characteristics(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
36 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
37 Maximum RAIN at fADC = 15MHz(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
38 ADC Accuracy ­ Limit Test Conditions(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
39 Temperature sensor characteristics(3)(4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
40 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
41 LQFP48 size description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
42 LQFP32 size description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4
43 QFN32 size description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
44 QFN20 size description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
45 TSSOP20 size description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5
General Introduction
DS_MM32SPIN05x_q_Ver1.23

1 General Introduction
General Introduction

1.1 Introduction

This product incorporates a high performance 32bit microcontroller with the core of Arm®
Cortex® ­M0. The highest operating frequency is up to 72MHz, with built­in high­speed
memory, a rich set of I/O ports and peripherals connected to the external bus. This product
contains one 12bit ADC, one comparator, one 16­bit general­purpose timer, one 32­bit
general­purpose timer, three 16­bit basic timers, one 16­bit advanced timer, and standard
communication interfaces, including one I2C, two SPI and two UART interfaces.

The device works between 2.0V to 5.5V range. The regular temperature for the device is
­40◦ C to +85◦ C and ­40◦ C to +105◦ C extended temperature range are also available. A
comprehensive set of power­saving mode allows the design of low­power applications.

The devices are available in 5 different packages: LQFP48, LQFP32, QFN32, QFN20
and TSSOP20.

The abundant peripherals make this microcontroller suitable for a variety of applications:

• Motor drive and application control

• Medical and handhled devices
• PC gaming peripherals and GPS platform
• Industrial applications: programmable controllers (PLCs), inverters, printers and scan­
ners
• Alarm system, video intercom, heating, ventilation and air conditioning

1.2 Product Characteristics

• Core and system
– 32­bit Arm® Cortex® ­M0 processor as the core
– Maximum operating frequency is up to 72MHz
– Single cycle 32­bit hardware multiplier
– Hardware divider(32bit)
• Memory
– 32K bytes of Flash memory
– 4K bytes of SRAM
– Boot loader supports Chip Flash and ISP (In­System Programming)
• Clock, reset and power management

www.mm32mcu.com 1/68
General Introduction
DS_MM32SPIN05x_q_Ver1.23

– 2.0V to 5.5V power supply

– Power­on/Power­down reset (POR/PDR), Programmable voltage detector (PVD)
– External 4 ∼ 24MHz high speed crystal oscillator
– Embedded factory­tuned 48/72MHz high speed oscillator
• Low­power
– Sleep, Stop and Standby modes
• One 12­bit ADC and 1µS of conversion time (up to 13 channels)
– Conversion range: 0 to VDDA
– Support sampling time and resolution configuration
– On­chip temperature sensor
– On­chip voltage sensor
• One comparator
• One 5­channel DMA controller
– Supported peripherals: Timer, UART, I2C, SPI and ADC
• Up to 39 fast I/Os:
– All I/O ports can be mapped to 16 external interrupts
– All ports are capable of inputting and outputting 5V signals
• Debug mode
– Serial wire debug (SWD)
• Up to 9 timers
– One 16­bit 4­channel advanced­control timer with 4­channel PWM output, dead­
time generation and emergency stop
– One 16­bit timer and one 32­bit timer, with up to 4 IC/OC, usable for IR control
decoding
– Two 16­bit timer, with one IC/OC, one OCN, deadtime generation and emer­
gency stop and modulator gate for IR control
– One 16­bit timer, with one IC/OC
– Two watchdog timers (independent and window type)
– One SysTick timer: 24­bit downcounter
• Up to 5 Communication interfaces
– Two UARTs
– One I2C
– Two SPIs
• 96­bit unique ID (UID)
• Packages LQFP48, LQFP32, QFN32, QFN20 and TSSOP20
For more information about the complete product, refer to Section 2.2 of the data sheet.
The relevant information about the Cortex® ­M0, please refer to Cortex® ­M0 technical
reference manual.

www.mm32mcu.com 2/68
Specification
DS_MM32SPIN05x_q_Ver1.23

2 Specification
Specification

2.1 Device contrast

Table 1. MM32SPIN05x device features and peripheral counts
Device
MM32SPIN05PF MM32SPIN05PT MM32SPIN05NT MM32SPIN05NW/TW
Peripheral
Flash memory ­K Bytes 32 32 32 32
SRAM ­K Bytes 4 4 4 4

General purpose
4 4 4 4
(16 bit)
Timers

General purpose
1 1 1 1
(32 bit)

Advanced
1 1 1 1
control
UART 2 2 2 2
Common
I2C 1 1 1 1
interfaces
SPI 2 1 1 1
GPIOs 39 25 27 16

12­bit Number 1 1 1 1

ADC Channel 13 13 13 9
Comparators 1
CPU frequency 72 MHz
Operating voltage 2.0V ∼ 5.5V
Packages LQFP48 LQFP32 QFN32 QFN20/TSSOP20

www.mm32mcu.com 3/68
Specification
DS_MM32SPIN05x_q_Ver1.23

AHB Flash Flash

interface

System
CPU
AHB SRAM
Bus Matrix

DMA
DMA

AHB APB1 APB1

AHB APB2 APB2

AHB

ADC1 SPI1 PWR IWDG

RCC COMP I2C1
TIM 1 WWDG
TIM14 MCUDBG UART2 TIM 3
TIM16 TIM 2
GPIOA/B/C/D TIM17 SPI2
SYSCFG
UART1
HWDIV

DMA request
444076

Figure 1. Block diagram

2.2 Summary

2.2.1 Arm® Cortex® ­M0 with embedded flash memory and SRAM
The Arm® Cortex® ­M0 processor is configurable and has multilevel pipeline 32bit reduced
instruction set processor, and characterized by high performance and low power consump­
tion.

2.2.2 Embedded flash memory

The embedded flash memory is up to 32K bytes, usable for storing programs and data.

2.2.3 Embedded SRAM

4K Bytes of embedded SRAM.

2.2.4 Nested vectored interrupt controller (NVIC)

This product embeds a nested vectored interrupt controller, which can handle multiple
maskable interrupting channels (excluding 16 Cortex® ­M0 interrupt lines) with 16 pro­

www.mm32mcu.com 4/68
Specification
DS_MM32SPIN05x_q_Ver1.23

grammable priorities.

• Tightly coupled NVIC enables low latency interrupt response

• Interrupt vector entry address directly enters into the core
• Tightly coupled NVIC interfaces
• Allow early processing of interrupts
• Handle higher priority interrupts that arrive late
• Support tail­chaining of interrupts
• Automatically saves the processor state
• Offer automatic recovery when the interrupt returns with no instruction overhead

This module provides flexible interrupt management with minimal interrupt latency.

2.2.5 Extended interrupt/event controller (EXTI)

The external interrupt/event controller consists of multiple edge detectors used to generate
interrupt/event requests. Each interrupt line can be independently configured to select
the trigger event (rising edge, falling edge or both) and can be masked independently.
A pending register maintains the status of all interrupt requests. The EXTI can detect a
signal with a pulse width shorter than the internal AHB clock period. All GPIOs can be
connected to the 16 external interrupt lines.

2.2.6 Clocks and startup

System clock selection is performed on startup, however the internal 48 MHz oscillator
is selected as default CPU clock on reset. Then an external 2∼24 MHz clock with failure
monitoring function can be selected. If an external clock failure is detected, the clock
will be isolated. The system automatically switches back to the internal oscillator. If an
interrupt is enabled, the software can receive the corresponding interrupt.

Multiple prescalers are used to configure AHB frequency and high­speed APB (APB2 and
APB1) domain. The maximum frequency of AHB and high­speed APB is 72MHz. Please
refer to the clock drive diagram in figure 2.

www.mm32mcu.com 5/68
Specification
DS_MM32SPIN05x_q_Ver1.23

Figure 2. Clock tree

2.2.7 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three
boot options：

• Boot from User Flash memory

• Boot from System Memory
• Boot from embedded SRAM

The boot loader is stored in the system memory, and can reprogram the flash by UART1

www.mm32mcu.com 6/68
Specification
DS_MM32SPIN05x_q_Ver1.23

2.2.8 Power supply schemes

• VDD = 2.0V ∼ 5.5V: external power supply for I/Os and the internal regulator through
VDD pins.
• VSSA , VDDA = 2.0V ∼ 5.5V：external power supply for reset modules and oscillators. VDDA
and VSSA must be connected to VDD and VSS .

2.2.9 Power supply supervisors

This product has integrated power­on reset (POR)/power­down reset (PDR) circuit. The
circuit remains in the working state and ensures proper operation above a threshold of
2.0V. When VDD is below a specified threshold (VPOR/PDR ), the device will be placed in the
reset state, without the need for an external reset circuit.

Additionally, the device features an embedded programmable voltage detector (PVD) that
monitors the VDD /VDDA power supply and compares it to the threshold VPVD . When VDD is
below or above the threshold VPVD , an interrupt can be generated. The interrupt handler
will send a warning message or switch the microcontroller to the safe mode. The PVD
function should be enabled by a program.

2.2.10 Voltage regulator

The voltage regulator converts the external voltage into the internal digital logic operating
voltage. The voltage regulator remains in the working state after reset.

2.2.11 Low­power modes

The product support lowpower mode to achieve the best compromise between low power
consumption, short startup time and multiple wakeup events.

Table 2. Low power mode list

Influence on 1.5V area Influence on Voltage
Mode Entry Wakeup
clock VDD area clock regulator
WFI (Wait for
SLEEP NOW or Any interrupt CPU clock off, no
Interrupt)
SLEEP ON EXIT influence on other clock
WFE (Wait for N/A On
Wake­up event and ADC clock
Event)
Any arbitrary
PDDS bit
interrupt (set in
Stop SLEEPDEEP bit All 1.5V area clocks are HSI and HSE On
the external
WFI or WFE off oscillator off
interrupt register)
WKUP pin rising
PDDS bit
edge, NRST pin
Standby SLEEPDEEP bit Off
external reset,
WFI or WFE
IWDG reset

www.mm32mcu.com 7/68
Specification
DS_MM32SPIN05x_q_Ver1.23

Sleep mode
In the Sleep mode, only the CPU stops working. All peripherals continue to operate and
can wake up the CPU when an interrupt/event occurs.

Stop mode
The Stop mode minimizes the power consumption while retaining the content of SRAM
and registers. The HSI oscillator and HSE crystal oscillator are also shut down in the
Stop mode. The microcontroller can be woken up from the Stop mode by any of the EXTI
signals. The EXTI signal can be a wakeup signal from one of the 16 external I/O ports
and the output of the PVD.

Standby mode
The Standby mode can minimize the power consumption of the system. In the Standby
mode, the voltage regulator turns off when the CPU is in the deep sleep mode. The entire
1.5V power supply domain is disconnected. HSI and HSE oscillators are also turned
off. They can be woken up by the rising edge of WKUP pin, external reset of NRST pin
and IWDG reset. They also can be woken up by the watchdog timer without reset. The
contents of SRAM and registers will be lost.

2.2.12 Direct memory access controller (DMA)

The flexible 5 way universal DMA can manage memory to memory, peripheral to memory
and memory to peripheral transfers. The DMA controller supports the management of the
ring buffer, avoiding the generation of interrupts when the controller reaches the end of
the buffer.

Each channel has dedicated hardware DMA request logic, with support for software trigger
on each channel. The length, the source address and the destination address of the
transfer can be set separately by the software.

The DMA can be used with major peripherals: UART, I2C, SPI, ADC and general­purpose,
basic, advanced control timer TIMx.

2.2.13 Timers and watchdogs

The product includes one advanced timer, two general­purpose timers, three basic timers,
two watchdog timers and one SysTick timer.

The following table compares the functions of advanced control timer, general­purpose
timer and basic timer:

www.mm32mcu.com 8/68
Specification
DS_MM32SPIN05x_q_Ver1.23

Table 3. Timer feature comparison

Capture/­ Complem
Counter Counter Prescaler DMA request
Timer type Timer compare ­entary
resolution type factor generation
channels outputs
integer
Advanced Up, down,
TIM1 16­bit from 1 to Yes 4 Yes
control up/down
65536
integer
Up, down,
TIM2 32­bit from 1 to Yes 4 No
up/down
General 65536
purpose integer
Up, down,
TIM3 16­bit from 1 to Yes 4 No
up/down
65536
integer
TIM14 16­bit Up from 1 to Yes 1 No
65536
Basic
integer
TIM16 /
16­bit Up from 1 to Yes 1 Yes
TIM17
65536

Advanced­control timer ( TIM1 )

The advanced control timer is composed of one 16­bit counter, four capture/compare chan­
nels and one three­phase complementary PWM generator. It has complementary PWM
outputs with dead time insertion and can be used as a complete general­purpose timer.
Four independent channels can be used for:

• Input capture
• Output compare
• PWM generation (edge or center alignment mode)
• Single pulse output

If configured as a 16­bit general­purpose timer, it has the same features as a TIM2 timer.
If configured as a 16­bit PWM generator, it has full modulation capability (0 ∼ 100%).

In the debug mode, the counter can be frozen and the PWM output is disabled to cut off
the switches controlled by these outputs.

Many features are shared with those of generalpurpose TIM timers which have the same
architecture. The advanced control timer can therefore work together with the TIM timers
via the Timer Link feature for synchronization or event chaining.

General­purpose timers (TIMx)

Two synchronizable general­purpose timers (TIM2, TIM3) are built into the product. The

www.mm32mcu.com 9/68
Specification
DS_MM32SPIN05x_q_Ver1.23

general­purpose timer has one 16/32bit auto­load up/down counter, one 16­bit prescaler
and four independent channels. Each channel can be used for input capture, output com­
pare, PWM and single pulse mode output.

General­purpose timers 32­bit

The general­purpose timer has one 32­bit auto­load up/down counter, one 16­bit prescaler
and four independent channels. Each channel can be used for input capture, output com­
pare, PWM and single pulse mode output.

General­purpose timers 16­bit

The general­purpose timer has one 16­bit auto­load up/down counter, one 16­bit prescaler
and four independent channels. Each channel can be used for input capture, output com­
pare, PWM and single pulse mode output.

The general­purpose timers can work together with the advanced control timer via the
Timer Link feature for synchronization or event chaining. Their counters can be frozen in
the debug mode. Any of the general­purpose timer can be used to produce PWM outputs.
Each timer has independent DMA request mechanism.

These timers can also handle signals from incremental encoders and digital outputs from
1∼ 4 Hall sensors. Each timer can produce PWM outputs, or be seen as a simple time
reference.

Basic timer

TIM14
This timer is based on a 16­bit auto­reload upcounter and a 16­bit prescaler. TIM14 fea­
tures one single channel for input capture/output compare, PWM or onepulse mode out­
put. Its counter can be frozen in debug mode.

TIM16/TIM17
Every timer is based on a 16­bit auto­reload up­counter and a 16­bit prescaler. They
each have a single channel for input capture/output compare, PWM or one­pulse mode
output. TIM16 and TIM17 have a complementary output with dead time generation and
independent DMA request generation. Their counters can be frozen in debug mode.

Independent watchdog (IWDG)

The independent watchdog is based on an 8­bit prescaler and 12­bit down­counter. It is
clocked from an independent 40 KHz internal oscillator and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either
as a watchdog to reset the device when a problem occurs, or as a free running timer
for application timeout management. It is hardware or software configurable through the
option bytes. The counter can be frozen in debug mode.

www.mm32mcu.com 10/68
Specification
DS_MM32SPIN05x_q_Ver1.23

Window watchdog (WWDG)

The window watchdog is based on a 7­bit down­counter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen
in debug mode.

SysTick timer
This timer is dedicated to real­time operating systems, but could also be used as a stan­
dard down­counter. It features:

• A 24­bit down­counter
• Auto­reload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source

2.2.14 Universal asynchronous receiver/transmitter (UART)

UART provides hardware management of the CTS, RTS.

Compatible with ISO7816 smart card mode. The UART interface supports output data
lengths of 5 bits, 6 bits, 7 bits, 8 bits, and 9 bits.

All UART interface can be served by the DMA controller.

2.2.15 I2C interface

The I2C interface can operate in multimaster or slave modes. It can support Standard
mode,and Fast Mode.

It supports 7­bit or 10­bit addressing modes.

2.2.16 Serial peripheral interface (SPI)

The SPI interface, in slave or master mode, can be configured to 1 ∼ 32 bits per frame.
The maximum rate is 24M for master mode and 12M for slave mode.

All SPI interfaces can be served by the DMA controller.

2.2.17 General­purpose inputs/outputs (GPIO)

Each GPIO pin can be configured by software as an output (push­pull or open­drain), an
input (with or without pull­up/pull­down), or alternate peripheral function. Most GPIO pins
are shared with digital or analog alternate peripherals.

If required, the peripheral function of the I/O pins can be locked following a specific se­
quence in order to avoid spurious writing to the I/O registers.

www.mm32mcu.com 11/68
Specification
DS_MM32SPIN05x_q_Ver1.23

2.2.18 Analog­to­digital converter (ADC)

The product is embedded with one 12­bit analog­to­digital converter (ADC) which has up
to 13 external channels and is available for single­shot, one­cycle and continuous scan
conversion. In the scan mode, the acquisition value conversion is automatically performed
on a selected set of analog inputs.

All ADC can be served by the DMA controller.

The analog watchdog function allows to monitor one or all selected channels precisely.
An interrupt will occur when the monitored signal exceeds a preset threshold.

Events generated by general­purpose timers (TIMx) and the advanced control timer can
be cascaded internally to the trigger of the ADC respectively. The application can syn­
chronize the ADC conversion with the clock.

2.2.19 Hardware Dvision

The hardware division unit consists of four 32­bit data registers, which are dividend, divi­
sor, quotient and remainder, and can be done with signed or unsigned 32­bit division. The
hardware division control register USIGN can choose whether to have signed division or
unsigned division.

Each time the divisor register is written, the division operation is automatically triggered.
After the operation is completed, the result is written to the quotient and remainder regis­
ters. If the reader register, remainder register, or status register is read before the end,
the read operation is suspended until the end of the operation.

If the divisor is zero, an overflow interrupt flag will be generated.

2.2.20 Temperature sensor

The temperature sensor generates a voltage that varies linearly with temperature. The
temperature sensor is internally connected to the ADC input channel to convert the sensor
output to a digital value.

2.2.21 Serial wire debug port (SWDP)

Two­wire serial debug port (SW­DP) is embedded in the Arm.

An Arm SW­DP allows to be connected to a single­chip microcomputer through serial wire

debugging tools.

2.2.22 Comparator (COMP)

The product has one built­in comparator which can be used independently (suitable for
I/Os on all terminals) or in combination with the timer. It can also be used for a variety of
functions, including:

www.mm32mcu.com 12/68
Specification
DS_MM32SPIN05x_q_Ver1.23

• Trigger wakeup events in the low­power mode by analog signals

• Adjust the analog signal
• Combine with PWM outputs from timers to form a cycle­by­cycle current control loop
• Rail­to­rail comparator
• Each comparator has an optional threshold
– Alternate I/O pins
– The internal comparison voltage CRV can be AVDD or the partial voltage value
of the internal reference voltage
• Programmable hysteresis voltage
• Programmable rate and power consumption
• The output terminal can be redirected to an I/O port or multiple timer input terminals to
trigger the following events:
– Capture event
– OCref_clr event (cycle­by­cycle current control)
– Brake event to shut off PWM rapidly

www.mm32mcu.com 13/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

3 Pin definition

11

BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48

47

46

45

44

43

42

41

40

39

38

37
NC 1 36 PD3
PC13 2 35 PD2
PC14 3 34 PA13
PC15 4 33 PA12
PD0-OSC_IN 5 32 PA11
PD1-OSC_OUT 6
LQFP48 31 PA10
nRST 7 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0-WKUP 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13

14

15

16

17

18

19

20

21

22

23

24
VSS
VDD
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11

485629

Figure 3. LQFP48 packet pinout

www.mm32mcu.com 14/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

BOOT0-PB8

PA15
VSS

PB7

PB6
PB5

PB4

PB3
29

27

26

25
31

30

28
32
VDD 1 24 PA14
PD0-OSC_IN 2 23 PA13
PD1-OSC_OUT 3 22 PA12
nRST 4 21 PA11
LQFP32
VDDA 5 20 PA10

PA0-WKUP 6 19 PA9

PA1 7 18 PA8

PA2 8 17 VDD
10

11

12

13

14

15

16
9
PA3

PA4

PA5

PA6

PA7

PB0

PB1
VSS
580827

Figure 4. LQFP32 packet pinout

www.mm32mcu.com 15/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

BOOT0

PA15
PB 5
PB 6

PB 4

PB 3
PB7
PB8
32

31

30

29

28

27

26

25
VDD 1 24 PA14

PD0-OSC_IN 2 23 PA13

PD1-OSC_OUT 3 22 PA12

nRST 4 21 PA11
QFN32
VDDA 5 20 PA10
Exposed Pad PA9
PA0-WKUP 6 19

PA1 7 18 PA8

PA2 8 17 VDD
10

11

12

13

14

15

16
9
PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2
VSS

633802

Figure 5. QFN32 packet pinout

PB7

PB6

PB4

PB3
PA6
20

19

18

17

16

nRST 1 15 PA14

PD0-OSC_IN 2 14 PA13

3
QFN20 13
PD1-OSC_OUT PB14
4 12
VSSA-VSS
- PB13

VCap 5 11 PB1
10
6

9
PA0-WKUP

PA5
VDD-VDDA

PA4

PB0

440673

Figure 6. QFN20 packet pinout

www.mm32mcu.com 16/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

PB6   PB4

PB7   PB3

PA6   PA14

nRST   PA13

PD0-OSC_IN   PB14
TSSOP20
PD1-OSC_OUT   PB13

VSSA-VSS   PB1

VCAP   PB0

VDD-VDDA   PA5

PA0-WKUP   PA4

628555

Figure 7. TSSOP20 packet pinout

Annotate: VCap should be setted to float or connect to ground with 0.1uF­0.01uF capacitor.

Table 4. Pin definitions

Pin number
I/O Main Alternate Additional
LQFP LQFP QFN TSSOP QFN Pin name Type(1)
(2)
level function functions functions
48 32 32 20 20
1 ­ ­ ­ ­ NC S ­ NC ­ ­
2 ­ ­ ­ ­ PC13 I/O FT PC13 TIM2_CH1 ­
3 ­ ­ ­ ­ PC14 I/O FT PC14 TIM2_CH2 ­
4 ­ ­ ­ ­ PC15 I/O FT PC15 TIM2_CH3 ­
PD0
5 2 2 5 2 I/O FT PD0 I2C1_SDA ­
OSC_IN
PD1
6 3 3 6 3 I/O FT PD1 I2C1_SCL ­
OSC_OUT
7 4 4 4 1 nRST I/O FT nRST ­ ­
8 ­ 0 ­ 4 VSSA S ­ VSSA ­ ­
VDDA
9 5 5 9 6 S ­ VDDA ­ ­
VDD(3)
UART2_CTS/
TIM2_CH1_ETR/
PA0
10 6 6 10 7 I/O TC PA0 SPI2_NSS/ ADC1_VIN[0]
WKUP
TIM2_CH3/
COMP1_OUT

www.mm32mcu.com 17/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

Pin number
I/O Main Alternate Additional
LQFP LQFP QFN TSSOP QFN Pin name Type(1)
(2)
level function functions functions
48 32 32 20 20
UART2_RTS/ ADC1_VIN[1]/
11 7 7 ­ ­ PA1 I/O TC PA1
TIM2_CH2 COMP1_INP[0]
UART2_TX/
ADC1_VIN[2]/
12 8 8 ­ ­ PA2 I/O TC PA2 TIM2_CH3/
COMP1_INP[1]
SPI2_NSS
UART2_RX/ ADC1_VIN[3]/
13 9 9 ­ ­ PA3 I/O TC PA3
TIM2_CH4 COMP1_INP[2]
SPI1_NSS/
TIM1_BKIN/ ADC1_VIN[4]/
14 10 10 11 8 PA4 I/O TC PA4
TIM14_CH1/ COMP1_INP[3]
I2C1_SDA
SPI1_SCK/
TIM2_CH1_ETR/
ADC1_VIN[5]/
15 11 11 12 9 PA5 I/O TC PA5 TIM1_ETR/
COMP1_INM[0]
I2C1_SCL/
TIM1_CH3N
SPI1_MISO/
TIM3_CH1/
TIM1_BKIN/
UART2_RX/ ADC1_VIN[6]/
16 12 12 3 20 PA6 I/O TC PA6
TIM1_ETR/ COMP1_INM[1]
TIM16_CH1/
TIM1_CH3/
COMP1_OUT
SPI1_MOSI/
TIM3_CH2/
TIM1_CH1N/
ADC1_VIN[7]/
17 13 13 ­ ­ PA7 I/O TC PA7 TIM14_CH1/
COMP1_INM[2]
TIM17_CH1/
TIM1_CH2N/
TIM1_CH3N
TIM3_CH3/
TIM1_CH2N/
18 14 14 13 10 PB0 I/O TC PB0 ADC1_VIN[8]
TIM1_CH1N/
TIM1_CH3

www.mm32mcu.com 18/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

Pin number
I/O Main Alternate Additional
LQFP LQFP QFN TSSOP QFN Pin name Type(1)
(2)
level function functions functions
48 32 32 20 20
TIM14_CH1/
TIM3_CH4/
TIM1_CH3N/
TIM1_CH4/
19 15 15 14 11 PB1 I/O TC PB1 ADC1_VIN[9]
TIM1_CH2N/
MCO/
TIM1_CH2/
TIM1_CH1N
20 ­ 16 ­ ­ PB2 I/O FT PB2 ­ ­
I2C1_SCL/
21 ­ ­ ­ ­ PB10 I/O FT PB10 TIM2_CH3/ ­
SPI2_SCK
I2C1_SDA/
22 ­ ­ ­ ­ PB11 I/O FT PB11 ­
TIM2_CH4
23 16 0 7 4 VSS S ­ VSS ­ ­
24 17 17 9 6 VDD S ­ VDD ­ ­
SPI2_NSS/
SPI2_SCK/
25 ­ ­ ­ ­ PB12 I/O FT PB12 TIM1_BKIN/ ­
SPI2_MOSI/
SPI2_MISO
SPI2_SCK/
SPI2_MISO/
TIM1_CH1N/
SPI2_NSS/
26 ­ ­ 15 12 PB13 I/O FT PB13 ­
SPI2_MOSI/
I2C1_SCL/
TIM1_CH3N/
TIM2_CH1
SPI2_MISO/
SPI2_MOSI/
TIM1_CH2N/
SPI2_SCK/
27 ­ ­ 16 13 PB14 I/O FT PB14 ­
SPI2_NSS/
I2C1_SDA/
TIM1_CH3/
TIM1_CH1

www.mm32mcu.com 19/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

Pin number
I/O Main Alternate Additional
LQFP LQFP QFN TSSOP QFN Pin name Type(1)
(2)
level function functions functions
48 32 32 20 20
SPI2_MOSI/
SPI2_NSS/
TIM1_CH3N/
28 ­ ­ ­ ­ PB15 I/O FT PB15 SPI2_MISO/ ­
SPI2_SCK/
TIM1_CH2N/
TIM1_CH2
MCO/
TIM1_CH1/
29 18 18 ­ ­ PA8 I/O FT PA8 ­
TIM1_CH2/
TIM1_CH3
UART1_TX/
TIM1_CH2/
UART1_RX/
30 19 19 ­ ­ PA9 I/O FT PA9 I2C1_SCL/ ­
MCO/
TIM1_CH1N/
TIM1_CH4
TIM17_BKIN/
UART1_RX/
TIM1_CH3/
31 20 20 ­ ­ PA10 I/O FT PA10 UART1_TX/ ­
I2C1_SDA/
TIM1_CH1/
SPI2_SCK
UART1_CTS/
SPI2_MOSI/
32 21 21 ­ ­ PA11 I/O FT PA11 TIM1_CH4/ ­
I2C1_SCL/
COMP1_OUT
UART1_RTS/
TIM1_ETR/
33 22 22 ­ ­ PA12 I/O FT PA12 SPI2_MISO/ ­
I2C1_SDA/
TIM1_CH2

www.mm32mcu.com 20/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

Pin number
I/O Main Alternate Additional
LQFP LQFP QFN TSSOP QFN Pin name Type(1)
(2)
level function functions functions
48 32 32 20 20
SWDIO/
SPI2_MISO/
34 23 23 17 14 PA13 I/O FT PA13 MCO/ ­
TIM1_CH2/
TIM1_BKIN
35 ­ ­ ­ ­ PD2 I/O FT PD2 ­ ­
36 ­ ­ ­ ­ PD3 I/O FT PD3 ­ ­
SWDCLK/
37 24 24 18 15 PA14 I/O FT PA14 UART2_TX/ ­
SPI1_NSS
SPI1_NSS/
38 25 25 ­ ­ PA15 I/O FT PA15 UART2_RX/ ­
TIM2_CH1_ETR
SPI1_SCK/
TIM2_CH2/
UART1_TX/
39 26 26 19 16 PB3 I/O TC PB3 ADC1_VIN[10]
TIM2_CH3/
TIM1_CH1/
TIM2_CH1
SPI1_MISO/
TIM3_CH1/
UART1_RX/
40 27 27 20 17 PB4 I/O TC PB4 ADC1_VIN[11]
TIM17_BKIN/
TIM1_CH2/
TIM2_CH2
SPI1_MOSI/
TIM3_CH2/
TIM16_BKIN/
41 28 28 ­ ­ PB5 I/O FT PB5 ­
MCO/
TIM1_CH3/
TIM2_CH3
UART1_TX/
I2C1_SCL/
42 29 29 1 18 PB6 I/O FT PB6 ­
TIM16_CH1N/
TIM2_CH1

www.mm32mcu.com 21/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

Pin number
I/O Main Alternate Additional
LQFP LQFP QFN TSSOP QFN Pin name Type(1)
(2)
level function functions functions
48 32 32 20 20
UART1_RX/
I2C1_SDA/
43 30 30 2 19 PB7 I/O TC PB7 ADC1_VIN[12]
TIM17_CH1N/
UART2_TX
44 31 31 ­ ­ BOOT0 I FT BOOT0 ­ ­
I2C1_SCL/
45 31 32 ­ ­ PB8 I/O FT PB8 TIM16_CH1/ ­
UART2_RX
I2C1_SDA/
TIM17_CH1/
46 ­ ­ ­ ­ PB9 I/O FT PB9 ­
TIM1_CH4/
SPI2_NSS
47 32 0 ­ 4 VSS S ­ VSS ­ ­
48 1 1 ­ 6 VDD S ­ VDD ­ ­
1.5V
­ ­ ­ 8 5 VCap S ­ regulator ­ ­
capacitor

1. I = input, O = output, S = power supply, HiZ = high resistance.

2. FT: 5V tolerant. Input signal should be between VDD and 5V.
TC: Standard I/O. Input signal does not exceed VDD.
3. Only exist in QFN20 and TSSOP package types.

Table 5. Alternate functions for PA port AF0­AF7

Pin
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Name
TIM2_CH1
PA0 ­ UART2_CTS SPI2_NSS TIM2_CH3 ­ ­ COMP1_OUT
_ETR
PA1 ­ UART2_RTS TIM2_CH2 ­ ­ ­ ­ ­
PA2 ­ UART2_TX TIM2_CH3 SPI2_NSS ­ ­ ­ ­
PA3 ­ UART2_RX TIM2_CH4 ­ ­ ­ ­ ­
PA4 SPI1_NSS ­ ­ TIM1_BKIN TIM14_CH1 I2C1_SDA ­ ­
TIM2_CH1
PA5 SPI1_SCK ­ TIM1_ETR ­ I2C1_SCL TIM1_CH3N ­
_ETR
PA6 SPI1_MISO TIM3_CH1 TIM1_BKIN UART2_RX TIM1_ETR TIM16_CH1 TIM1_CH3 COMP1_OUT
PA7 SPI1_MOSI TIM3_CH2 TIM1_CH1N ­ TIM14_CH1 TIM17_CH1 TIM1_CH2N TIM1_CH3N
PA8 MCO ­ TIM1_CH1 ­ ­ ­ TIM1_CH2 TIM1_CH3
PA9 ­ UART1_TX TIM1_CH2 UART1_RX I2C1_SCL MCO TIM1_CH1N TIM1_CH4
PA10 TIM17_BKIN UART1_RX TIM1_CH3 UART1_TX I2C1_SDA ­ TIM1_CH1 SPI2_SCK

www.mm32mcu.com 22/68
Pin definition
DS_MM32SPIN05x_q_Ver1.23

Pin
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Name
PA11 ­ UART1_CTS TIM1_CH4 ­ SPI2_MOSI I2C1_SCL ­ COMP1_OUT
PA12 ­ UART1_RTS TIM1_ETR ­ SPI2_MISO I2C1_SDA ­ TIM1_CH2
PA13 SWDIO ­ ­ ­ SPI2_MISO MCO TIM1_CH2 TIM1_BKIN
PA14 SWDCLK UART2_TX ­ SPI1_NSS ­ ­ ­ ­
TIM2_CH1
PA15 SPI1_NSS UART2_RX ­ ­ ­ ­ ­
_ETR

Table 6. Alternate functions for PB port AF0­AF7

Pin
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Name
PB0 ­ TIM3_CH3 TIM1_CH2N TIM1_CH1N TIM1_CH3 ­ ­ ­
PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TIM1_CH4 TIM1_CH2N MCO TIM1_CH2 TIM1_CH1N
PB3 SPI1_SCK ­ TIM2_CH2 UART1_TX TIM2_CH3 ­ TIM1_CH1 TIM2_CH1
PB4 SPI1_MISO TIM3_CH1 ­ UART1_RX ­ TIM17_BKIN TIM1_CH2 TIM2_CH2
PB5 SPI1_MOSI TIM3_CH2 TIM16_BKIN MCO ­ ­ TIM1_CH3 TIM2_CH3
PB6 UART1_TX I2C1_SCL TIM16_CH1N ­ TIM2_CH1 ­ ­ ­
PB7 UART1_RX I2C1_SDA TIM17_CH1N ­ UART2_TX ­ ­ ­
PB8 ­ I2C1_SCL TIM16_CH1 ­ UART2_RX ­ ­ ­
PB9 ­ I2C1_SDA TIM17_CH1 ­ TIM1_CH4 SPI2_NSS ­ ­
PB10 ­ I2C1_SCL TIM2_CH3 ­ ­ SPI2_SCK ­ ­
PB11 ­ I2C1_SDA TIM2_CH4 ­ ­ ­ ­ ­
PB12 SPI2_NSS SPI2_SCK TIM1_BKIN SPI2_MOSI SPI2_MISO ­ ­ ­
PB13 SPI2_SCK SPI2_MISO TIM1_CH1N SPI2_NSS SPI2_MOSI I2C1_SCL TIM1_CH3N TIM2_CH1
PB14 SPI2_MISO SPI2_MOSI TIM1_CH2N SPI2_SCK SPI2_NSS I2C1_SDA TIM1_CH3 TIM1_CH1
PB15 SPI2_MOSI SPI2_NSS TIM1_CH3N SPI2_MISO SPI2_SCK ­ TIM1_CH2N TIM1_CH2

Table 7. Alternate functions for PC port AF0­AF7

Pin
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Name
PC13 ­ ­ ­ ­ ­ ­ TIM2_CH1 ­
PC14 ­ ­ ­ ­ ­ ­ TIM2_CH2 ­
PC15 ­ ­ ­ ­ ­ ­ TIM2_CH3 ­

Table 8. Alternate functions for PD port AF0­AF7

Pin
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Name
PD0 ­ I2C1_SDA ­ ­ ­ ­ ­ ­
PD1 ­ I2C1_SCL ­ ­ ­ ­ ­ ­

www.mm32mcu.com 23/68
Memory mapping
DS_MM32SPIN05x_q_Ver1.23

4 Memory mapping
Memory mapping

Table 9. Memory mapping

Bus Boundary address Size Peripheral Notes
Main flash memory, system
0x0000 0000 ­ 0x0000 7FFF 32 KB memory, or SRAM, depends on
the configuration of BOOT
0x0000 8000 ­ 0x07FF FFFF ∼ 128 MB Reserved
0x0800 0000 ­ 0x0800 7FFF 32 KB Main Flash memory
0x0800 8000 ­ 0x1FFD FFFF ∼ 256 MB Reserved
Flash 0x1FFE 0000 ­ 0x1FFE 01FF 0.5 KB Reserved
0x1FFE 0200 ­ 0x1FFE 0FFF 3 KB Reserved
0x1FFE 1000 ­ 0x1FFE 1BFF 3 KB Reserved
0x1FFE 1C00 ­ 0x1FFF F3FF ∼ 256 MB Reserved
0x1FFF F400 ­ 0x1FFF F7FF 1 KB System memory
0x1FFF F800 ­ 0x1FFF F80F 16 B Option bytes
0x1FFF F810 ­ 0x1FFF FFFF ∼ 2 KB Reserved
0x2000 0000 ­ 0x2000 0FFF 4 KB SRAM
SRAM
0x2000 1000 ­ 0x2FFF FFFF ∼ 512 MB Reserved
0x4000 0000 ­ 0x4000 03FF 1 KB TIM2
0x4000 0400 ­ 0x4000 07FF 1 KB TIM3
0x4000 0800 ­ 0x4000 27FF 8 KB Reserved
0x4000 2800 ­ 0x4000 2BFF 1 KB Reserved
0x4000 2C00 ­ 0x4000 2FFF 1 KB WWDG
0x4000 3000 ­ 0x4000 33FF 1 KB IWDG
0x4000 3400 ­ 0x4000 37FF 1 KB Reserved
0x4000 3800 ­ 0x4000 3BFF 1 KB SPI2
APB1 0x4000 4000 ­ 0x4000 43FF 1 KB Reserved
0x4000 4400 ­ 0x4000 47FF 1 KB UART2
0x4000 4800 ­ 0x4000 4BFF 3 KB Reserved
0x4000 5400 ­ 0x4000 57FF 1 KB I2C1
0x4000 5800 ­ 0x4000 5BFF 1 KB Reserved
0x4000 5C00 ­ 0x4000 5FFF 1 KB Reserved
0x4000 6000 ­ 0x4000 63FF 1 KB Reserved
0x4000 6400 ­ 0x4000 67FF 1 KB Reserved
0x4000 6800 ­ 0x4000 6BFF 1 KB Reserved

www.mm32mcu.com 24/68
Memory mapping
DS_MM32SPIN05x_q_Ver1.23

Bus Boundaryaddress Size Peripheral Notes

0x4000 6C00 ­ 0x4000 6FFF 1 KB Reserved
APB1 0x4000 7000 ­ 0x4000 73FF 1 KB PWR
0x4000 7400 ­ 0x4000 FFFF 35 KB Reserved
0x4001 0000 ­ 0x4001 03FF 1 KB SYSCFG
0x4001 0400 ­ 0x4001 07FF 1 KB EXTI
0x4001 0800 ­ 0x4001 23FF 7 KB Reserved
0x4001 2400 ­ 0x4001 27FF 1 KB ADC1
0x4001 2800 ­ 0x4001 2BFF 1 KB Reserved
0x4001 2C00 ­ 0x4001 2FFF 1 KB TIM1
APB2 0x4001 3000 ­ 0x4001 33FF 1 KB SPI1
0x4001 3400 ­ 0x4001 37FF 1 KB DBGMCU
0x4001 3800 ­ 0x4001 3BFF 1 KB Reserved
0x4001 3C00 ­ 0x4001 3FFF 1 KB COMP
0x4001 4000 ­ 0x4001 43FF 1 KB TIM14
0x4001 4400 ­ 0x4001 47FF 1 KB TIM16
0x4001 4800 ­ 0x4001 4BFF 1 KB TIM17
0x4001 4C00 ­ 0x4001 7FFF 13 KB Reserved
0x4002 0000 ­ 0x4002 03FF 1 KB DMA
0x4002 0400 ­ 0x4002 0FFF 3 KB Reserved
0x4002 1000 ­ 0x4002 13FF 1 KB RCC
0x4002 1400 ­ 0x4002 1FFF 3 KB Reserved
0x4002 2000 ­ 0x4002 23FF 1 KB Flash interface
0x4002 2400 ­ 0x4002 5FFF 15 KB Reserved
AHB 0x4002 6000 ­ 0x4002 63FF 1 KB Reserved
0x4002 6400 ­ 0x4002 FFFF 39 KB Reserved
0x4003 0000 ­ 0x4003 03FF 1 KB HDIV
0x4003 0400 ­ 0x47FF FFFF ∼ 128 MB Reserved
0x4800 0000 ­ 0x4800 03FF 1 KB GPIOA
0x4800 0400 ­ 0x4800 07FF 1 KB GPIOB
0x4800 0800 ­ 0x4800 0BFF 1 KB GPIOC
0x4800 0C00 ­ 0x4800 0FFF 1 KB GPIOD
0x4800 1000 ­ 0x5FFF FFFF ∼ 384 MB Reserved

www.mm32mcu.com 25/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

5 Electrical characteristics
Electrical characteristics

5.1 Test condition

All voltages are based on VSS unless otherwise stated.

5.1.1 Typical value

Unless otherwise stated, typical data is based on TA = 25◦ C and VDD = 3.3V. These data
are for design guidance only and have not been tested.

5.1.2 Typical curve

Typical curves are for design guidance only and are not tested unless otherwise stated.

5.1.3 Load capacitor

The load conditions when measuring the pin parameters are shown in the figure below.

C = 50 pF

230907

Figure 8. Load condition of the pin

5.1.4 Pin input voltage

The measurement of the input voltage on the pin is shown in the figure below.

www.mm32mcu.com 26/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

VIN

984785

Figure 9. Pin input voltage

5.1.5 Power scheme

The power supply design scheme is shown in the figure below.

VCAP

VDD
VDD
1/2/3
Regulator

OUT Kernel logic

Level shifter

IO (CPU, Digital
GP I/Os & Memories)
IN Logic

5x100nF VSS
+1x4.7µF 1/2/3

VDD
VDDA

10nF Analog:
+1µF $'& RC, PLL, COMP ...

VSSA

782609

Figure 10. Power scheme

5.1.6 Current consumption measurement

The measurement of the current consumption on the pin is shown in the figure below.

www.mm32mcu.com 27/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

I DD_VBAT
VBAT

I DD
VDD

VDDA

738329

Figure 11. Current consumption measurement scheme

5.2 Absolute maximum rating

If the load applied to the device exceeds the value given in the ”Absolute Group Maximum
Ratings” list (Table 10, Table 11), it may result in that the device is permanently damaged.
This is just to give the maximum load that can be tolerated, and does not mean that the
functional operation of the device is correct under these conditions. Long­term operation
of the device under maximum conditions can affect device reliability.

Table 10. Voltage characteristics

Symbol Description min max units

External main supply voltage

VDD ­ VSS ­ 0.3 5.8
(including VDDA and VSSA )(1)
V
Input voltage on the 5 Vtolerant pin
VSS ­ 0.3 5.8
VIN (2)

Input voltage on other pins (2) VSS ­ 0.3 VDD + 0.3

Voltage variations between
| △ VDDx | 50
different power pins mV
Voltage variations between
|VSSx − VSS | 50
different ground pins

1. All power (VDD , VDDA ) and ground (VSS , VSSA ) pins must always be connected to the
external power supply within the permissible range.
2. VIN maximum must always be respected. For information about the maximum allowed
injected current values, please see the table below.

Table 11. Current characteristics

Symbol Description Maximum Units

IVDD Total current into VDD /VDDA power lines (supply current) (1) 120

mA

www.mm32mcu.com 28/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Symbol Description Maximum Units

IVSS Total current out of VSS wire (outflow current) (1) 120
Output sink current on any I/O and control pins 20
IIO
Output current on any I/O and control pins ­18
(2)(3)
IINJ(PIN) Injection current on NRST pin ±5 mA
Injection current on OSC_IN pin of HSE and OSC_IN pin
IINJ(PIN) (2)(3) ±5 mA
LSE
IINJ(PIN) (2)(3) injection current on other pins (4) ±5 mA
Σ IINJ(PIN) (4) Total injection current on all I/O and control pins (4) ±25 mA

1. All main power (VDD , VDDA ) and ground (VSS , VSSA ) pins must always be connected to
the external power supply within the permissible range.
2. TThis current consumption must be correctly distributed to all I/O and control pins. The
total output current must not be sunk/pulled between two consecutive power pins that
refer to LQFP package with dense pins.
3. The reverse injection current can interfere with the analog performance of the device.
4. A positive injection current is induced by VIN > VDDA while a negative injection current
is induced by VIN < VSS . IINJ(PIN) must never be exceeded.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the
absolute sum of the positive and negative injected currents (instantaneous values).

5.3 Operating conditions

5.3.1 General operating conditions

Table 12. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency 0 72 MHz

fPCLK1 Internal APB1 clock frequency 0 fHCLK MHz
fPCLK2 Internal APB2 clock frequency 0 fHCLK MHz
VDD Standard operating voltage 2.0 5.5 V
◦ ◦ QFN20 266
TA =85 C(industrial) or TA =105 C
PD mW
(extended industrial) power dissipation TSSOP
Analog operating voltage
2.0 5.5
(1)
VDDA (ADC not used) Must be the same voltage as VDD
V
Analog operating voltage
2.5 5.5
(ADC used)
◦
TA Maximum power dissipation ­40 105 C
◦
TJ Junction temperature range ­40 125 C

1. It is recommended to power VDD and VDDA from the same source. A maximum differ­

www.mm32mcu.com 29/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

ence of 300 mV between VDD and VDDA can be tolerated during power­up and opera­
tion.

5.3.2 Thermal characteristics

The maximum junction temperature of the chip must not exceed the value given in the
”General operating conditions”.

The maximum junction temperature is calculated as follows:

Tj max = TA max + PD max × θ JA

TA max: Maximum ambient temperature

PD max: Total chip power consumption, including the sum of internal and IO power con­
sumption

Table 13. Package thermal characteristics

Symbol Description Value Unit

QFN20 Thermal resistance from

junction temperature to ambient 75
◦
θ JA C/W
temperature
TSSOP20 Thermal resistance from
junction temperature to ambient
temperature

5.3.3 Operating conditions at power­up/power­down

The parameters given in the table below are based on tests under normal operating con­
ditions.

Table 14. Operating conditions at power­up/power­down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate 300 ∞

tVDD (1) TA = 25◦ C µS/V
VDD fall time rate 300 ∞
Power­down
Vft (3) ­ 0 ­ mV
threshold voltage

1. All power­ups need to start at 0V, to ensure that the chip can be powered up reliably.

5.3.4 Embedded reset and power control block characteristics

The parameters given in the table below are based on the ambient temperature and the
VDD supply voltage listed in Table 12.

www.mm32mcu.com 30/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Table 15. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLS[3：0]=0000 (Rising edge) 1.82 V

Level selection of
PLS[3：0]=0000 (Falling edge) 1.71 V
VPVD programmable
PLS[3：0]=0001 (Rising edge) 2.12 V
voltage detectors
PLS[3：0]=0001 (Falling edge) 2.00 V
PLS[3：0]=0010 (Rising edge) 2.41 V
Level selection of
PLS[3：0]=0010 (Falling edge) 2.30 V
VPVD programmable
PLS[3：0]=0011 (Rising edge) 2.71 V
voltage detectors
PLS[3：0]=0011 (Falling edge) 2.60 V
PLS[3：0]=0100 (Rising edge) 3.01 V
PLS[3：0]=0100 (Falling edge) 2.90 V
PLS[3：0]=0101 (Rising edge) 3.31 V
PLS[3：0]=0101 (Falling edge) 3.19 V
PLS[3：0]=0110 (Rising edge) 3.61 V
PLS[3：0]=0110 (Falling edge) 3.49 V
Level selection of PLS[3：0]=0111 (Rising edge) 3.91 V
VPVD programmable PLS[3：0]=0111 (Falling edge) 3.79 V
voltage detectors PLS[3：0]=1000 (Rising edge) 4.21 V
PLS[3：0]=1000 (Falling edge) 4.09 V
PLS[3：0]=1001 (Rising edge) 4.51 V
PLS[3：0]=1001 (Falling edge) 4.39 V
PLS[3：0]=1010 (Rising edge) 4.81 V
PLS[3：0]=1010 (Falling edge) 4.69 V
(2)
VPDRhys PDR hysteresis 110 mV

VPOR/PDR Power on/down 1.66 V

reset threshold
(2)
TRSTTEMPO Reset duration 0.61 ms

1. The product behavior is guaranteed by design down to the minimum value VPOR/PDR .
2. Guaranteed by design, not tested in production.

Note: The reset duration is measured from power­on (POR reset) to the time when the user appli­
cation code reads the first instruction.

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the op­
erating voltage, temperature, I/O pin loading, device software configuration, operating fre­
quencies, I/O pin switching rate, program location in memory and executed binary code.

All Run­mode current consumption measurements given in this section are performed with
a reduced code.

www.mm32mcu.com 31/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Current consumption
The MCU is placed under the following conditions:

• All I/O pins are in analog input mode, and are connected to a static level —­ VDD or VSS
(no load)
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted to the fHCLK (0 ∼ 24 MHz is 0 waiting period
, 24 ∼ 48 MHz is 1 waiting period, 48 ∼ 72 MHz is 2 waiting periods ).
• The instruction prefetching function is on. When the peripherals are enabled：
fHCLK = fPCLK1 = fPCLK2 .

Note：The instruction prefetching function must be set before setting the clock and bus divider.

Table 16. Typical and maximum current consumption in stop and standby modes(2)
Max(1)
Symbol Parameter Conditions Unit
TA =25◦ C

Supply current in Stop mode Enter the stop mode after reset 6
IDD Supply current in Standby µA
Enter the standby mode after reset 0.4
mode

1. Data based on characterization results, not tested in production.The IO state is an

analog input.

90

80

70

60

50

40

30

20

10

0
TA = - 40°C TA = 25°C TA = 70°C TA = 105°C

Supply current in standby mode(uA)

148491

Figure 12. Typical current consumption in standby mode vs. temperature at VDD = 3.3V

www.mm32mcu.com 32/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

90

80

70

60

50

40

30

20

10

0
TA = - 40°C TA = 25°C TA = 70°C TA = 105°C

Supply current in stop mode(uA)

577187

Figure 13. Typical current consumption in stop mode vs. temperature at VDD = 3.3V

Typical current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input configuration, and are connected to a static level —­ VDD
or VSS (no load).
• All the peripherals are closed, unless otherwise specified.
• The Flash memory access time is adjusted to the fHCLK (0 ∼ 24 MHz is 0 waiting period
, 24 ∼ 48 MHz is 1 waiting period, 48 ∼ 72 MHz is 2 waiting periods ).
• The ambient temperature and VDD supply voltage conditions are summarized in Ta­
ble 12.
• The instruction prefetching function is on. When the peripherals are enabled：
fHCLK = fPCLK1 = fPCLK2 ..

Note: The instruction prefetch function must be set before the clock is set and the bus is divided.

Table 17. Typical current consumption in Run mode, code executing from Flash
Typ(1)
Symbol Parameter Conditions fHCLK All peripherals Unit
All peripherals
disabled
enabled(2)
72MHz 14.4 8.78
Supply current
IDD Internal clock 48MHz 9.57 6.25 mA
in operating mode
8MHz 2.21 1.66

1. The typical value is tested at TA = 25◦ Cand VDD = 3.3V.

www.mm32mcu.com 33/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Table 18. Typical current consumption in sleep mode, code executing from Flash
Typ(1)
Symbol Parameter Conditions fHCLK (2) All peripherals Unit
All peripherals
disabled
enabled(2)
72MHz 9.16 3.75
Supply current
IDD Internal clock 48MHz 6.44 2.71 mA
in sleep mode
8MHz 1.66 0.95

1. The typical value is tested at TA = 25◦ Cand VDD = 3.3V.

2. External clock is 8MHz, when fHCLK > 8MHz choose HSI 48MHz or HSI 72MHz.

On­chip peripheral current consumption

The current consumption of the on­chip peripherals is given in Table 19. The MCU is
placed under the following conditions:

• All I/O pins are in analog input mode, and are connected to a static level —­ VDD or VSS
(no load) .
• All peripherals are disabled except when explicitly mentioned.
• The given value is calculated by measuring the current consumption.
– With all peripherals clocked OFF
– With only one peripheral clocked on
• Ambient operating temperature and supply voltage conditions VDD summarized in Ta­
ble 12.

Table 19. On­chip peripheral current consumption(1)

Typical Typical
Peripheral Unit Peripheral Unit
consumption consumption
at 25 ◦ C at 25 ◦ C
HWDIV 2.17 SPI 7.92
GPIOD 0.75 TIM1 17.04
GPIOC 0.58 APB2 ADC 1.54
AHB GPIOB 0.71 SYSCFG 0.37
GPIOA 0.71 UART1 5.38
CRC 1.00 PWR 0.79
µA/MHz µA/MHz
DMA 4.38 I2C 9.58
PWM 1.75 WWDG 5.96
TIM17 3.29 APB1 TIM3 8.83
APB2 TIM16 3.17 TIM2 0.50
TIM14 3.17 UART2 5.96
COMP 0.58

1. fHCLK = 72MHz, fAPB1 = fHCLK /2, fAPB2 = fHCLK , the prescale coefficient for each device
is the default value.

www.mm32mcu.com 34/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

5.3.6 External clock source characteristics

High­speed external user clock generated from an external source

The characteristic parameters given in the following table are measured using a high­
speed external clock source, ambient temperature and power supply voltage meet the
conditions of General operating conditions.
Table 20. High­speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fHSE_ext 2 8 24 MHz
frequency(1)
OSC_IN input pin high level
VHSEH 0.7VDD VDD V
voltage
OSC_IN input pin low level
VHSEL VSS 0.3VDD V
voltage
tw(HSE) OSC_IN high or low time(1) 16 ns
(1)
tr(HSE) OSC_IN rise time 20 ns
(1)
tf(HSE) OSC_IN fall time 20 ns
(1)
Cin(HSE) OSC_IN input capacitance 5 pF
DuCy(HSE) Duty cycle 45 55 %
IL OSC_IN input leakage current VSS ≤ VIN ≤ VDD ±1 μA

1. Guaranteed by design, not tested in production.

VHSEH
90%

10%
VHSEL
tr(HSE) tf(HSE) tw(HSE) tw(HSE) t

THSE

External Clock IL
Source fHSE_ext OSC_IN

474122

Figure 14. High­speed external clock source AC timing diagram

www.mm32mcu.com 35/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

High­speed external clock generated from a crystal/ceramic

resonator
The high­speed external (HSE) clock can be supplied with an 4 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design simu­
lation results obtained with typical external components specified in the table below. In the
application, the resonator and the load capacitors have to be placed as close as possible
to the oscillator pins in order to minimize output distortion and startup stabilization time.
Refer to the crystal resonator manufacturer for more details on the resonator characteris­
tics (frequency, package, accuracy...).
Table 21. HSE 8∼ 24 oscillator characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

fOSC_IN Oscillator frequency 4 8 24 MHz

RF Feedback resistor 1000 kΩ
The proposed load
CL1
capacitance corresponds to the RS = 30Ω 30 pF
CL2 (3)
crystal serial impedance (RS ) (4)
VDD = 3.3V
I2 HSE current consumption VIN = VSS 4.5 mA
30pF load
gm Oscillator transconductance Startup 8.5 mA/V
(5)
tSU(HSE) Startup time VDD is stabilized 3 mS

1. The characteristic parameters of the resonator are given by the crystal/ceramic res­
onator manufacturer.
2. Drawn from comprehensive evaluation, not tested in production.
3. For CL1 and CL2 , it is recommended to use high­quality external ceramic capacitors
in the 5 pF to 25 pF (typical value) range, designed for high­frequency applications.
A suitable crystal or resonator should also be carefully selected. Usually, CL1 and
CL2 have the same parameter. The crystal manufacturer typically specifies a load
capacitance which is the serial combination of CL1 and CL2 . When choosing CL1 and
CL2 , the capacitive reactance of the PCB and MCU pins should be taken into account
(the combined pin and the PCB board capacitance can be roughly estimated as 10pF).
4. The relatively low value of the RF resistor offers a good protection against issues re­
sulting from use in a humid environment, due to the induced leakage and the bias
condition change. However, it is recommended to take this point into account if the
MCU is used in tough humidity conditions.
5. tSU(HSE) is the startup time, measured from the moment the software enables HSE to
a stable 8MHz oscillation is obtained. This value is measured for a standard crystal
resonator and it can vary significantly with the crystal manufacturer.

www.mm32mcu.com 36/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Resonator with integrated

capacitors

CL1

OSC_IN fHSE
Bias
8MHz RF controlled
resonator gain

REXT OSC_OUT

CL2
*In the sample RF=510KΩ REXT=510Ω

860676

Figure 15. Typical application with an 8 MHz crystal

5.3.7 Internal clock source characteristics

The characteristic parameters given in the table below are measured using ambient tem­
perature and supply voltage in accordance with general operating conditions.

High­speed internal (HSI) oscillator

Table 22. HSI oscillator characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency 48/72 MHz

◦ ◦
ACCHSI Accuracy of the HSI oscillator TA = ­40 C ∼ 105 C ­6 6 %
◦ ◦
ACCHSI Accuracy of the HSI oscillator TA = ­10 C ∼ 105 C ­4 4 %
ACCHSI Accuracy of the HSI oscillator TA = 25 ­1 1 %
tSU(HSI) HSI oscillator startup time 10 μS
HSI oscillator power
IDD(HSI) 200 μA
consumption

1. VDD = 3.3V, TA = ­ 40◦ C ∼ 85◦ C, unless otherwise specified.

2. Guaranteed by design, not tested in production.

Low­speed internal (LSI) oscillator

Table 23. LSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fLSI (2) Frequency 40 KHz

(2)
tSU(LSI) LSI oscillator startup time 100 μS
LSI oscillator power
IDD(LSI) (3) 1.1 1.7 μA
consumption

1. VDD = 3.3V, TA = ­40◦ C ∼ 105◦ C, Unless otherwise stated

www.mm32mcu.com 37/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

2. Comprehensive assessment, not tested in production.

3. Guaranteed by design, not tested in production.

Wake­up times from low power mode

The wake­up times listed in the table below are measured during the wake­up phase of
the internal clock HSI. The clock source used when waking up depends on the current
operating mode:

• Stop or Standby mode: The clock source is the oscillator

• Sleep mode: The clock source is the clock used when entering sleep mode

All times are measured using ambient temperature and supply voltage in accordance with
common operating conditions.

Table 24. Low­power mode wakeup timings

Symbol Parameter Conditions Max Unit

Wakeup from Sleep

tWUSLEEP (1) HSI clock wakeup 4.2 μS
mode
Wakeup from Stop
tWUSTOP (1) HSI clock wakeup < 2μS 12 μS
mode
HSI clock wakeup < 2μS
Wakeup from Standby
(1)
tWUSTDBY The regulator wakes up 230 μS
mode
from the off mode < 38μS

1. The wake­up time is measured from the start of the wake­up event to the user program
to read the first instruction.

5.3.8 Memory characteristics

Flash memory
Table 25. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max Unit

tprog 16­bit programming time 28 μS

Page (1024K bytes) erase
tERASE 8 10 mS
time
tME Mass erase time 30 40 mS
Read mode 9 mA
IDD Supply current Write mode 7 mA
Erase mode 2 mA

www.mm32mcu.com 38/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Table 26. Flash memory endurance and data retention(1)

Symbol Parameter Conditions Min Typ Max Unit

Endurance
NEND (erase 20000 K cycle
cycles)
Data TA = 105◦ C 20
tRET ◦
Year
retention TA = 25 C 100

1. Guaranteed by design, not tested in production.

5.3.9 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports) ,
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:

• EFT：A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC61000­4­4standard.

A device reset allows normal operations to be resumed.

The test results are given in the following table.

Table 27. EMS characteristics

Symbol Parameter Conditions Level/Class

Fast transient voltage burst

limits to be applied through VDD = 3.3V,TA =+25◦ C,
VEFT 100 pF on VDD and VSS fHCLK =48MHz. Conforming 2A
pinsto induce a functional to IEC61000­4­4
disturbance

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.

Therefore, it is recommended that users apply EMC software optimization and conduct
EMC­related prequalification tests.

www.mm32mcu.com 39/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Software recommendations
The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset
• Critical Data corruption (for example control registers)

Prequalification trials
Most of the common failures (unexpected reset and corrupted program counter) can be
reproduced by manually forcing a low level on NRST or a onesecond low level on the
crystal oscillator pins.

During ESD test, a voltage over the range of specification values can be directly applied to
the chip. When unexpected behavior is detected, the software needs to be strengthened
to prevent unrecoverable errors.

5.3.10 Absolute Maximum (Electrical Sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device
is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This
test conforms to the JEDECJS­001­2017/JS­002­2018 standard.

Static latch­up
Two complementary static tests are required on six parts to assess the latch­up perfor­
mance：

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD78E IC latch­up standard.

Table 28. MCU ESD characteristics

Symbol Parameter Conditions Max(1) Unit

Electrostatic discharge voltage TA = 25◦ C, Conforming to

VESD(HBM) ±6000
(Human body model) JEDECJS­001­2017
V
Electrostatic discharge voltage TA = 25◦ C, Conforming to
VESD(CDM) ±500
(Charging device model) JEDECJS­002­2018
TA = 25◦ C, Conforming to
ILU Latch­up current ±100 mA
JESD78E

www.mm32mcu.com 40/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

5.3.11 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 10 are derived from tests. All
I/O ports are compatible with CMOS.
Table 29. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

2.5V< VDD <

VIL Input low level voltage 0.3*VDD V
5.5V
2.5V< VDD <
VIH Input high level voltage 0.7*VDD V
5.5V
I/O pin Schmitt trigger voltage 2.5V< VDD <
Vhy 0.1*VDD V
(1)
hysteresis 5.5V
2.5V< VDD <
Ilkg Input leakage current(2) ­1 1 µA
5.5V
Weak pull­up equivalent 2.5V< VDD <
RPU 10 50 kΩ
(3)
resistor 5.5V
Weak pull­down equivalent 2.5V< VDD <
RPD 10 100 kΩ
(3)
resistor 5.5V
2.5V< VDD <
CIO I/O pin capacitance 10 pF
5.5V

1. The leakage could be higher than the maximum value, if negative current is injected
on adjacent pins.
2. Pull­up and pull­down resistors are MOS.

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±20mA.

In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in 5.2：

• The sum of the currents obtained from VDD for all I/O ports, plus the maximum operating
current that the MCU obtains on VDD , cannot exceed the absolute maximum rating IVDD .
• The sum of the currents drawn by all I/O ports and flowing out of VSS , plus the maximum
operating current of the MCU flowing out on VSS , cannot exceed the absolute maximum
rating IVSS .

Output voltage levels

Unless otherwise stated, the parameters listed in the table below are measured using the

www.mm32mcu.com 41/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

ambient temperature and VDD supply voltage in accordance with the condition of Table 12.
All I/O ports are CMOS compatible.
Table 30. Output voltage characteristics

SPEED[1：0] Symbol Parameter Conditions Min Typ Max Unit

Output low level

VOL (1) |IIO | = 6mA 0.40 V
voltage
VDD = 3.3V
Output high level
(2)
VOH 2.80 V
11 voltage
Output low level
VOL (1)(3) |IIO | = 8mA 0.40 V
voltage
VDD = 3.3V
Output high level
VOH (2)(3) 2.80 V
voltage
Output low level
VOL (2)(3) |IIO | = 20mA 0.80 V
voltage
VDD = 3.3V
Output high level
(2)(3)
VOH 2.20 V
voltage
Output low level
VOL (1) |IIO | = 6mA 0.40 V
voltage
VDD = 3.3V
Output high level
VOH (2) 2.80 V
10 voltage
Output low level
VOL (1)(3) |IIO | = 8mA 0.60 V
voltage
VDD = 3.3V
Output high level
(2)(3)
VOH 2.60 V
voltage
Output low level
VOL (2)(3) |IIO | = 20mA 1.00 V
voltage
VDD = 3.3V
Output high level
(2)(3)
VOH 1.80 V
voltage
Output low level
VOL (1) |IIO | = 6mA 0.60 V
voltage
VDD = 3.3V
Output high level
(2)
VOH 2.60 V
01 voltage
Output low level
VOL (1)(3) |IIO | = 8mA 0.60 V
voltage
VDD = 3.3V
Output high level
(2)(3)
VOH 2.40 V
voltage
Output low level
VOL (2)(3) |IIO | = 20mA 1.40 V
voltage
VDD = 3.3V
Output high level
VOH (2)(3) V
voltage

www.mm32mcu.com 42/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Input/output AC characteristics
The definitions and values of the input and output AC characteristics are given in figure 16
and Table 31, respectively.

Unless otherwise stated, the parameters listed in Table 31 are measured using the ambient
temperature and supply voltage in accordance with the condition Table 10.
Table 31. I/O AC characteristics(1)

SPEED[1：0] Symbol Parameter Conditions Min Typ Max Unit

Fall time from high

tf level output to low 4.0 ns
11
level output
Rise time from low CL =50pF,

tr level output to high VDD =3.3V 5.0 ns

level output
Fall time from high
tf level output to low 5.0 ns
10
level output
Rise time from low
tr level output to high 6.2 ns
level output
Fall time from high
tf level output to low 7.2 ns
01
level output
Rise time from low
tr level output to high 11.0 ns
level output

1. The speed of the I/O port can be configured via MODEx[1:0]. See the description of
the GPIO Port Configuration Register in this chip reference manual.
2. The maximum frequency is defined in figure 16.

www.mm32mcu.com 43/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

90% 10%
50% 50%

90%
10%
The external output

load is 50 pF tr (IO)out tr (IO)out

Maximum frequency is achieved if ((tr + tf) ≤ 2/3)T, and if the duty cycle is (45 ~ 55%)
when loaded by C/(see the i/O AC characteristics definition)

868304

Figure 16. I/O AC characteristics

5.3.12 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pullup resistor, RPU . Unless otherwise stated, the parameters listed in the table below are
measured using the ambient temperature and VDD supply voltage in accordance with the
condition of Table 10.

Table 32. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) (1) NRST input low level voltage ­0.3 0.3*VDD

V
NRST input high level
(1)
VIH(NRST) 0.7*VDD VDD
voltage
NRST Schmitt trigger voltage
Vhys(NRST) 0.1*VDD V
hysteresis
Weak pull­up equivalent
RPU VIN = VSS 50 kΩ
resistor(2)
VNF(NRST) (1) NRST input not filtered pulse 300 ns

1. Guaranteed by design, not tested in production.

2. The pull­up resistor is a MOS resistor.

www.mm32mcu.com 44/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

(1)
External reset circuit VDD VDD

100kΩ RPU
NRST(2) Internal reset
Filter
1µF

368560

Figure 17. Recommended NRST pin protection

1. The reset network is to prevent parasitic reset

2. The user must ensure that the potential of the NRST pin is below the maximum VIL(NRST)
listed in Table 32, otherwise the MCU cannot be reset.

5.3.13 Timer characteristics

The parameters given in the following tables are guaranteed by design.

For details on the characteristics of the I/O multiplexing function pins (output compare,
input capture, external clock, PWM output) , see subsubsec 5.3.11.

www.mm32mcu.com 45/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Table 33. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

1 tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK =
41.6 nS
24MHz
Timer external clock 0 fTIMxCLK
fEXT MHz
frequency on CH1 to CH4 fTIMxCLK =
0 24
24MHz
ResTIM Timer resolution 16 Bit
16bit counter clock cycle 1 65536 tTIMxCLK
tCOUNTER
when the internal clock is selected fTIMxCLK 24MHz 0.0417 2732 µS
65536 × 65536 tTIMxCLK
tMAX_COUNT The maximum possible count
fTIMxCLK 24MHz 178.9 S

1. TIMx is a generic name.

5.3.14 Communication interfaces

I2C interface characteristics

Unless otherwise specified, the parameters given in Table 34 are derived from tests per­
formed under the ambient temperature, fPCLK1 frequency and supply voltage conditions
summarized in Table 12.

The I2C interface conforms to the standard I2C communication protocol, but has the fol­
lowing limitations: SDA and SCL are not true pins. When configured as open­drain output,
the PMOS transistor between the pin and VDD Was closed but still exists.

The I2C I/Os characteristics are listed in Table 34, the alternate function characteristics of
I/Os (SDA and SCL) refer to subsubsec 5.3.11.
Table 34. I2C characteristics
Standard I2C(1) Fast I2C (1)(2)
Symbol Parameter Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 1.3 µs
tw(SCLH) SCL clock high time 4.0 0.6 µs
tsu(SDA) SDA setup time 250 100
th(SDA) SDA data hold time 0(3) 0(4) 900(3)
ns
tr(SDA) tr(SDL) SDA and SCL rise time 1000 2.0+0.1Cb 300
tf(SDA) tf(SDL) SDA and SCL fall time 300 300
th(STA) Start condition hold time 4.0 0.6
tsu(STA) Start condition setup time 4.7 0.6
tsu(STO) Stop condition setup time 4.0 0.6 µs
Time from Stop condition to
tw(STO:STA) 4.7 1.3
Start condition

www.mm32mcu.com 46/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Standard I2C(1) Fast I2C (1)(2)

Symbol Parameter Unit
Min Max Min Max
Cb Capacitive load of each bus 400 400 pF

1. Guaranteed by design, not tested in production.

2. fPCLK1 must be at least 3MHz to achieve standard mode I2C frequencies. It must be at
least 12MHz to achieve fast mode I2C frequencies.
3. The maximum Data hold time has only to be met if the interface does not stretch the
low period of SCL signal.
4. In order to span the undefined area of the falling edge of SCL, it must ensure that the
SDA signal has a hold time of at least 300nS.

VDD VDD

4.7KΩ 4.7KΩ
100 Ω
SDA
,&EXV 100 Ω
SCL

Start repeated

Start

t su(STA) Start
SDA
t f(SDA) t r(SDA) t su(SDA) t su(STA:STO)
Stop
t h(STA) t w (SCKL) t h(SDA)

SCL
t w (SCKH) t r(SCK) t f(SCK) t su(STO)

澳
130244

Figure 18. I2C bus AC waveform and measurement circuit(1)

1. Measurement point is set to the CMOS level：0.3VDD and 0.7VDD .

SPI characteristics
Unless otherwise specified, the parameters given in Table 35 are derived from tests per­
formed under the ambient temperature, fPCLKx frequency and VDD supply voltage condi­
tions summarized in Table 12.

Refer to subsubsec 5.3.11 for more details on the input/output alternate function charac­
teristics (NSS, SCK, MOSI, MISO).

www.mm32mcu.com 47/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Table 35. SPI characteristics(1)

Symbol Parameter Conditions Min Max Unit

Master mode 0 36
fSCK 1/tc(SCK) SPI clock frequency MHz
Slave mode 0 18
tr(SCK) SPI clock rise time Load capacitance: C = 30pF 8 ns
tf(SCK) SPI clock fall time Load capacitance: C = 30pF 8 ns
(2)
tsu(NSS) NSS setup time Slave mode 4tPCLK ns
(2)
th(NSS) NSS hold time Slave mode 73 ns

tw(SCKH) (2) SCK high time Master mode，fPCLK = 36MHz， 50 60 ns

prescale coefficient = 4

tw(SCKL) (2) SCK low time Master mode，fPCLK = 36MHz， 50 60 ns

prescale coefficient = 4
tsu(SI) (2) Data input setup time Slave mode 1 ns
(2)
th(SI) Data input hold time Slave mode 3 ns
Slave mode，fPCLK = 36MHz， 0 55
ta(SO) (2)(3) Data output access time
prescale coefficient = 4
Slave mode，fPCLK = 24MHz 4tPCLK
(2)(4)
tdis(SO) Data output disable time Slave mode 10
(2)(1)
ns
tv(SO) Data output valid time Slave mode (after enable edge) 25
Master mode (after enable
tv(MO) (2)(1) Data output valid time 3
edge)
th(SO) (2) Slave mode (after enable edge) 25
Data output hold time
Master mode (after enable
th(MO) (2) 4
edge)

1. Data based on characterization results. Not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maxi­
mum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi­Z.

www.mm32mcu.com 48/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

NSS input
tsu(NSS) tc(SCK) th(NSS)
CPHA = 0
SCK input

CPOL = 0
tw(SCKH)
CPHA = 0 tw(SCKL)
CPOL = 1

tv(SO) tr(SCK)
tdis(SO)
th(SO)
ta(SO) tf(SCK)
MISO
OUTPUT MSB OUT BIT6 OUT LSB OUT

tsu(SI)
MOSI MSB IN BIT1 IN LSB IN
INPUT

th(SI)

679527

Figure 19. SPI timing diagram­slave mode and CPHA = 0

www.mm32mcu.com 49/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

NSS input
tsu(NSS) tc(SCK) th(NSS)
CPHA =1
SCK input

CPOL = 0
tw(SCKH)
CPHA = 1 tw(SCKL)
CPOL = 1
tv(SO) tr(SCK)
tdis(SO)
ta(SO) th(SO) tf(SCK)

MISO
OUTPUT MSB OUT BIT6 OUT LSB OUT

tsu(SI) th(SI)
MOSI MSB IN BIT1 IN LSB IN
INPUT

429658

Figure 20. SPI timing diagram­slave mode and CPHA = 1(1)

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD .

www.mm32mcu.com 50/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

High
NSS INPUT

t c(SCK)
CPHA = 0
SCK Output

CPOL = 0

CPHA = 0
CPOL = 1

CPHA = 1
SCK Output

CPOL = 0

CPHA = 1
CPOL = 1
t w (SCKH) t r (SCK)
t su(MI ) t w (SCKL) t f (SCK)

MISO INPUT MSB IN BIT6 IN LSB IN

t h(M )

MOSI OUTPUT MSB OUT BIT6 OUT LSB OUT

t v(MO ) t h(MO )

184118

Figure 21. SPI timing diagram­master mode(1)

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD .

5.3.15 12­bit ADC characteristics

Unless otherwise specified, The parameters in the table below are measured using the
ambient temperature, fPCLK2 frequency and VDDA supply voltage in accordance with the
conditions of Table 12.

Table 36. ADC characteristics

Symbol Parameter Conditions Min Type Max Unit

VDDA Supply voltage 2.5 3 5.5 V

ADC clock
fADC 15(1) MHz
frequency
fS (2) Sampling rate 1 MHz
External trigger fADC = 15MHz 823 KHz
fTRIG (2)
frequency 1/17 1/fADC

www.mm32mcu.com 51/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Symbol Parameter Conditions Min Type Max Unit

Conversion voltage
VAIN (2) VSSA VDDA V
range(3)
External sample
RAIN (2) See Formulas 1 and Table 37 kΩ
and hold capactor
Sampling switch
RADC (2) 1 kΩ
resistance
Internal sample and
CADC (2) 10 pF
hold capacitor
fADC = 15MHz 0.1 16 µs
tS (2) Sampling time
1.5 239.5 1/fADC
(2)
tSTAB Stabilization time 1 µs
Total conversion fADC = 15MHz 1 16.9 µs
tconv (2)
time (including 15 ∼ 253 (sampling tS+ ) stepwise
1/fADC
Sampling time) approximation 13.5

1. Guaranteed by comprehensive evaluation, not tested in production.

2. Guaranteed by design, not tested in production.
3. In this series of products, VREF+ is internally connected to DDA ，VREF− is internally con­
nected to SSA .

TS
RAIN < − RADC
fADC × C ADC × (N + 3) × In(2)

The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12­bit resolution) .

Table 37. Maximum RAIN at fADC = 15MHz(1)

TS (cycles) tS (µs) RAIN max (kΩ)

1.5 0.1 0.1

7.5 0.5 4.0
13.5 0.9 7.8
28.5 1.9 17.5
41.5 2.76 25.9
55.5 3.7 34.9
71.5 4.77 45.2
239.5 16.0 153.4

1. Guaranteed by comprehensive evaluation, not tested in production.

www.mm32mcu.com 52/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Table 38. ADC Accuracy ­ Limit Test Conditions(1)(2)

Symbol Parameter Test Conditions Type Max Unit

ET Comprehensive error ±10 ±14

EO Offset error fPCLK2 = 60MHz,fADC = ±4 ±10
EG Gain error 15MHz,RAIN < 10KΩ,VDDA ±6 ±8 LSB
ED Differential linearity error ◦ ±2 ±4
= 3.3V，TA = 25 C
EL Integral linearity error ±4 ±6

1. ADC Accuracy vs Negative Injection Current: Injecting negative current on any of the
standard (non­robust) analog input pins should be avoided as this significantly reduces
the accuracy of the conversion being performed on another analog input. It is recom­
mended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in sub­
subsec 5.3.12 does not affect the ADC accuracy.
2. Guaranteed by comprehensive evaluation, not tested in production.

ET = Total unadjusted error: The maximum deviation between the actual and ideal trans­
mission curves.

EO = Offset error: The deviation between the first actual conversion and the first ideal
conversion.

EG = Gain error: The deviation between the last ideal transition and the last actual transi­
tion.

ED = Differential linearity error: The maximum deviation between the actual step and the
ideal value.

EL = Integral linearity error: The maximum deviation between any actual conversion and
the associated line of the endpoint.

www.mm32mcu.com 53/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Sample and hold

ADC converter
RAIN(1) AINx RADC(1) 12-bit
converter
Cparasi c(2)
VAIN
CADC(1)

Parasi c
capacitance

439454

Figure 22. Typical connection diagram using the ADC

1. See Table 38 for the values of RAIN , RADC and CADC .

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB lay­
out quality) plus the pad capacitance (roughly 7pF) . A high Cparasitic value will down­
grade conversion accuracy. To remedy this, fADC should be reduced.

PCB design recommendations

The power supply must be connected as shown below. The 10 nFcapacitor in the figure
must be a ceramic capacitor (good quality) , and they should be as close as possible to
the MCU chip.

www.mm32mcu.com 54/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

VDDA
VDDA

1 µF // 10 nF

VSSA

澳
326818

Figure 23. Power supply and reference power supply decoupling circuit

5.3.16 Temperature sensor characteristics

Table 39. Temperature sensor characteristics(3)(4)
Symbol Parameter Min Type Max Unit

VSENSE linearity with respect to

◦
TL (1) ±5 C
temperature
Avg_Slope(1) Average slope 4.571 4.801 5.984 mV/◦ C
V25 (1) Voltage at 25◦ C 1.433 1.451 1.467 V
(2)
tstart Setup time 10 µs
ADC sampling time when
TS_temp (2) 10 µs
reading temperature

1. Guaranteed by comprehensive evaluation, not tested in production.

2. Guaranteed by design, not tested in production.
3. The shortest sampling time can be determined by the application through multiple iter­
ations.
4. VDD = 3.3V.

5.3.17 Comparator characteristics

Table 40. Comparator characteristics
Register
Symbol Parameter Min Type Max Unit
configuration
HYST Hysteresis 00 0 mV
HYST Hysteresis 01 15 mV
HYST Hysteresis 10 30 mV

www.mm32mcu.com 55/68
Electrical characteristics
DS_MM32SPIN05x_q_Ver1.23

Register
Symbol Parameter Min Type Max Unit
configuration
HYST Hysteresis 11 90 mV
OFFSET Offset voltage 00 0.091 0.213 0.358 mV
OFFSET Offset voltage 01 3.23 7.51 12.08 mV
OFFSET Offset voltage 10 9.79 15 20.8 mV
OFFSET Offset voltage 11 34.25 47.4 62.22 mV
(1)
DELAY Propagation delay 00 80 nS
(1)
DELAY Propagation delay 01 51 nS
(1)
DELAY Propagation delay 10 26 nS
(1)
DELAY Propagation delay 11 9 nS
(2)
Iq Operating current mean 00 4.5 uA
(2)
Iq Operating current mean 01 4.4 uA
(2)
Iq Operating current mean 10 4.4 uA
(2)
Iq Operating current mean 11 4.4 uA

1. The output flips 50% of the time and the time difference between the input and the flip.
2. Total current consumption, operating current.

www.mm32mcu.com 56/68
Package information
DS_MM32SPIN05x_q_Ver1.23

6 Package information
Package information

6.1 Packaging LQFP48

A3
A2
A

c
A1

R1

L2
R2

s
K
D L
A1

L1
D1

36 25

37 24

b
E1
E

b
b1

48 13
c1
c

PIN 1
IDENTIFICATION 1 12

591233

Figure 24. LQFP48 ­ 48­pin low­profile quad square flat package

1. The drawing is not drawn to scale.

2. Dimensions are in millimeters.

www.mm32mcu.com 57/68
Package information
DS_MM32SPIN05x_q_Ver1.23

Table 41. LQFP48 size description

MM
Label
Min Typ Max
A 1.60
A1 0.05 0.15
A2 1.35 1.40 1.45
A3 0.59 0.64 0.69
b 0.18 0.27
b1 0.17 0.20 0.23
c 0.13 0.18
c1 0.117 0.127 0.137
D 8.80 9.00 9.20
D1 6.90 7.00 7.10
E 8.80 9.00 9.20
E1 6.90 7.00 7.10
e 0.40 0.50 0.60
H 8.14 8.17 8.20
L 0.50 0.70
L1 1.00REF
R1 0.08
R2 0.08 0.20
S 0.20
θ 0◦ C 3.5◦ C 7◦ C
θ1 11◦ C 12◦ C 13◦ C
θ2 11◦ C 12◦ C 13◦ C

www.mm32mcu.com 58/68
Package information
DS_MM32SPIN05x_q_Ver1.23

6.2 LQFP32 Package information

A3
A2
A

c
A1

R1

L2
R2

s
K
L

A1
D
L1
D1

24 17

25 16

b
E1

b
b1

32 9
c1
c

PIN 1
IDENTIFICATION 1 8

989913

Figure 25. LQFP32 ­ 32­pin low­profile quad flat package outline

1. Drawing is not to scale.

2. Dimensions are expressed in millimeters.

Table 42. LQFP32 size description

Millimeters
Symbol
Min Typ Max
A 1.60
A1 0.05 0.15
A2 1.35 1.40 1.45
A3 0.59 0.64 0.69
b 0.33 0.42
b1 0.32 0.35 0.38
c 0.13 0.18
c1 0.117 0.127 0.137

www.mm32mcu.com 59/68
Package information
DS_MM32SPIN05x_q_Ver1.23

Millimeters
Symbol
Min Typ Max
D 8.80 9.00 9.20
D1 6.90 7.00 7.10
E 8.80 9.00 9.20
E1 6.90 7.00 7.10
e 0.70 0.80 0.90
H 8.14 8.17 8.20
L 0.50 0.70
L1 1.00REF
R1 0.08
R2 0.08 0.20
S 0.20
θ 0◦ C 3.5◦ C 7◦ C
θ1 11◦ C 12◦ C 13◦ C
θ2 11◦ C 12◦ C 13◦ C

www.mm32mcu.com 60/68
Package information
DS_MM32SPIN05x_q_Ver1.23

6.3 Packaging QFN32

A2
D

e A1
A3

C2

R c1
e

E2 b
E1 E
H

1
L
32
L
PIN 1 Identifier
D2

978941

Figure 26. QFN32 ­ 32­pin quad flat no­leads package outline

1. The drawing is not drawn to scale.

2. Dimensions are in millimeters.

Table 43. QFN32 size description

MM
Label
Min Typ Max
A 0.7 0.75 0.80
A1 0.00 0.02 0.05
A2 0.50 0.55 0.60
A3 0.20REF
b 0.20 0.25 0.30
D 4.90 5.00 5.10
E 4.90 5.00 5.10
D2 3.40 3.50 3.60
E2 3.40 3.50 3.60

www.mm32mcu.com 61/68
Package information
DS_MM32SPIN05x_q_Ver1.23

MM
Label
Min Typ Max
e 0.5
H 0.30REF
K 0.35REF
L 0.35 0.40 0.45
R 0.09
c1 0.08
c2 0.08
N Number of pins = 32

www.mm32mcu.com 62/68
Package information
DS_MM32SPIN05x_q_Ver1.23

6.4 QFN20 Package information

D
A

e A1
A3

K
b

C2
R c1

E2
E
b H

1
L
20
L
PIN 1 Identifier
D2

926545

Figure 27. QFN20 ­ 20­pin quad flat no­leads package outline

1. Drawing is not to scale.

2. Dimensions are expressed in millimeters.

Table 44. QFN20 size description

Millimeters
Symbol
Min Typ Max
A 0.50 0.55 0.60
A1 0.00 0.02 0.05
A3 0.152REF
b 0.15 0.20 0.25
D 2.90 3.00 3.10
E 2.90 3.00 3.10
D2 1.40 1.50 1.60
E2 1.40 1.50 1.60

www.mm32mcu.com 63/68
Package information
DS_MM32SPIN05x_q_Ver1.23

Millimeters
Symbol
Min Typ Max
e 0.30 0.40 0.50
H 0.35REF
K 0.40REF
L 0.25 0.35 0.45
R 0.075
N Number of pins = 20

www.mm32mcu.com 64/68
Package information
DS_MM32SPIN05x_q_Ver1.23

6.5 TSSOP20 Package information

20 11

E1
c

1 10

PIN1
IDENTIFICATION

SEATING
PLANE
aaa C 0.25 mm
C GAUGE PLANE

A A2

k
b e L
A1
L1

618013

Figure 28. TSSOP20 ­ 20­lead thin shrink small outline package outline

1. Drawing is not to scale.

2. Dimensions are expressed in millimeters.

Table 45. TSSOP20 size description

Millimeters
Symbol
Min Typ Max
A 1.0 1.10
A1 0.05 0.15
A2 0.95
A3 0.39 0.40
b 0.20 0.22 0.24
c 0.10 0.19
c1 0.10 0.15
D 6.40 6.45 6.50

www.mm32mcu.com 65/68
Package information
DS_MM32SPIN05x_q_Ver1.23

Millimeters
Symbol
Min Typ Max
E 6.25 6.40 6.55
E1 4.35 4.40
e 0.55 0.65 0.75
L 0.45 0.60 0.75
L2 0.25BSC
L1 1.0REF
R 0.09
θ1 0◦ C 8◦ C

www.mm32mcu.com 66/68
Ordering information
DS_MM32SPIN05x_q_Ver1.23

7 Ordering information
Ordering information

MM32 SPIN 0 5 N T
Device family
MM32 = Arm-based 32-bit microcontroller

Product type
SPIN = Motor

Sub- family
0 = 0 Series

User code memory size

5 = 32K

Package
P = LQFP
N = QFN
T = TSSOP

Pin count
F = 48 Pins
T = 32 Pins
W = 20 Pins

896243

Figure 29. Ordering information scheme

www.mm32mcu.com 67/68
Revision history
DS_MM32SPIN05x_q_Ver1.23

8 Revision history
Revision history

Table 46. Revision history

Date Version Changes
Update the parameters of operating conditions at
2022/08/24 Rev1.23
power­up/power­down.
Update IO parameters; add annoation 1 in table
2022/06/06 Rev1.22
14; change the NRST figure.
Modify the maximum value of the voltage
2022/01/21 Rev1.21
characteristics.
2022/01/12 Rev1.20 Modify PD and add thermal characteristics.
2021/11/10 Rev1.19 Modify high­speed internal oscillator parameters.
2021/11/10 Rev1.18 Modify temperature characteristics.
2021/09/08 Rev1.17 Modify IO static characteristics.
2020/08/27 Rev1.16 Modify AF parameters in the pin definition.
2020/05/10 Rev1.15 Modify electrical parameters.
2020/04/07 Rev1.14 Modify high­speed internal oscillator parameters.
2020/01/17 Rev1.13 Modify typical current consumption parameters.
2019/07/26 Rev1.12 Modify selection guide.
2019/07/08 Rev1.11 Modify ADC parameters in the selection guide.
2019/05/05 Rev1.10 Modify pin definition.
2019/03/11 Rev1.09 Modify the package parameters.
2019/03/06 Rev1.08 Modify the package parameters.
2019/01/10 Rev1.07 Add the QFN20 package.
2019/01/07 Rev1.06 Modify ADC voltage parameters.
2018/12/14 Rev1.05 Modify ADC descriptions.
2018/11/13 Rev1.04 Modify descriptions.
2018/11/12 Rev1.03 Modify descriptions.
2018/10/11 Rev1.02 Modify electrical parameters.
2018/08/26 Rev1.01 Modify pin definition.
2018/08/04 Rev1.00 Initial release.

www.mm32mcu.com 68/68