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Module 1 Part 2

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14 views30 pages

Module 1 Part 2

Uploaded by

Dheeraj Gm
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 1 Part 2

Hierarchical Modeling Concepts


By
Madhavi Gatty
Asst. Professor
Department of EEE
SJEC
Objectives
● Understand top-down and bottom-up design methodologies for digital
design.
● Explain differences between modules and module instances in Verilog.
● Describe four levels of abstraction to represent the same module.
● Describe components required for the simulation of a digital design.
● Define a stimulus block and a design block and explain two methods
of applying stimulus.
Content
● Design Methodologies
● 4-bit Ripple Carry Counter
● Modules
● Instances
● Components of a Simulation
● Example
● Summary
Design Methodology
● Top-down design methodology

● Bottom-up design methodology


Top Down design methodology
○ Define the final
(top) module
○ Analyze the
components
which are
composed of top
module step by
step
Bottom Up design methodology
○ Design the basic
components
○ Assemble basic
components to
larger design until
the top design is
completed
Ripple Carry Counter
● Ripple Carry
○ Output of current stage is driven from output of previous
stage

● Counter
○ Increments/ Decrement pulses
4-bit Ripple Carry Counter
Negative edge
trigger
1 2 3 4
D Flipflop
Clk Reset Current Next
State State

↓ 1 x 0

↓ 0 0 0

↓ 0 1 1
Truth table of T flipflop
T- Flip Flop
Hierarchy of 4-bit Ripple Carry Counter
Top-down

Bottom-up
Modules
Basic component in Verilog for describing/defining a hardware

module <module_name> (<module_terminal_list>);


…
<module internals>
…
…
endmodule
Example Module
module T_FF (q, clock , reset);
…
… Clock
<functionality of T-flipflop> Black Box q
… Inputs T_FF
reset Outputs
…
endmodule
Levels of functionality
● Behavioral (algorithmic) level

● Dataflow level

● Gate level

● Switch level
Levels of functionality (Types of
Descriptions)
Instances
● Individual object of module
● Module is similar to “function declaration” in C, and instance
likes the concept of “function call”
● Instantiation - Process of creating objects from a module
template
● Instance: The object
Example of Instance
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
Instantiation

T_FF tff0(q[0],clk, reset); Port list


Instance name
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
4 Bit Ripple Carry Counter (Top- Down)
module ripple_carry_counter(q, clk,
reset);
output [3:0] q;
input clk, reset;

T_FF tff0(q[0],clk, reset);


T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
T Flipflop
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q);
endmodule
D Flipflop
module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
always @(posedge reset or negedge clk)
if (reset)
q <= 1'b0;
else
q <= d;
endmodule
Components of a Simulation
Design Under Test (DUT) － Design Block

Test bench － Stimulus Block

Stimulus generation

Output checking
Stimulus Block Instantiates Design
Block
Stimulus and Design Block Instantiated
in a Dummy Top-level module
Example with simulation
● 4 Bit Ripple Carry Counter
● Using Top-down and Bottom-up Methodology
● Simulation
Simulation Block reset = 1'b1;
#15 reset = 1'b0;
module stimulus(); #180 reset = 1'b1;
reg clk,reset; #10 reset = 1'b0;
#20 $finish; //terminate the simulation
wire[3:0] q;
end
ripple_carry_counter r1(q, clk, reset);
// Monitor the outputs
initial
initial
clk = 1'b0; //set clk to 0 Begin
always $monitor($ time, “output q=%d”,q);
#5 clk = ~clk; //toggle clk every 5 time units end
initial begin endmodule
Result
Timing diagram
Summary
● Two kinds of design methodologies are used for digital design:
top-down and bottom-up
● Modules are the basic building blocks in Verilog
● A design block and a stimulus block
● The example of the ripple carry counter
Thank you

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