Module 2

Modules and ports

By
Madhavi
Asst. Professor
Department of EEE, SJEC
Objective
● Identify the components of a Verilog module definition
● Understand how to define the port list for a module and declare it in
Verilog.
● Describe the port connection rules in a module instantiation
● Understand how to connect ports to external signals, by ordered list, and
by name
● Explain hierarchical name referencing of Verilog identifiers
Topics
● Modules
● Ports
● Hierarchical Names
Module Components
1. Component I
a. Module Name
b. Port list
c. Parameters
2. Component II
a. Declaration
b. Data flow, instantiation, behaviour
c. Function or Task
3. Component III
a. endmodule
Component I
MODULE

Module_Name
Parameters
(Optional)

Ports (if any) Port

Declaration (if
any)
Component I
● Module name, port list, port declarations, and optional parameters must come
first in a module definition
Example: module SR_latch(Q, Qbar, Sbar, Rbar);

● Port list and port declarations are present only if the module has any ports to
interact with the external environment.

output Q, Qbar;
input Sbar, Rbar;
Component II

Wire and Reg

Declaration

Behaviour model
Instantiate Lower
Data Flow model always or initial
modules
block

Task and Function

Component II
● Ports to interact with the external environment
● The five components within a module are Wire and Reg
Declaration

○ Variable declarations
Instantiate
Data Flow Behaviour
○ Dataflow statements (assign) Lower
modules
model model

○ Instantiation of lower modules (gate level)

Task and
○ Behavioral blocks(always or initial ) Function

○ Tasks or functions (sub program)

● These components can be in any order and at any
place in the module definition.
Component III
endmodule:
● Ending the module with the keyword: endmodule
● Always comes last in a module definition.
A complete Verilog Module
module <module_name> (<module_terminal_list>);
<I/O declaration>
<parameter declaration>
…
<module internals>
…
…
endmodule
Example - SR latch (gate level description)
 Example - SR latch Sbar
Q

Case-1: Sbar=Rbar=1 (S=R=0) –

● If Q = 0, Q and Rbar inputs for Qbar
2nd NAND gate are 0 and 1 Rbar
respectively.
Sbar
Q
● If Q = 1, Q and Rbar inputs
for 2nd NAND gate are
both 1.

Rbar Qbar
 Sbar
Q
Example - SR latch
Case-2: Sbar=0, Rbar=1 (S=1, R=0) –
● As Sbar=0, the output of 1st NAND gate,
Q = 1(SET state). In 2nd NAND gate, as
Q and Rbar inputs are 1, Qbar=0. Rbar Qbar

Sbar Nextstate
state: 1: 1
Next
00 Q
● As Sbar=0, the output of 1st NAND 1
gate, Q = 1. In 2nd NAND gate, as Q
and Rbar inputs are 1, Qbar=0

1 1 1
Rbar Qbar
Next state : 0
 Next state : 0
1
Example - SR latch Sbar
Q
Case-3: Sbar= 1, Rbar= 0 (S=0, R=1) –
● As Rbar=0, the output of 2nd NAND gate,
Qbar= 1. In 1st NAND gate, as Qbar and 1 0
Sbar inputs are 1, Q=0(RESET state). 0
Rbar Qbar
Next state : 1

● As Sbar=1, the output of 1st NAND Sbar

gate, Q = 0. In 2nd NAND gate, as Q
Qbar and Rbar inputs are 0, Qbar=1.

Qbar
Rbar Qbar
Components of SR Latch
module SR_latch(Q, Qbar, Sbar, Rbar);

output Q, Qbar;
input Sbar, Rbar;
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);

endmodule
Verilog SR Latch
module SR_latch(Q, Qbar, Sbar, Rbar);

output Q, Qbar;
input Sbar, Rbar;
nand n1(Q, Sbar, Qbar);
Module name and port nand n2(Qbar, Rbar, Q);
list of
SR_latch module endmodule
Verilog SR Latch
module SR_latch(Q, Qbar, Sbar, Rbar);

output Q, Qbar;
input Sbar, Rbar;
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
Port
endmodule
declarations
Verilog SR Latch
Wires are connected in a
module SR_latch(Q, Qbar, Sbar, Rbar);
cross-coupled fashion.
output Q, Qbar;
input Sbar, Rbar;
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
Instan
tiate endmodule
lower
-leve
modu l
les
SR Latch stimulus module
module Top;
wire q, qbar;
reg set, reset;
SR_latch m1(q, qbar, ~set, ~reset);
initial
begin
$monitor($time, " set = %b, reset= %b, q= %b\n",set,reset,q);
set = 0; reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 set = 1;
end
endmodule
SR Latch stimulus module
module Top;
wire q, qbar;
reg set, reset;
SR_latch m1(q, qbar, ~set, ~reset);
initial
begin
Declarations $monitor($time, " set = %b,
Of variables reset= %b, q= %b\n",set,reset,q);
set = 0; reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 set = 1;
end
endmodule
SR Latch stimulus module
module Top;
wire q, qbar;
reg set, reset;

SR_latch m1(q, qbar, ~set, ~reset);

Instan initial
tiate begin
lower
-leve $monitor($time, " set = %b, reset=
modu l %b, q= %b\n",set,reset,q);
les - S
R set = 0; reset = 0;
Latch #5 reset = 1;
#5 reset = 0;
#5 set = 1;
end
endmodule
SR Latch stimulus module
module Top;
wire q, qbar;
reg set, reset;
SR_latch m1(q, qbar, ~set, ~reset);

initial
begin
$monitor($time, " set = %b, reset=
Beha %b, q= %b\n",set,reset,q);
viora
l set = 0; reset = 0;
block #5 reset = 1;
#5 reset = 0;
#5 set = 1;
end
endmodule
Ports
● A Verilog HDL module consist of two major parts:
○ The interface
○ The internal (body)
● Ports provide interface to communicate with external environment.
● The internals of the module are not visible to the environment.
● The environment can interact with the module only through its ports.
● Ports are also referred to as terminals.
List of Ports
● “No” port declaration is required if do
not need to communicate with other
module, such as Top module

● Module fulladd4 has five ports

while top has no port.
● a, b, and c_in are input ports
and sum and c_out are output
ports.
List of Ports
Example:

❖ module fulladd4(sum, c_out, a, b, c_in); //Module with a list of ports

❖ module Top; // No list of ports, top-level module in simulation
Port Declaration

Verilog Keyword Type of Port

input Input port

output Output port
inout Bidirectional port
 Port Declaration
Example:
module fulladd4(sum, c_out, a, b, c_in);

output [3:0] sum;

Port output c_out;
declaration input [3:0] a, b;
input c_in;
...
<module internals>
...
endmodule
Port Declaration
Example:
module DFF(q, d, clk, reset);
● Default data type of I/O
output q;
ports is “wire” reg q;
● Input or inout ports are input d, clk, reset;
normally declared as wires. ...
● If output ports hold their ...
value, they must be endmodule
declared as reg.
Port Declaration
ANSI C style syntax module fulladd4(output reg [3:0]
● This syntax avoids the sum, output reg c_out, input [3:0]
duplication of naming the a, b, input c_in);
ports in both the module ...
definition statement and the <module internals>
module port list definitions. ...
● If a port is declared but no endmodule
data type is specified, then,
under specific circumstances,
the signal will default to a wire
data type.
Port Connection Rules
Port Connection Rules
■ Input Port
❑ Internal view－ viewed as “a wire/net”
❑ External view－ can be connected to a
reg or wire

■ Output Port
❑ Internal view－declared as a reg or
wire
❑ External view－only be connected to a
wire
Port Connection Rules

■ Inout Port
❑ Viewed as a wire/net regardless of
internal or external module
Port Connection Rules
❏ Width matching: Mismatch of internal and external port
connections
❏ Simulation will issue a warning for this condition

❏ Unconnected ports: Floating of port connection

❏ Ex: Fulladd4 fa0(sum, , a, b, c_in); // c_out floating
Connecting Ports to External Signals
Connecting by ordered list:

● The signals to be connected must have the same order as in the port list.

● All unconnected ports are left blank

Connecting Ports to External Signals
Connecting by ordered list:
module Top;
module fulladd4(sum, c_out, a, b,
reg [3:0]A,B;
c_in); reg C_IN;
output[3:0] sum; wire [3:0] SUM;
output c_cout; wire C_OUT;
input [3:0] a, b;
input c_in; fulladd4 fa_ordered(SUM, C_OUT, A, B,
... C_IN);
<module internals> ...
... <stimulus>
endmodule ...
endmodule
Connecting Ports to External Signals
Connecting ports by name:

● Ports to be connected to external signals are specified by listing their names.

● The order of the ports is not important

● Unconnected ports can be dropped from the port list.

Connecting Ports to External Signals
Connecting ports by name: module Top;
reg [3:0]A,B;
module fulladd4(sum, c_out, a, b,
reg C_IN;
c_in);
wire [3:0] SUM;
output[3:0] sum; wire C_OUT;
output c_cout;
input [3:0] a, b; Fulladd4 fa_byname(.c_out(C_OUT),
input c_in; .sum(SUM), .b(B), .c_in(C_IN), .a(A),);
... ...
<module internals> <stimulus>
... ...
endmodule endmodule
Hierarchical Names
● Hierarchical name referencing allows us to denote every identifier in
the design hierarchy with a unique name.
● A hierarchical name is a list of identifiers separated by dots (".") for
each level of hierarchy.
● The top-level module - Root module
● To assign a unique name to an identifier, start from the top-level
module and trace the path along the design hierarchy to the desired
identifier.
Hierarchical Names
Hierarchical Names
Stimulus (Root)
stimulus stimulus.q
m1(SR_latch)
stimulus.qbar stimulus.set
q, qbar,
set, reset stimulus.reset stimulus.m1
n1(nand n2(nand
) ) stimulus.m1.Q stimulus.m1.Qbar

Q, Qbar, S, stimulus.m1.S stimulus.m1.R

R
stimulus.m1.n1 stimulus.m1.n2
Thank you