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Architecture

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22 views6 pages

Architecture

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darlachantisaideepthi450
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EMBEDDED SYSTEMS

INTERNSHIP MINI PROJECT

ARCHITECTURE OF 8051
MICROCONTROLLER

Report submitted by

M.Soma Sundari

1
MICROCONTROLLER EVOLUTION

First, microcontrollers were developed in the mid-1970s. These were basically


calculator- based processors with small ROM program memories, very limited RAM
data memories and a handful of input/output ports. As silicon technology
developed, more powerful, 8-bit microcontrollers were produced. In addition to
their improved instruction sets, these microcontrollers included on-chip
counter/timers, interrupt facilities, and improved I/O handling. On-chip memory
capacity was still small and was not adequate for many applications. One of the
most significant developments at this time was the availability of on-chip ultraviolet
erasable EPROM memory. This simplified the product development time
considerably and for the first time, also allowed the use of microcontrollers in
lowvolume applications. The 8051 family was introduced in the early 1980s by Intel.
Since its introduction, the 8051 has been one of the most popular microcontrollers
and has been second- sourced by many manufacturers. The 8051 currently has many
different versions and some types include on-chip analogue-to-digital converters, a
considerably large size of program and data memories.

INTRODUCTION TO 8051:
The Intel MCS-51 (commonly referred to as 8051) is a Harvard architecture, single
chip microcontroller (μC) series which was developed by Intel in 1980 for use in
embedded systems. The 8051 architecture provides many functions (CPU, RAM,
ROM, I/O, interrupt logic, timer,etc.) in a single package Features of 8051: 8-bit

ALU, Accumulator, 8-bit Registers and 8-bit data bus; hence it is

 an 8-bit microcontroller 16-bit program counter


 8-bit Processor Status Word(PSW)
 8-bit Stack Pointer
 Internal RAM of128bytes
 On chip ROM is4KB
 Special Function Registers (SFRs) of 128bytes
 32 I/O pins arranged as four 8-bit ports (P0 -P3)
 Two 16-bit timer/counters : T0 andT1

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 Two external and three internal vectored interrupts Full duplex UART
(serialport)

BLOCK DIAGRAM OF 8051

INTERNAL ARCHITECTURE OF 8051 MICROCONTROLLER

3
The Internal architecture is shown in Figure 4.1.4 and the various Registers and units
are described below.

Accumulator (Acc):

•Operand register

• Implicit or specified in the instruction

•Has an address in on chip

SFR bank B Register: Used to store one of the operands for multiplication and
division, otherwise, scratch pad considered as a SFR.

Stack Pointer (SP): 8 bit wide register. Incremented before data is stored on to the
stack using PUSH or CALL instructions. Stack defined anywhere on the 128 byte
RAM. Data Pointer (DPTR): 16 bit register contains DPH and DPL Pointer to
external RAM address. DPH and DPL allotted separate addresses in SFR bank Port 0
To 3.

Latches & Drivers: Each I/O port allotted a latch and a driver Latches allotted
address in SFR. User can communicate via these ports P0, P1, P2, and P3.

Serial Data Buffer: Internally had TWO independent registers, TRANSMIT buffer
(parallel in serial out – PISO) and RECEIVE buffer (serial in parallel out –SIPO)
identified by SBUF and allotted an address in SFR.

Program Status Word (PSW): Set of flags contains status information as detailed .

Timer Registers: for Timer0 (16 bit register – TL0 & TH0) and for Timer1 (16 bit
register – TL1 & TH1) four addresses allotted in SFR. Control Registers: Control
registers are IP, IE, TMOD, TCON, SCON, and PCON. These registers contain
control and status information for interrupts, timers/counters and serial port.
Allotted separate address in SFR.

Timing and Control Unit: The timing and control unit

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necessary timing and control signals for internal circuit and external system bus.

Oscillator: generates basic timing clock signal using crystal oscillator. Instruction

Register: Decodes the opcode and gives information to timing and control unit.

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EPROM & program address Register: provide on chip EPROM and mechanism to
address it. All versions don’t have EPROM. Ram & Ram Address Register: provide
internal 128 bytes RAM and a mechanism to address internally ALU: Performs 8 bit
arithmetic and logical operations over the operands held by TEMP1 and TEMP 2.User
cannot access temporary registers. SFR Register Bank: set of special function registers
address range: 80 H to FF H. Interrupt, serial port and timer units control and perform
specific functions under the control of timing and control unit.

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