2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems

(VLSID)
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID) | 979-8-3503-4678-7/23/$31.00 ©2023 IEEE | DOI: 10.1109/VLSID57277.2023.00039

An Energy-Efficient and Robust 10T SRAM based

In-Memory Computing Architecture
Noopur Srivastava∗ , Anil Kumar Rajput∗ , Manisha Pattanaik∗ , Gaurav Kaushal∗
∗ VLSI
Design Lab, ABV-IIITM, Gwalior
{noopurs,anil,manishapattanaik,kaushalg}@iiitm.ac.in

Abstract—In-Memory Computing (IMC) is emerging as a new II. BACKGROUND AND R ELATED WORK
paradigm to address the von Neumann bottleneck (VNB) in data- The various IMC and Near Memory Computation (NMC)
intensive applications. This research proposes a 10T SRAM-based architectures have been reported in the [5]–[7]. In [4] ALU
IMC architecture that is both robustand energy-efficient. The
write margin and read margin of the proposed 10T SRAM are unit has been kept near the storage unit to design an NMC
both increased by 40% and 2.5%, respectively, over the 9T SRAM architecture with wider bandwidth for minimizing energy con-
cell. The proposed 10T SRAM has write energy and leakage sumption. Most of the design for the IMC-based implemented
power reduction of 89% and 96.6%, respectively while maintain- system usually uses 6T SRAM cells [5], [6]. In work, [5], an
ing a similar read enery as compared to 9T SRAM. Additionally, addressable content memory and Boolean logic operation have
a 4 Kb SRAM array based on 10T SRAM is implemented in 180-
nm SCL technology to analyze the suggested IMC architecture. been presented by using a 6T SRAM cell. The classification
At 1.8 V, 60 MHz, the suggested IMC architecture achieves energy of machine learning in IMC has been implemented using a
efficiency of 0.43 TOPS/W for 1-bit logic and 0.41TOPS/W for convolutions (conv) 6T SRAM memory array in [7]. The local
1-bit addition. The area efficiency of 65.2% for a 136 32 array grouped SRAM has been presented for arithmetic and logic
is achieved. operation in the IMC system [8]. The noise margin degrades in
Index Terms—SRAM, Von-Neumann architecture (VNA), In-
Memory Computing (IMC), energy-efficiency
convolution (conv) 6T SRAM cell because it contains a single
path for both read-write operations and is further engaged to
create read disturbance during the IMC system.
I. I NTRODUCTION The 8T SRAM has been implemented for performing the
The conventional Von-Neumann-based architecture (VNA) logic operation for IMC based system [9]. The 8T SRAM has
[1] contains a separate processing unit and memory unit as been designed using a different path for both read and write
shown in fig. 1(a). The separate unit for processing and storage operation, which improves the read noise margin. The author
consumes a large amount of energy for transferring data in [10] has proposed the 8T SRAM for memory computing
between these two different units. For the prevalence of big with Boolean logic operation. The ternary address content
data applications like artificial intelligence and neuromorphic memory has been presented in [11] with left, and right shift
computing, a large amount of energy is required and a large operations as well as the storage function with a configurable
amount of latency is also generated for transferring the data 8T SRAM cell.
between the processing unit and memory unit in VNA [2]. Re- The author in [10] presented the 9T SRAM cell for the
cent computing systems used In-Memory Computation (IMC) computation in memory which performed the logic operation.
[3], [4] based architecture in which data is processed inside the The author in [12] has been implemented the 9T SRAM cell
storage unit, as shown in fig. 1(b). The IMC-based architecture for the logic operation of computation in memory. The author
contains an integrated computational unit (arithmetic logic in [13] has been presented the convolution (conv) SRAM for
unit) along with storage unit (memory) which required less a machine learning-based dot product system. Although the
energy consumption for the computing system. read static margin is improved via a different path of read and
write operating modes in the 8T, 9T, and 10T SRAM cells but
the read static and write static margins must still beincreased
in addition to the energy efficiency of the SRAM cell.
In this work, an energy-efficient and robust 10T SRAM cell
is proposes. Further, IMC architecture based on proposed 10T
is implemented to perform in memory logic operation and near
memory arithmetic operations.
The paperis organized as follows: Section II examines
the context and related work. Section III concentrates on
a summary of the proposed 10T SRAM bit-cell for IMC
architecture. The IMC-based architecture’s design specifica-
Figure 1: (a) Von-Neumann architecture (b) IMC architecture. tions are presented in Section IV. An overview of the various

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DOI 10.1109/VLSID57277.2023.00039
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operating modes in the IMC architecture is presented in The proposed 10T SRAM cells is precisely like the conv 10T
Section V. The proposed 10T SRAM cell based IMC system’s SRAM cells [13], with the exception that just one transistor
simulation results are covered in Section VI, and the final is utilised to write the data and a second transistor, M5, is
section concludes the paper. added for lowering the power consumption due to off state for
the write ”1” operation. Additionally, the open Vgnd signal
is utilized, and is used for reducing leakage current during
write operations. In addition to Gc1 being connected to VDD
and Vgnd being connected to GND, the hold operation is
comparable to that of the conv10T SRAM cell

(a) (b)

Figure 2: a) Proposed 10T SRAM bit-cell schematic (a) Proposed

10T SRAM bit-cell layout
III. P ROPOSED 10T SRAM FOR IMC A RCHITECTURE
For IMC architecture, the 10T SRAM cell, which has
ten transistors, is proposed. Fig. 2(a) depicts the proposed
Figure 3: Proposed 10T SRAM Cell Operating condition in a) Read
10T SRAM cell’s schematic. Two extra transistors, M7 and
(b) Write.
M9, are included in the proposed SRAM cell’s schematic.
These transistors help to create a virtual ground during the
hold condition and separate the core from the ground, which
enhances WSNM and lowers leakage power. Fig. 2(b) shows
the logical layout of the proposed 10T SRAM cell, which has
an area of 70.47 μm2 (10.44 μm × 6.75 μm). If the layout
of proposed 10T SRAM is designed in thin cell layout then
the area of of 65.42 μm2 (11.28 μm × 5.8 μm).

Table I: Operation Table of the proposed 10T SRAM bit Cell

Memory
RWL RWLB WWL RBL RBLB WLB Gc1 Vgnd
Operation Figure 4: Proposed 10T SRAM array, as well as the storage
Read VDD VDD GND Pre Pre VDD VDD GND node of the row and column half select cells during the write
Write
”1” operation
GND GND VDD VDD VDD GND VDD VDD
0

Write
GND GND VDD VDD VDD VDD GND VDD
1

Hold GND GND GND VDD GND VDD VDD GND

1) Read/Write/Hold Operation: All the signals that are

used by proposed 10T SRAM’s signals for writing, reading,
and holding operations are illustrated in Table I. The proposed
10T SRAM cell’s read operation is comparable to that of the
existing conv10T SRAM cell. The proposed 10T SRAM’s Figure 5: Transient timing analysis for the selected cell and
read operation is carriedout withtransistors M7M8 for RWL for the column half-selected cell during write ”1” operation
and M9M10 for RWLB. The sensory amplifier senses RBL 2) Half-select issue: A write operation can flip data in
andRBLBvalues. The proposed SRAM’s schematic is depicted a half-selected column or row cell. In Fig. 4, four cells are
in fig.3(a) during a read operation.The proposed SRAM’s presented for the write ’1’ operation: the selected cell, the
schematic is depicted in fig. 3(b) during a write operation. row half-selected cell, the column half-selected cell, and the

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 (a) (b)

Figure 6: a) Block diagram of the proposed IMC architecture based on a 10T SRAM (b)Proposed IMC architecture layout

unselected cell. Half-select difficulties in columns with half-

selected cells during write operations are analysed with Monte-
Carlo (MC)simulations. Fig. 5 indicates that, for the proposed
IMC-based design, when both cells are off-Gc1, the write ”1”
operation is effective in the selected cell without the half select
issue at column half-selected cells. Here Q1, QB1 represents
the data in the selected cell and Q2, QB2 represents the data
in the column half selected cell.
IV. I N -M EMORY C OMPUTATION A RCHITECTURE
The proposed 136-word × 32-bit memory array consist of
10T SRAM cell, a pre-charge circuit for charging the RBL
and RBLB, an SRAM cell array, a decoder for accessing the
row and column of the memory array, and a sensing circuit
to sense the RBL and RBLB. The PMOS transistor is used in
the pre-charge circuit and the differential-based sense amplifier
[14] is used as a sensing element, which is shown in Figure
6(a). A total of eight sense amplifiers are used for the 32
columns by using the 8x1 muxing. Two sense amplifiers are
used for a group of 8 columns, one is for RBL and the other is Figure 7: In-memory Boolean and Near memory arithmetic
for RBLB. Write, and read word lines are connected with the operations with multiple rows activated
row decoder, and Gc1, Vgnd, and write driver are connected simultaneously. The RBL and RBLB are discharged or remain
through the column decoder. Fig. 6(b) shows the layout of at pre charged level according to the stored operand values,
IMC based system which has an area of 0.77mm2 (1216.4μm if operand are 00 then RBL remains at precharged level and
× 632.54μm). RBLB start discharging as shows in fig 8(b). If operand are
V. O PERATING M ODE OF IMC ARCHITECRUE 01/10 then both RBL and RBLB start discharging as shown in
fig.8(c). If operand are 11 then RBLB remain at precharged
A. Logic-in memory Operations level and RBL start discharging as shows in fig 8(d). The
Fig. 7 shows the simulation setup for performing in memory SA1 is used to senses the difference between RBL and Vref
boolean logic operation on two different operand store in row 0 voltage and produce the OR and NOR logic operations results.
and row 1, respectively. For performing logic in memory com- The SA2 is used to senses the difference between RBLB
puting operations (OR, NOR, AND, NAND) in the proposed and Vref voltage and produce the AND and NAND logic
architecture, intially RBL and RBL are pre charged to VDD, operations results. The XOR operation is performed by using
after that two read word line RWL[0], RWL[1] are activated extra circuitry of NOR.

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For SA1, the positive terminal is connected to the RBL, and
the negative terminal is connected to the reference voltage
(Vref). For the second SA2, the RBLB is used on the SA’s
negative end, while Vref is used on the SA’s positive end. The
Vref signal generator is used to produce a 1.65 V reference
voltage (fig. 7) [15].

Figure 10: Arithmetic addition waveform for different condi-

tion

Figure 8: IMC waveform for (a) Read 0 (b) logic 00 (b) logic
01/10 (b) logic 11

Figure 11: Test chip die photo and power/area breakdown.

VI. S IMULATION R ESULTS AND D ISCUSSION

Figure 9: Monte Carlo 1K simulation with null operands (A=0, Here, the proposed 10T SRAM cell is compared to the
B=0) in the worst-case process corner conv10T SRAM and the 9T SRAM bit cell in terms of cost,
energy, stability, and quality. Using 180nm CMOS technology
The 1K Monte-Carlo Simulation with zero operands (A=0, at room temperature (i.e. 27 C), the proposed IMC architecture
B=0) is depicted in fig. 9. No logical operation is discovered is implemented in the cadence virtuoso tool. The energy used
to have failed even at the worst possible process corner [15]. per bit during Boolean logic-based computation (IMBC) is
compared to that of IMBCs described in [5], [8], [10], [13].
B. Arithmetic Operation Fig. 11 shows the fabricated chip, area, and power breakdown
of IMC-based architecture. The size of 5×5mm2 is used to
Fig. 7 illustrates in memory boolean logic operations fabricate the chip. The area breakdown, power breakdown,
through the 10T SRAM based IMC architecture. To enable and performance parameters of the fabricated chip are shown
addition, a carry ripple adder nearthe array using two nor in fig. 11.
gates and one xor gate is implemented. Each peripheral circuit
at column receives a carry-in from the peripheral circuit of A. Stability analysis
previous column, and provides a carry-out to the peripheral The proposed 10T SRAM is analyzed for stability using the
circuit of next column. Fig. 10 shows the transient simulation RSNM, WSNM, and HSNM criteria with respect to the 9T,
of 1 bit addition at different operating condition. Subtraction conv 10TSRAM bit cell.
operation can be performed using two’s complement method 1) Hold Static Noise Margin (HSNM): The HSNM is
[8]. The multiplication operation can be performed by using evaluated using the butterfly curve method. The HSNM of
the shift and add algorithm. the proposed 10T cell is increased by 2.5% due to Vgnd with

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 Table II: Comparison of various SRAM with proposed SRAM
cell

SRAM Proposed 10T conv 10T [13] 9T [10]

RSNM (mV) 655.1 635.86 635.82

WSNM (mV) 957 683.2 683.1438

HSNM (mV) 655.1 635.84 635.8291

RAT (ns) 1.609 1.609 1.609

WAT (ps) 82 37.03 34.77

Figure 12: Distribution plot for RSNM/HSNM Read Energy (fJ) 190.5 190.56 192.5

Write Energy (fJ) 0.245 0.118 2.34

respect to both conv 10T SRAM and 9T SRAM bit cells. Fig.
12 shows the distribution plot for HSNM which is similar to Area (Normalized) 1.12 1.12 1
the RSNM due to decoupled circuitry.
2) Read Static Noise Margin (RSNM): The RSNM is also Leakage Power(uW) 2.1065 2.1065 68.09
evaluated using the butterfly curve method. The proposed Quality Factor 36.53 30.24 1
10T SRAM cell is used in the read decoupled path which is
responsible for a disturbance-free read operation. The RSNM
of the proposed 10T bit cell is increased by 2.5% due to Gc1 1) Read access time (RAT) and Write access time(WAT):
with respect to conv 10T SRAM and 9T SRAM. Fig. 12 shows The proposed 10T SRAM bit cell has a read access time (RAT)
the distribution plot for RSNM which has a mean value of of the time it takes to transition from the read word line at 50%
655.1 mV. supply voltage to the RBL or RBLB at 10% supply voltage.
A comparison of the read access times of the proposed 10T
SRAM cell with those of other SRAM bit cells is provided in
Table II.
The write access time (WAT) of the proposed 10T SRAM
is defined as the interval between the negative edge of the
write word line at 50% VDD and node ’Q’ or ’QB’ at 10%
VDD (discharging). When compared to the other SRAM cells
in Table II, the proposed 10T SRAM cell has a longer write
access time.
2) Read and Write Energy: Table II compares the read and
write energyof the proposed 10T SRAM bit cell to those of
the 9T SRAM and the conv 10T SRAM bit cell. Table II
demonstrates that the proposed cell reduces read energy by
Figure 13: Distribution plot for WSNM (0 and 1) 1% compared to 9T SRAM bit cell. The proposed cell has an
89 %lower write energy than 9T SRAM bit cell.
3) Write Static Noise Margin (WSNM): The WSNM is
3) Area: The proposed work’s 10T SRAM cell layout is
calculated using dynamic write margin and Write Trip Voltage
designed using the Cadence Virtuoso layout editor and the
(WTV) to depict SRAM’s dynamic behavior during a write
design guidelines specified by the 180nm SCLPDK. Signal-
operation. The WTV is the difference between VDD and
ing in the proposed 10T SRAM, as shown in Fig. 3(b), is
WWL at which Q and QB flip. By adding an off transistor
accomplished via two metal layers and one poly silicon layer.
Gc1, the proposed SRAM is able to increase the WSNM of
Table II compares the proposed SRAM’s area to that of 9T,
its write ”1” operation. This means that the proposed 10T bit
conv10T SRAM bit cells. Area-wise, the proposed SRAM bit
cell has a WSNM that is 40% higher than the WSNM of a 9T
cell is about equivalent to a conv 10T SRAM bit cell, however
SRAM bit cell. The mean value of WSNM is 957 mV, and its
it is 12% larger than a 9T due to an additional transistor.
distribution plot is shown in fig. 13.
4) Power Consumption: Most of the undesirable leakage
B. Cost Compression power in an SRAM is produced by the bit cell itself during the
hold operation. The proposed SRAM employs an additional
The proposed 10T SRAM is compared to the 9T, conv
terminal, Vgnd, to cut down on leakage power in the hold
10T SRAM bit cell in terms of RAT, WAT, read energy, and
state. Table II compares the leakage of the proposed 10T
write energy, all of which contribute to the overall cost of the
SRAM to that of the 9T and the conv10T SRAM bit cell.
memory.
The results reveal that the proposed 10T SRAM significantly

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 Table III: Comparison of various IMC based architecture architecture is performed for arithmetic and logic operation.
This
The proposed IMC architecture reduces the normalize energy
TCAC18 [10] JSSC19 [13] JSSC20 [5] TC20 [8]
Work
for Boolean logic by 3.09%, 6% with respect to recently
Local reported 9T SRAM and 8T SRAM cell, respectively. A 0.41
SRAM 9T 10T 8T 10T
grouped 6T TOPS energy consumption is found for arithmetic operation
Process 45nm 65nm 28nm 28nm 180nm in the proposed IMC architecture. The proposed 10T SRAM
Array Size NA 256x64 128x256 32x256 136x32 bit-cell can be significant option for In-Memory Computing.
Supply 1.1 1 1 1.1 1.8

Logic Logic Logic ACKNOWLEDGEMENT

Operation Logic Logic
Arithmetic Arithmetic Arithmetic
The chip fabrication and CAD tools are supported by
Column Mux NA NA 8x1 NA 8x1
SMDP-C2SD project, MeitY Government of India.
Average
17.23 NA 7.5 7.73 291.5
Logic Energy(fJ/bit) R EFERENCES
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