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MODULE-4

Exception and Interrupt Handling

Introduction:
Exceptions and interrupts are unexpected events which will disrupt the
normal flow of execution of instruction. An exception is an unexpected
event from within the processor. Interrupt is an unexpected event from
outside the process. Whenever an exception or interrupt occurs, the
hardware starts executing the code that performs an action in response to
the exception.
The following types of action can cause an exception:
⚫ Reset is called by the processor when power is applied. This
instruction branches to the initialization code.
⚫ Undefined instruction is used when the processor cannot decode an
instruction.
⚫ Software interrupt is called when we execute a SWI instruction. The
SWI instruction is frequently used as the mechanism to invoke an
operating system routine.
⚫ Prefetch abort occurs when the processor attempts to fetch an
instruction from an address without the correct access permissions.
The actual abort occurs in the decode stage.
⚫ Data abort is similar to a prefetch abort but is raised when an
instruction attempts to access data memory without the correct access
permissions.
⚫ Interrupt request is used by external hardware to interrupt the normal
execution flow of the processor. It can only be raised if IRQs are not
masked in the cpsr.

4.1 Exception handling

An exception is any condition that needs to halt the normal sequential
execution of instructions.
Example for exceptions are: ARM core reset, instruction fetch or
memory access failure, an undefined instruction fetch, execution of
software interrupt instruction, when an external interrupt has been raise.

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Exception handling is the method of processing these exceptions.Most

exceptions have an associated software exception handler. Software
exception handler are software routine that executes when an exception
occurs. The handler first determines the cause of the exception and then
services the exception. Servicing takes place either within the handler or
by branching to a specific service routine.
The Reset exception is a special case of exception and it is used to
initialize an embedded system.

4.1.1 ARM Processor Exceptions and Modes

Whenever an exception occurs, the core enter a specific mode. The ARM
processor modes can be entered manually by changing the cpsr.
When an exception occurs the ARM processor always switches to ARM
state. Figure 4.1 shows an exceptions and associated modes.

Figure 4.1 Exceptions and associated modes.

The user and system mode are the only two modes that are not entered
by an exception.
When an exception causes a mode change, the core automatically
■ saves the cpsr to the spsr of the exception mode
■ saves the pc to the lr of the exception mode
■ sets the cpsr to the exception mode
■ sets pc to the address of the exception handler

4.1.2 Vector Table

The vector table is a table of addresses that the ARM core branches to
when an exception is raised. These addresses contain branch instructions
The memory map address 0x00000000 is reserved for the vector table, a
set of 32-bit words. On some processors the vector table can be optionally
located at a higher address in memory (starting at the offset 0xffff0000).

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Table 4.2 Vector table and processor modes

The branch instruction can be any of the following forms:

B <address>—This branch instruction provides a branch relative from
the pc.
LDR pc, [pc, #offset]—This load register instruction loads the handler
address from memory to the pc. This form gives slight delay in branching
as it need the extra memory access. But using this form we can branch to
any address in memory.
LDR pc, [pc, #-0xff0]—This load register instruction loads a specific
interrupt service routine address from address 0xfffff030 to the pc. This
specific instruction is used when a vector interrupt controller is present
(VIC PL190).
MOV pc, #immediate—This move instruction copies an immediate value
into the pc. The address must be an 8-bit immediate rotated right by an
even number of bits.

Figure 4.2 Example vector table.

4.1.3 Exception Priorities

Exceptions can occur simultaneously, so the processor has to adopt a
priority mechanism. Each exception is dealt with according to the priority
level set out in Table.
Table shows the various exceptions that occur on the ARM processor and
their associated priority level.

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Table 4.3 Exception priority levels.

◆ The Reset exception is the highest priority and it occurs when

power is applied to the processor. The reset handler initializes the
system, and setting up memory and caches. The reset handler must
also set up the stack pointers for all processor modes. When a
reset occurs, it takes precedence over all other exceptions.
◆ Data Abort exceptions occur when the memory controller or
MMU indicates that an invalid memory address has been accessed or
when the current code attempts to read or write to memory without the
correct access permissions. When Data Abort occurs, it takes
precedence over all other exceptions except Reset exception.
◆ A Fast Interrupt Request (FIQ) exception occurs when an external
peripheral sets the FIQ pin to nFIQ. An FIQ exception is the highest
priority interrupt. The core disables both IRQ and FIQ exceptions on
entry into the FIQ handler. Thus, no external source can interrupt the
processor unless the IRQ and/or FIQ exceptions are reenabled by
software.
◆ An Interrupt Request (IRQ) exception occurs when an external
peripheral sets the IRQ pin to nIRQ. An IRQ exception is the second-
highest priority interrupt. The IRQ handler will be entered if neither
an FIQ exception nor Data Abort exception occurs. On entry to the
IRQ handler, the IRQ exceptions are disabled and should remain
disabled until the current interrupt source has been cleared.
◆ A Prefetch Abort exception occurs when an attempt to fetch an
instruction results in a memory fault. This exception is raised when
the instruction is in the execute stage of the pipeline and if none of the
higher exceptions have been raised. After enter to the handler, IRQ

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exceptions will be disabled, but the FIQ exceptions will remain

unchanged. If FIQ is enabled and an FIQ exception occurs, it can be
taken while servicing the Prefetch Abort.
◆ A Software Interrupt (SWI) exception occurs when the SWI
instruction is executed and none of the other higher-priority
exceptions have been flagged. On entry to the handler, the cpsr will be
set to supervisor mode. If the system uses nested SWI calls, the link
register r14 and spsr must be stored away before branching to the
nested SWI to avoid possible corruption of the link register and the
spsr.
◆ An Undefined Instruction exception occurs when an instruction not in
the ARM or Thumb instruction set reaches the execute stage of the
pipeline and none of the other exceptions have been flagged. The ARM
processor “asks” the coprocessors if they can handle this as a
coprocessor instruction. Since coprocessors follow the pipeline,
instruction identification can take place in the execute stage of the core.

4.1.4 Link Register Offsets

When an exception occurs, the link register is set to a specific address

based on the current pc.
For example when an IRQ exception is raised, the link register lr points to
the last executed instruction plus 8 because of three stage pipeline. Care
has to be taken to make sure the exception handler does not corrupt lr
because lr is used to return from an exception handler. The IRQ exception
is taken only after the current instruction is executed, so the return
address has to point to the next instruction, or lr − 4.
Table 4.4 provides a list of useful addresses for the different exceptions.

Table 4.4 Useful link-register-based addresses.

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Example(1)
This show the method of returning from an IRQ and FIQ handler is to use
a SUBS instruction:

Since there is an S at the end of the SUB instruction and the pc is the
destination register, the cpsr is automatically restored from the spsr
register.

4.2 Interrupts
There are two types of interrupts available on the ARM processor. The
first type of interrupt causes an exception raised by an external
peripheral—namely, IRQ and FIQ.

The second type is a specific instruction that causes an exception—the SWI

instruction.
Both types suspend the normal flow of a program.

a) Assigning Interrupts
• A system designer can decide which hardware peripheral can produce
which interrupt request.
• This decision can be implemented in hardware or software (or both)
and depends upon the embedded system being used.
• An interrupt controller unit is used to connects multiple external
interrupts to one of the two ARM interrupt requests either IRQ or FIQ.
• The system designers will use a standard design practice to
assigning interrupts.
• Software Interrupts are normally reserved to call privileged operating
system routines.
• IRQ Requests are normally assigned for general-purpose interrupts.
The IRQ exception has a lower priority and higher interrupt latency
than the FIQ exception.
• Fast Interrupt Requests are normally reserved for a single interrupt
source that requires a fast response time.
• In an embedded operating system design, the FIQ exception is used for
a specific application and the IRQ exception are used for more general
operating system activities.

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b) Interrupt Latency
• It is the time interval, from an external interrupt request signal
being raised to the first fetch of an instruction of a specific
interrupt service routine (ISR).
• Interrupt latency depends on a combination of hardware and
software. System designer must balance the system design to
handle multiple simultaneous interrupt sources and minimize
interrupt latency.
• Software handlers have two main methods to minimize interrupt
latency.
1) Nested interrupt handler,
2) Prioritization.

1)Nested interrupt handler

▪ Nested interrupt handler allows other interrupts to occur even
when it is currently servicing an existing interrupt.
▪ This is achieved by reenabling the interrupts as soon as the
interrupt source has been serviced but before the interrupt
handling is complete.
▪ Once a nested interrupt has been serviced, then control is
relinquished tothe original interrupt service routine. Fig 4.3 shows
the three-level nested interrupt,

Figure 4.3 A three-level nested interrupt.

2)Prioritization
▪ We can program the interrupt controller to ignore interrupts of
the same or lower priority than the interrupt we are handling
presently, so only a higher-priority task can interrupt our handler.
We then re-enable the interrupts.
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▪ The processor spends time in the lower-priority interrupts until a

higher-priority interrupt occurs.
▪ Therefore higher-priority interrupts have a lower average interrupt
latency than the lower-priority interrupts.
▪ It reduces latency by speeding up the completion time on the
critical time-sensitive interrupts.

c) IRQ and FIQ Exceptions

IRQ and FIQ exceptions only occur when a specific interrupt mask is
cleared in the cpsr.
The ARM processor will continue executing the current instruction in the
execution stage of the pipeline before handling the interrupt.
An IRQ or FIQ exception causes the processor hardware to go through a
standard procedure listed below,
1) The processor changes to a specific interrupt request mode, which
being raised.
2) The previous mode’s cpsr is saved into the spsr of the new interrupt
request mode.
3) The pc is saved in the lr of the new interrupt request mode.
4) Interrupt/s are disabled—either the IRQ or both IRQ and FIQ exceptions
are disabled in the cpsr. This immediately stops another interrupt request
of the same type being raised.
4)The processor branches to a specific entry in the vector table.

d) Enabling and Disabling FIQ and IRQ Exceptions

The ARM processor core has a simple procedure to manually enable and
disable interrupts by modifying the cpsr when the processor is in a
privileged mode.
The procedure uses three ARM instructions.
1)The instruction MRS copies the contents of the cpsr into register r1.
2)The instruction BIC clears the IRQ or FIQ mask bit.
3) The instruction MSR then copies the updated contents in register r1
back into the cpsr, to enable the interrupt request.

Table 4.5 shows how IRQ and FIQ interrupts are enabled.
Table 4.5 Enabling an interrupt.

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Table 4.6 shows procedure to disable or mask an interrupt request.

Table 4.6 Disabling an interrupt.

Basic Interrupt Stack Design and Implementation

Exceptions handlers use the stacks to save the register contents. Each
mode has dedicated register containing the stack pointer. The design of
the exception stacks depends upon these factors:
⚫ Operating system requirements—Each operating system has its
own requirements for stack design.
⚫ Target hardware—The target hardware provides a physical limit
tothe size and positioning of the stack in memory
Two design decisions need to be made for the stacks:

■ The location: which determines where in the memory map the stack
begins. Most ARM-based systems are designed with a stack that descends
downwards, with the top of the stack at a high memory address.
◼ Stack size: depends upon the type of handler, nested or non nested.
A nested interrupt handler requires more memory space since the stack
will grow with the number of nested interrupts.

Stack overflow—when the stack extends beyond the allocated memory.

It causes instability in embedded systems.
There are software techniques that identify overflow and that allow
corrective measures to take place to repair the stack before irreparable
memory corruption occurs.
The two main methods are
(1) use memory protection
(2) call a stack check function at the start of each routine.

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The IRQ mode stack has to be set up during the initialization code for the
system. The stack size is reserved in the initial stages of boot-up .
Figure 4.6 shows two memory layouts in a linear address space.

Figure 4.6 Memory layouts.

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