IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 31, NO.

5, MAY 2023 701

Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection Circuit

Jihwan Park and Hanwool Jeong

Abstract— In this brief, an energy-efficient, wide-range level shifter

(LS) with a logic error detection circuit (LEDC) is proposed. The
proposed LS is designed based on a current mirror-based LS (CMLS),
and a feedback pFET is added to solve the static current, which is a
limitation of the CMLS. Similarly, Wilson’s CMLS (WCMLS) solves the
problem of the CMLS through the feedback pFET; however, it cannot
convert low supply voltage (VDDL ) to high supply voltage (VDDH ) fully
due to the feedback pFET. In contrast, the proposed LS can convert VDDL
to full VDDH using the LEDC. To verify the performance between the
proposed LS and the previously proposed LS, the postlayout simulation
was performed using the 7-nm finFET model. The simulation results of Fig. 1. Two types of conventional LS. (a) CPLS. (b) CMLS.
the proposed LS show that the propagation delay and energy are 0.21 ns
and 20.43 fJ, respectively, at a low/high voltage of 0.4/1.2 V and an input VDDH -powered pFET for positive feedback to start. Thus, when
frequency of 1 MHz. (VDDH –VDDL ) increases, the contention is larger, causing functional
failure. Hence, the voltage conversion range is limited.
Index Terms— Current mirror, level shifter (LS), low power,
Fig. 1(b) shows the CMLS, which is free from the contention
near-threshold operation, wide range.
problem. Even if VDDH –VDDL is large, the CMLS can convert
VDDL –VDDH easily due to the diode-connected pFET. Thus, the
I. I NTRODUCTION CMLS has a wide range of input voltages than the CPLS. However,
Lowering the supply voltage is an effective way of reducing the when IN is high after the transition, a large static current path exists
dynamic power consumption of the system-on-chip (SoC). This is (M P1 –M N 1 ), making it impractical because of the large energy
because the dynamic power consumption of the SoC is proportional consumption.
to the square of the supply voltage (VDD ). Accordingly, operating Various schemes have been proposed to solve the limitation of the
a circuit in the near-threshold region can reduce the dynamic power two conventional LS structures [3], [4], [5], [6], [7], [8], [9], [10].
consumption by almost ten times compared with the nominal supply Although the limitations of the conventional LS are solved, each
voltage operation [1], [2]. However, with the use of the near-threshold of the announced LSs also has its limitations, which are discussed
VDD , degradation in the circuit operation speed is inevitable, making in Section II. In this brief, we propose an LS that solves the
the circuit more vulnerable to noise. Thus, to achieve power efficiency problems associated with the previously proposed LS. The structure
while minimizing the negative effects on the speed and operation and operation of the proposed LS are discussed in Section III. The
stability, it is desirable to use multi-VDD schemes; a high supply simulation results that verify the performance of various LSs are
voltage (VDDH ) is used for such noise-sensitive or speed-critical presented in Section IV. Finally, Section V concludes the study.
circuit blocks, while a low supply voltage (VDDL ) is used for the
remaining circuit blocks. When a multi-VDD is used, the signals from II. P REVIOUS LS S TRUCTURES
the blocks supplied with different voltages should not be directly In this section, the structure, operation, and limitations of the
connected. Instead, a level shifter (LS) that stably converts signals previously proposed LSs are briefly introduced. Fig. 2 shows the
between different voltage domains is required. To utilize the wide structure of various LSs and the sizing of each transistor. As 7-nm
range of VDD s in a single chip, the LS should be capable of finFET technology is used, only the number of fins is marked
converting the near-threshold voltage signal into the superthreshold on each transistor, while the length of all transistors is 20 nm.
voltage so that the power efficiency can be maximized. Fig. 2(a) shows an LS with a regulated cross-coupled (RCC) pull-
There are two types of conventional LS structures: the cross- up network [3]. To solve the contention problem, diode-connected
coupled pFET LS (CPLS) and the current mirror-based LS (CMLS), pFETs (M P3 and M P4 ) are added to regulate the pull-up strength.
as shown in Fig. 1(a) and (b), respectively. However, each of However, because of the diode-connected pFET, the OUT driving Q 2
these conventional LSs has limitations. The CPLS has a contention cannot achieve full swing. Thus, the conversion range is limited from
problem in the transition state. This is because, due to the cross- 0 to VDDH –|Vth,MP4 |, which increases the power consumption of the
coupled pFET structure, a VDDL -powered nFET must overcome a output buffer.
Manuscript received 8 September 2022; revised 17 January 2023; accepted Fig. 2(b) shows a CPLS with a current limiter [4]. To solve the
9 February 2023. Date of publication 22 February 2023; date of current version contention, X is biased to limit the pull-up current according to
26 April 2023. This work was supported in part by the National Research the value of VDDL . However, a static current path exists through
Foundation of Korea (NRF) grant funded by the Korean Government through M P3 –M N 3 because M N 3 is always turned on with VDDL .
the Ministry of Science and ICT (MSIT) under Grant 2020R1G1A1009777,
and in part by the Basic Science Program through the National Research Fig. 2(c) shows the CPLS with an adaptive current limiter [5].
Foundation of Korea (NRF) funded by the Ministry of Education under Grant To solve the static current in the LS, shown in Fig. 2(b), this circuit
2018R1A6A1A03025242. (Corresponding author: Hanwool Jeong.) selectively provides a pull-up current to either Q 1 or Q 2 that needs
The authors are with the Department of Electronic Engineering, Kwangwoon to be pulled up using a current mirror that operates according to the
University, Seoul 01897, South Korea (e-mail: [email protected]).
Color versions of one or more figures in this article are available at
logic states of IN and OUT. However, after the transition, the current
https://doi.org/10.1109/TVLSI.2023.3244569. mirror does not supply the pull-up current. Thus, Q 1 and Q 2 cannot
Digital Object Identifier 10.1109/TVLSI.2023.3244569 be driven to full VDDH .
1063-8210 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 702 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 31, NO. 5, MAY 2023

Fig. 2. Structure of existing LS with the number of fins for each transistor. (a) LS with an RCC pull-up network. (b) CPLS with a current limiter. (c) CPLS
with an adaptive current limiter. (d) Matsuzuka’s LS. (e) Wilson’s CMLS. (f) Osaki’s LS. (g) Hosseini’s LS. (h) Lotfi’s LS. (i) CMLS-LED.

Fig. 2(d) shows Matsuzuka’s LS [6], which is composed of the TABLE I

preamplifier and latch stage. The preamplifier stage uses a logic error S UMMARY OF P REVIOUS LS S TRUCTURES
correction circuit (LECC), which operates when the IN and OUT
logic states do not correspond and removes the static current of the
CMLS by using a feedback nFET. The contention in the latch stage is
mitigated because the input VDDL signal is amplified close to VDDH
in the preamplifier stage. However, the dual-stage operation limits
the circuit speed.
Fig. 2(e) shows Wilson’s CMLS (WCMLS) [7]. To solve the static
current problem in the conventional CMLS, the feedback pFET M P1
is added. However, gradually turned off M P1 raises V1 , turning off
M P2 and M P3 . This results in the degradation of OUT slope and
prevents OUT from attaining full VDDH .
Fig. 2(f) shows Osaki’s LS [8], which is composed of LECC
and a level conversion circuit. Using LECC, the static current is
removed because X is only pulled down during the transition of OUT.
However, during the rising and falling transition of OUT, contention
exists between M N 8 –M P6 and M N 3 –M P1 , respectively. In addition,
when VDDH –VDDL is small, Y is pulled down before OUT rises, and Fig. 3. Schematic of the proposed LS with the number of fins for each
thus, OUT cannot reach full VDDH . transistor.
Fig. 2(g) shows Hosseini’s LS [9], which aims to cut off the static
III. P ROPOSED LS
current path with the feedback nFET M N 4 when IN is high. However,
a problem arises when VDDH –VDDL is small because A is pulled Table I summarizes the limitations of the previous LS, as shown
down by M N 3 before OUT increases due to the increased strength in Fig. 2(a)–(i). Each previous LS solves the limitations of the
of M N 3 . Thus, OUT cannot reach full VDDH , meaning that a stable conventional LS, but none of the previous LSs solves all the
level-shifting operation is not achieved. limitations listed in Table I. Thus, in this brief, we propose a novel
Fig. 2(h) shows Lotfi’s LS [10], which cuts off static current by LS that solves all the limitations and guarantees a low-power-, low-
flowing current only during high-to-low transition of IN through delay-, and wide-range operation.
turning off M N 2 . In addition, by creating a voltage difference between Fig. 3 shows the proposed LS, which is composed of two parts: the
G P and G N with the diode-connected pFET M P3 , the contention left part is the level-shifting circuit and the right part is an LED circuit
between pull-up and pull-down of OUT is reduced. However, when (LEDC). The proposed LS is designed to solve the limitation of the
falling transition of OUT, because G P cannot reach full VDDH and WCMLS. The reason of the limitation in WCMLS is that OUT rises
voltage of G N is lower than the voltage of G P , OUT cannot be fully and M P1 is gradually turned off; thus, the node V1 in Fig. 2(e) rises
lowered to the ground. and the pull-up current no longer flows to OUT. Hence, to maintain
Fig. 2(i) shows the CMLS with logic error detection (CMLS-LED) the pull-up current flowing to OUT, V1 should be fully lowered to
[11], which aims to cut the static current by feedback pFET of M P3 . the ground and remain low when IN is high. In the proposed LS,
CMLS-LED is composed level-shifting part and logic error detection X, which is similar to V1 in WCMLS of Fig. 2(e), is connected to
(LED) part. LED part is used to turn off M P4 by generating ERR the drain of M N 1 . In this manner, when IN is VDDL , X is pulled
signal like a pulse when IN and OUT are different at the falling down to the ground and kept low by M N 1 . This fully turns on M P3
transition of IN. The reason for turning off M P4 during the falling so that the pull-up current can be stably provided to OUT through
transition is to cut off the pull-up current from M P2 , which is turned M P3 –M P4 . OUT can then reach full VDDH and remain high.
on by low X. However, at the falling transition, M P3 or M P4 should be turned
However, when VDDL is lowered to near-threshold level, contention off in the proposed LS to pull down OUT without contention.
between M P2 –M P4 and M N 2 occurs since ERR is not raised enough To accomplish this goal, the LEDC is added to turn off M P4 at the
to turn off M P4 . Consequently, the voltage range is significantly falling edge of IN and block the pull-up current from M P3 . It should
limited. The proposed LS in this brief tackles this problem by revising be noted that the LEDC generates a Y signal that only becomes near
the structure of LED, which is to be explained in detail in Section III. VDDH when IN and OUT are different (i.e., logic error) at the falling

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 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 31, NO. 5, MAY 2023 703

Fig. 4. Operation details of the proposed LS (a) during the rising transition
of IN and OUT and (b) falling transition of IN and OUT.

Fig. 6. Comparison of 3σ worst delay for (a) different VDDL values when
VDDH = 1.2 V and (b) different VDDH values when VDDL = 0.4 V.

In addition, it should be noted that Y does not need to reach full

VDDH , because even if M P4 is not turned off completely, the pull-up
Fig. 5. Voltage and current waveforms of (a) rising transition and (b) falling strength of OUT is significantly lower than the pull-down strength of
transition in the proposed LS when VDDL = 0.4 V and VDDH = 1.2 V. M N 2 . Consequently, OUT can be pulled down by M N 2 . In addition,
when OUT falls, M P1 turns on gradually. Thus, the diode-connected
transition of IN. The specific falling transition procedure of the LEDC pFET of M P2 pulls X up to VDDH –|Vth ,MP2 |. The resultant turned-
is described later. off M P3 limits the pull-up current to OUT, which accelerates the
The operation of the rising transition in the proposed LS is shown falling transition of OUT.
in Fig. 4(a). Before IN and OUT rise, because M P1 is turned on The transistor size is set to minimize the delay of the proposed
by a low OUT, M P2 pulls up X to VDDH –|Vth,MP2 |, and therefore, LS. In this manner, the energy can also be reduced by minimizing
M P2 and M P3 are turned off. Therefore, when IN rises, M N 1 turns the short-circuit current. To achieve this goal, the size of M P3 –M P4
on and easily pulls down X. Subsequently, M P2 and M P3 are turned is set large enough to provide a sufficient pull-up current to OUT.
on to provide the pull-up current to OUT. Simultaneously, M N 3 is In addition, M N 1 is set to a large size to increase the pull-down
turned on and Y is lowered. Consequently, by turning on M P4 , OUT strength of X so that M P3 is quickly turned on at the rising transition
is pulled up. In addition, during the rising transition of OUT, M P1 is of IN. With regard to the falling operation, the size of M N 2 is set to
turned off; thus, X is fully lowered to the ground. Therefore, when be large to efficiently pull OUT downward. The size of transistors in
IN is high, OUT can reach full VDDH and remain high. LEDC is set small for less energy consumption.
Fig. 5 shows the waveform of the proposed LS operation and the
current sum of IVDDH and IVDDL . As shown in Fig. 5(a), during
the rising transition, contention exists at X. Contention causes short- IV. Q UANTITATIVE A NALYSIS
circuit current through M P2 –M P1 –M N 1 and degrades the rising This section describes the comparison of the proposed LS with
slope of OUT, which increases the delay and energy consumption. various previously proposed LSs shown in Figs. 1(a) and 2(a)–(i) in
Nevertheless, the proposed LS shows a small delay and energy terms of delay, energy, and area. Simulation results were obtained
compared to other LSs as shown in Section III of the simulation from a postlayout simulation using HSPICE, with the ASAP 7-nm
results. finFET model [12]. To consider an output slope, the inverter whose
The operation for the falling transition in the proposed LS is shown nFET and pFET have Nfin = 8 was connected to the output of all
in Fig. 4(b). When IN falls, the initial state of OUT is equal to VDDH . LSs as a load circuit. For a fair comparison, simulation results of LS
When a logic error occurs between IN and OUT, M N 4 and M N 5 that do not satisfy the target operation yield of 3σ are excluded. For
in the LEDC are turned on by INb and OUT, respectively, which example, the simulation results of WCMLS and Hosseini’s LS are
turns on M P6 . Simultaneously, M P5 is turned on by the lowered IN, excluded because the rising slope is severely degraded by negative
leading to the pull-up of Y. Consequently, M P4 is turned off to block OUT feedback, which does not satisfy the target yield. In addition,
the pull-up current from M P3 , and thus, OUT can be fully driven to the simulation results of Osaki’s LS are excluded because the rising
the ground by M N 2 . and falling operation of Osaki’s LS is problematic by negative OUT
The improvement of LEDC in the proposed LS compared to feedback.
CMLS-LED is that Y is pulled up more easily than ERR in the The delay is compared in the 3σ worst value, through the worse
CMLS-LED of Fig. 2(i) for the same VDDL condition (both Y and one between the rising and falling delays, which are obtained from the
ERR control M P4 ) because M N 3 of the proposed LS is completely Monte Carlo simulation. Fig. 6(a) presents a comparison of various
turned off by low IN. Thus, unlike CMLS-LED, a wider voltage LS delays. The table in Fig. 6(a) shows the ratio of the delay based on
range is achieved because M P4 can be sufficiently turned off by Y. the delay of the proposed LS. The simulation results were obtained by

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 704 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 31, NO. 5, MAY 2023

fixing VDDH at 1.2 V, while VDDL was swept from the near-threshold
voltage of 0.4 V to the superthreshold voltage of 1.0 V.
In the CPLS, when VDDL is 0.4 V, positive feedback is not
triggered due to contention, and thus, the level-shifting operation is
not achieved. When VDDL = 0.5 V, the delay is 105.7 times larger
than that of the proposed LS and decreases to 0.6 times when VDDL
is 1.0 V. As a result, when the voltage difference is large, CPLS
cannot be used due to the very large delay.
In the RCC, when VDDL is 0.4 V, the delay is 1.0 times of the
proposed LS delay. However, because OUT is pulled up by the diode-
connected pFET, the rising slope of OUT is degraded; thus, the delay
is up to 1.4 times larger than that of the proposed LS when VDDL
is 1.0 V. In the CPLS with a current limiter, the delay is 1.1–20.7
times larger than that of the proposed LS. This is because when
VDDH –VDDL increases, M P1 and M P2 are weakly turned on, which
results in a long development time for nodes Q 1 and Q 2 . In the
CPLS with an adaptive current limiter, when OUT rises, the pull-up
current is reduced by feedbacks of M N 3 and M N 4 . Hence, the delay
is 1.3 times larger than that of the proposed LS.
The delay of Matsuzuka’s LS is 1.1–1.4 times that of the proposed Fig. 7. Comparison of energy at the input frequency of 1 MHz for
(a) different VDDL values when VDDH = 1.2 V and (b) different VDDH values
LS because of the dual-stage operation. In CMLS-LED, when VDDL when VDDL = 0.4 V.
is higher than 0.6 V, the delay is comparable with the proposed LS
delay. However, when VDDL is lower, the contention issue of CMLS-
LED becomes significant, which greatly increases the delay. Thus,
when VDDL is 0.4 V, the delay of CMLS-LED is 60.5 times larger
than the proposed LS delay.
In Lotfi’s LS, when VDDL is less than 0.6 V, the target yield (3σ )
is not satisfied, and thus, simulation results are excluded. This is
because, due to the negative feedback, OUT of Lotfi’s LS cannot be
lowered to the ground, which is severe when VDDL is much lower
than VDDH . The delay of Lotfi’s LS, which is compared in the range
that satisfies the target yield, is 1.2–1.3 times larger than that of the
proposed delay.
Fig. 8. Minimum operating VDDL according to input frequencies when
Fig. 6(b) presents a comparison of the delay of the LS for different VDDH = 1.2 V.
values of VDDH when VDDL is 0.4 V. Compared to the VDDL
change, the delay is less sensitive to VDDH . This is because, when because of the contention as VDDL decreases, the energy consumption
VDDH increases, there are two counter effects on the delay: 1) the of CMLS-LED exceedingly increases. Thus, CMLS-LED has
drivability of the VDDH -powered pFET increases, which has the effect 36 times larger energy consumption than the energy of the proposed
of reducing the delay, and 2) the contention becomes stronger, which LS when VDDL = 0.4 V.
has the effect of increasing the delay, whereas the delay of the CPLS The CPLS with a current limiter is excluded from the graph
with a current limiter and CMLS-LED is sensitive to VDDH . because the static current path M P3 –M N 3 consumes an exceedingly
In CPLS with a current limiter, the delay of CPLS with a current large amount of energy. The energy consumption of the RCC and
limiter is 15.3–38.7 times larger than the proposed LS delay. This is CPLS with an adaptive current limiter is similar to that of the
because M P1 and M P2 are further weakly turned on with increasing proposed LS. However, OUT of these LSs cannot reach full VDDH .
VDDH , so the current required for pulling up Q 1 or Q 2 is limited, In Matsuzuka’s LS, because of the dual-stage operation, the energy
degrading the rising delay. In CMLS-LED, when VDDH increases, the consumption is 1.1–1.7 times larger than that of the proposed LS.
delay becomes exceedingly larger than the proposed LS delay due Fig. 7(b) presents a comparison of the energy of the LS for different
to the contention. These cases exhibiting exceedingly large delay are values of VDDH when VDDL is 0.4 V, and the input frequency
excluded in the graph. In addition, the simulation results of Lotfi’s is 1 MHz. When VDDH increases, the energy of all the LSs increases.
LS show only when VDDH is lower than 1 V. This is because larger In particular, because of contention, as VDDH increases, the energy of
VDDH –VDDL does not satisfy the target yield. Simulation results of CMLS-LED exceedingly increases compared to other LSs. Therefore,
CPLS in Fig. 6(b) cannot be obtained because CPLS does not operate when VDDH is more than 0.9 V, the simulation results are excluded
for low VDDL (= 0.4 V). in Fig. 7(b). The simulation result of CPLS is also excluded in Fig.
Fig. 7(a) presents a comparison of the energy of the LS for different 7(b), because when VDDL is 0.4 V, the level-shifting operation is not
values of VDDL when VDDH is 1.2 V, and the input frequency achieved. The ratios in the table of Fig. 7(b) have similar values and
is 1 MHz. To reflect the effect of OUT, the energy of the load inverter exhibit a similar trend to those in the table of Fig. 7(a).
is included. The table in Fig. 7(a) shows the ratio of the energy Fig. 8 presents the minimum operating VDDL according to input
based on the energy of the proposed LS. In Fig. 7(a), the energy frequencies with VDDH of 1.2 V. The simulation result of Lotfi’s
consumption of most LSs is invariant for different VDDL values LS cannot be obtained because OUT cannot be fully lowered to the
because the energy consumption is dominant for the VDDH values. ground due to negative OUT feedback. In Fig. 8, CPLS has the largest
However, the case of CPLS and CMLS-LED is exceptions. In CPLS, minimum operating VDDL due to the contention. This implies that
when VDDL is 0.5 V, the CPLS has large energy consumption because the operation range of CPLS is highly limited compared to the other
a large VDDH –VDDL causes a strong contention. In CMLS-LED, structures. The LS of the second-largest minimum operating VDDL is

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The static power of RCC pull-up and Matsuzuka’s LS is large

because the pFETs, which are turned off with gate voltage of
VDDH –|Vthp | due to the diode-connected pFET, flow the static
current. Similar to RCC pull-up and Matsuzuka’s LS, pFET in the
CPLS with adaptive current and the proposed LS are also turned
off with the gate voltage of VDDH –|Vthp |; however, the static power
is much smaller than RCC pull-up LS and Matsuzuka’s LS. This
is because two-stacked pFETs reduce the static current. When
one of the stacked pFETs is turned off with the gate voltage of
Fig. 9. 3σ worst delay of the proposed LS for –40 ◦ C, 25 ◦ C, and 120 ◦ C VDDH –|Vthp |, the other is weakly or completely turned off. Although
at different VDDL s when VDDH = 1.2 V.
RCC pull-up LS also has two-stacked pFETs, one of the stacked
pFET, which is fully turned on with the gate voltage of 0 by node
Q1 or Q2 in Fig. 2(a), flows a larger static current. Thus, the static
power of the RCC pull-up LS is large.
As shown in Table II, the proposed LS is not the smallest, but it
is a competitive size, compared to various LSs.

V. C ONCLUSION
In this brief, we propose an energy-efficient and wide-range LS
that can convert a near-threshold voltage to a superthreshold voltage
Fig. 10. Layout of the proposed structure. by utilizing the current mirror structure. Due to the LEDC, the
proposed LS only dissipates current in the transition state and solves
TABLE II the limitations of the WCMLS; thus, the proposed LS is capable
P ERFORMANCE C OMPARISON OF VARIOUS LS of energy-efficient operation. Quantitative analysis was performed
S TRUCTURES (VDDL = 0.4 V, VDDH = 1.2 V)
through a postlayout simulation using the ASAP 7-nm model, which
proved the superiority of the LS in delay and energy consumption.

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power measured during the idle time after the transition. In Table II, pp. 34–37, Feb. 2018.
the simulation results of CPLS and Lotfi’s LS are excluded. This is [11] H. Jeong, T.-H. Kim, C. N. Park, H. Kim, T. Song, and S.-O.
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and Lotfi’s LS cannot satisfy the target yield. In addition, due to the logic error detection for near-threshold operation,” IEEE J. Solid-State
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static current path, the energy and static power of current limiter are
[12] L. T. Clark et al., “ASAP7: A 7-nm FinFET predictive process design
exceedingly large, and thus, these are excluded in Table II. kit,” Microelectron. J., vol. 53, pp. 105–115, Jul. 2016.

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