MEMORY I NTERFACING AND IO INTERFACING

In a microprocessor system, there are two methods of interfacing input/output (I/O) devices: memory-mapped I/O and I/O
mapped I/O. In memory-mapped I/O, input/output devices are mapped to the memory address space of the
microprocessor. This means that the I/O devices are treated like memory locations and can be accessed using the same
read and write instructions as memory. In other words, the same bus and control signals used for memory access are used
for I/O access as well.
On the other hand, in I/O mapped I/O, input/output devices are mapped to a separate I/O address space that is different
from the memory address space. The microprocessor uses special instructions to access the I/O devices using specific I/O
address signals, which are separate from the memory address signals.
This method of I/O access is simpler and more efficient in terms of hardware design, as it does not require separate I/O
address signals. However, it limits the number of memory locations available for use by the microprocessor.
The microprocessor cannot do anything by itself therefore, It needs to be linked with memory, extra peripherals, or IO
devices. This linking is called Interfacing. The interfacing of the I/O devices in 8085 can be done in two ways : 1.
Memory-Mapped I/O Interfacing : In this kind of interfacing, we assign a memory address that can be used in the same
manner as we use a normal memory location. 2. I/O Mapped I/O Interfacing : A kind of interfacing in which we assign
an 8-bit address value to the input/output devices which can be accessed using IN and OUT instruction is called I/O
Mapped I/O Interfacing.
Difference between Memory-Mapped I/O Interfacing and I/O Mapped I/O Interfacing :
Features Memory Mapped IO IO Mapped IO

Addressing IO devices are accessed like any other memory They cannot be accessed like any other
location. memory location.

Address Size They are assigned with 16-bit address values. They are assigned with 8-bit address values.

Instructions Used The instruction used are LDA and STA, etc. The instruction used are IN and OUT.

Cycles Cycles involved during operation are Memory Cycles involved during operation are IO read
Read, Memory Write. and IO writes in the case of IO Mapped IO.

Registers Any register can communicate with the IO Only Accumulator can communicate with IO
Communicating device in case of Memory Mapped IO. devices in case of IO Mapped IO.

Space Involved 216 IO ports are possible to be used for Only 256 I/O ports are available for
interfacing in case of Memory Mapped IO. interfacing in case of IO Mapped IO.

IO/M` signal During writing or read cycles (IO/M` = 0 ) in During writing or read cycles (IO/M` = 1) in
case of Memory Mapped IO. case of IO Mapped IO.

Control Signal No separate control signal required since we Special control signals are used in the case of
have unified memory space in the case of IO Mapped IO.
Memory Mapped IO.
 Arithmetic and Arithmetic and logical operations are performed Arithmetic and logical operations cannot be
Logical operations directly on the data in the case of Memory performed directly on the data in the case of
Mapped IO. IO Mapped IO.

Hardware Only one set of address and data buses are Separate address and data buses are required
requirements required for memory and I/O devices for memory and I/O devices

Instruction set Uses the same instructions for accessing both Special instructions are used for accessing I/O
memory and I/O devices devices

Address range Limited number of memory locations available Dedicated address space available for I/O
for use by the microprocessor devices

Design complexity Simple to implement and design More complex to implement and design

SERIAL AND PARALLEL COMMUNICATION INTERFACE

There are two methods used for transferring data between computers which are given below.
Serial Transmission: In Serial Transmission, data-bit flows from one computer to another computer in bi-direction. In
this transmission, one bit flows at one clock pulse. In Serial Transmission, 8 bits are transferred at a time having a start
and stop bit.

Parallel Transmission: In Parallel Transmission, many bits are flow together simultaneously from one computer to
another computer. Parallel Transmission is faster than serial transmission to transmit the bits. Parallel transmission is used
for short distance.

Difference between Serial and Parallel Transmission:

Serial Transmission Parallel Transmission

S.NO
 Serial Transmission Parallel Transmission
S.NO

In this type, a single communication link is In this type, multiple parallels links
1.
used to transfer data from one end to another used to transmit the data

In serial transmission, data(bit) flows in bi- In Parallel Transmission, data flows

2.
direction. in multiple lines.

Parallel Transmission is not cost-

3. Serial Transmission is cost-efficient.
efficient.

In serial transmission, one bit transferred at In Parallel Transmission, eight bits

4.
one clock pulse. transferred at one clock pulse.

Serial Transmission is slow in comparison of Parallel Transmission is fast in

5.
Parallel Transmission. comparison of Serial Transmission.

Generally, Serial Transmission is used for long- Generally, Parallel Transmission is

6.
distance. used for short distance.

The circuit used in Serial Transmission is The circuit used in Parallel

7.
simple. Transmission is relatively complex.

Parallel Transmission is half-duplex

Serial Transmission is full duplex as sender
8. since the data is either send or
can send as well as receive the data
receive

Converters are required in a serial transmission

No converters are required in
9. to convert the data between internal and
Parallel Transmission
parallel form

Serial transmission is reliable and Parallel transmission is unreliable

10.
straightforward. and complicated.

1. 8255A - Programmable Peripheral Interface

INTRODUCTION: The 8255A is a general purpose programmable I/O device designed to transfer the
data from I/O to interrupt I/O under certain conditions as required. It can be used with almost any
microprocessor.
It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as per the requirement.
Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
  Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) by the
control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and upper PORT C. Group
B includes PORT B and lower PORT C. These two groups can be programmed in three different modes, i.e. the
first mode is named as mode 0, the second mode is named as Mode 1 and the third mode is named as Mode 2.
Features of 8255A
The prominent features of 8255A are as follows −
 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux'd.
 It is TTL compatible.
 It has improved DC driving capability.
8255 Architecture/ Block Diagram
The following figure shows the architecture of 8255A –

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus. Data is
transmitted or received by the buffer as per the instructions by the CPU. Control words and status information is
also transferred using this bus.
Read/Write Control Logic
This block is responsible for controlling the internal/external transfer of data/control/status word. It accepts the
input from the CPU address and control buses, and in turn issues command to both the control groups.
CS
It stands for Chip Select. A LOW on this input selects the chip and enables the communication between the
8255A and the CPU. It is connected to the decoded address, and A0 & A1 are connected to the microprocessor
address lines.
Their result depends on the following conditions −
CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B
0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection
WR
It stands for write. This control signal enables the write operation. When this signal goes low, the
microprocessor writes into a selected I/O port or control register.
RESET
This is an active high signal. It clears the control register and sets all ports in the input mode.
RD
It stands for Read. This control signal enables the Read operation. When the signal is low, the microprocessor
reads the data from the selected I/O port of the 8255.
Control Word/Register

Operating Modes
8255A has 2 different operating modes −

1. Bit set reset (BSR) mode – This mode is used to set or reset the bits of port C only, and selected when the
most significant bit (D7) in the control register is 0. Control Register is as

2. Input/output mode (I/O) – This mode is selected when the most significant bit (D7) in the control register
is 1.
 Mode 0 – Simple or basic I/O mode: Port A, B and C can work either as input function or as output
function. The outputs are latched but the inputs are not latched. It does not have interrupt handling
capability.
 Mode 1 – Handshake or strobed I/O: In this either port A or B can work and port C bits are used to
provide handshaking. The outputs as well as inputs are latched. It has interrupt handling capability.
Before actual data transfer there is transmission of signal to match speed of CPU and
printer. Example: When CPU wants to send data to a slow peripheral device like printer, it will send
handshaking signal to printer to tell whether it is ready or not to transfer the data. When the printer is
ready it will send one acknowledgement to CPU then there will be transfer of data through data bus.

 Mode 2 – Bidirectional I/O: In this mode only port A will work, port B can either is in mode 0 or 1 and
port C bits are used as handshake signal. The outputs as well as inputs are latched. It has interrupt
handling capability. Control Register is as follows:

 The most significant bit (D7) is 1 for the I/O mode and 0 for the BSR mode. D6 & D5It is used to set the
port A mode.

2. 8259 PIC Microprocessor

Introduction: The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In 8085 and
8086 there are five hardware interrupts and two hardware interrupts respectively. Bu adding 8259, we can
increase the interrupt handling capability. This chip combines the multi-interrupt input source to single interrupt
output. This provides 8-interrupts from IR0 to IR7. Let us see some features of this microprocessor.
 This chip is designed for 8085 and 8086.
 It can be programmed either in edge triggered, or in level triggered mode
 We can mask individual bits of Interrupt Request Register.
 By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines
 Clock cycle is not needed
Architecture of 8259
Data Bus Buffer This block is used to communicate between 8259 and 8085/8086 by acting as buffer. It takes
the control word from 8085/8086 and send it to the 8259. It transfers the opcode of the selected interrupts and
address of ISR to the other connected microprocessor. It can send maximum 8-bit at a time.

R/W Control Logic This block works when the value of pin CS is 0. This block is used to flow the data
depending upon the inputs of RD and WR. These are active low pins for read and write.

Control Logic It controls the functionality of each block. It has pin called INTR. This is connected to other
microprocessors for taking the interrupt request. The INT pin is used to give the output. If 8259 is enabled, and
also the interrupt flags of other microprocessors are high then this causes the value of the output INT pin high,
and in this way this chip can responds requests made by other microprocessors.

Interrupt Request Register It stores all interrupt level that are requesting for interrupt service.

Interrupt Service Register It stores interrupt level that are currently being execute.

Interrupt Mask Register It stores interrupt level that will be masked, by storing the masking bits of interrupt
level.

Priority Resolver It checks all three registers, and set the priority of the interrupts. Interrupt with the highest
priority is set in the ISR register. It also reset the interrupt level which is already been serviced in the IRR.

Operating modes of 8259 :

Fully nested mode :
 It is the default mode of operation of 8259.
  Here, IR0 has the highest priority and IR7 has the lowest priority. When any interrupt requests occurs
then the highest priority interrupt request is serviced first and its vector address is placed on data bus and
its corresponding bit in ISR register is set until the processor executes the EOI command before
returning the interrupt service routine or AEOI(Automatic end of interrupt bit is set) until the falling of
the last INTA’.
 When the ISR bit is set for an interrupt, then all the equal and lower priority interrupts are masked, but a
higher level interrupt request can occur and which will be acknowledged only if the microprocessor
interrupt enables flag IF= 1.
 It is suitable for a single 8259 configuration.
 The priority mechanism can be easily programmed.
Special fully nested mode (SFNM) :
This mode is used by master 8259 in a cascaded mode. Its priority structure is fixed and is the same as fully
nested mode (i.e. IR0 has the highest priority and IR7 has the lowest priority).
In a special fully nested mode, the master will only serve higher priority interrupt from a slave, whose another
interrupt is currently in service.

3. Intel 8253 - Programmable Interval Timer

Introduction: The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors
to perform timing and counting functions using three 16-bit registers. Each counter has 2 input pins, i.e. Clock
& Gate, and 1 pin for “OUT” output. To operate a counter, a 16-bit count is loaded in its register. On command,
it begins to decrement the count until it reaches 0, then it generates a pulse that can be used to interrupt the
CPU.
Features of 8253 / 54
The most prominent features of 8253/54 are as follows −
 It has three independent 16-bit down counters.
 It can handle inputs from DC to 10 MHz.
 These three counters can be programmed for either binary or BCD count.
 It is compatible with almost all microprocessors.
 8254 has a powerful command called READ BACK command, which allows the user to check the count
value, the programmed mode, the current mode, and the current status of the counter.
8254 Architecture
In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a control register.
Each counter has two input signals - CLOCK & GATE, and one output signal - OUT.
Data Bus Buffer
It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system data bus. It has
three basic functions −
 Programming the modes of 8253/54.
 Loading the count registers.
 Reading the count values.
Read/Write Logic
It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O mode, the RD and
WR signals are connected to IOR and IOW, respectively. In the memorymapped I/O mode, these are connected
to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is tied to a decoded
address. The control word register and counters are selected according to the signals on lines A0 & A1.
A1 A0 Result

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection
Counters
Each counter consists of a single, 16 bit-down counter, which can be operated in either binary or BCD. Its input
and output is configured by the selection of modes stored in the control word register. The programmer can read
the contents of any of the three counters without disturbing the actual count in process.
Intel 8253/54 - Operational Modes
8253/54 can be operated in 6 different modes. In this chapter, we will discuss these operational modes.
Mode 0 ─ Interrupt on Terminal Count
 It is used to generate an interrupt to the microprocessor after a certain interval.
 Initially the output is low after the mode is set. The output remains LOW after the count value is loaded
into the counter.
 The process of decrementing the counter continues till the terminal count is reached, i.e., the count
become zero and the output goes HIGH and will remain high until it reloads a new count.
 The GATE signal is high for normal counting. When GATE goes low, counting is terminated and the
current count is latched till the GATE goes high again.
Mode 1 – Programmable One Shot
 It can be used as a mono stable multi-vibrator.
 The gate input is used as a trigger input in this mode.
 The output remains high until the count is loaded and a trigger is applied.
Mode 2 – Rate Generator
 The output is normally high after initialization.
 Whenever the count becomes zero, another low pulse is generated at the output and the counter will be
reloaded.
Mode 3 – Square Wave Generator
 This mode is similar to Mode 2 except the output remains low for half of the timer period and high for
the other half of the period.
Mode 4 − Software Triggered Mode
  In this mode, the output will remain high until the timer has counted to zero, at which point the output
will pulse low and then go high again.
 The count is latched when the GATE signal goes LOW.
 On the terminal count, the output goes low for one clock cycle then goes HIGH. This low pulse can be
used as a strobe.
Mode 5 – Hardware Triggered Mode
 This mode generates a strobe in response to an externally generated signal.
 This mode is similar to mode 4 except that the counting is initiated by a signal at the gate input, which
means it is hardware triggered instead of software triggered.
 After it is initialized, the output goes high.
 When the terminal count is reached, the output goes low for one clock cycle.

4. 8257 DMA Controller

Introduction
DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It allows the
device to transfer the data directly to/from memory without any interference of the CPU. Using a DMA
controller, the device requests the CPU to hold its data, address and control bus, so the device is free to transfer
data directly to/from the memory. The DMA data transfer is initiated only after receiving HLDA signal from the
CPU.
DMA Operations
Following is the sequence of operations performed by a DMA −
 Initially, when any device has to send data between the device and the memory, the device has to send
DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the
control over bus and acknowledges the HOLD request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses
between the CPU, memory, and I/O devices.
Features of 8257
Here is a list of some of the prominent features of 8257 −
 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer operations.
 It generates MARK signal to the peripheral device that 128 bytes have been transferred.
 It requires a single phase clock.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in 2 modes, i.e., Master mode and Slave mode.
8257 Architecture
The following image shows the architecture of 8257 −
8257 Description
The following image shows the pin diagram of a 8257 DMA controller −

DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the peripheral devices for using
DMA services. When the fixed priority mode is selected, then DRQ0 has the highest priority and DRQ3 has the
lowest priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the status of
their request by the CPU. These lines can also act as strobe lines for the requesting devices.
Do − D7
These are bidirectional, data lines which are used to interface the system bus with the internal data bus of DMA
controller. In the Slave mode, it carries command words to 8257 and status word from 8257. In the master
mode, these lines are used to send higher byte of the generated address to the latch. This address is further
latched using ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal registers of 8257
in the Slave mode. In the master mode, it is used to read data from the peripheral devices during a memory
write cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the 8-bit mode
register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master mode, it
is used to load the data to the peripheral devices during DMA memory read cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.
Ao - A3
These are the four least significant address lines. In the slave mode, they act as an input, which selects one of
the registers to be read or written. In the master mode, they are the four least significant memory address output
lines generated by 8257.
CS
It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from 8257. In the
master mode, it disables the read/write operations to/from 8257.
A4 - A7
These are the higher nibble of the lower byte address generated by DMA in the master mode.
READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.
HRQ
This signal is used to receive the hold request signal from the output device. In the slave mode, it is connected
with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus has been granted to the
requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed memory locations during
DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed memory location during
DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address generated by the DMA controller into the
latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It indicates the
current DMA cycle is the 128th cycle since the previous MARK output to the selected peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit.