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Best design practices for DFT

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1. Introduction

SoC sub-components (IPs) generally come from various sources – internal and external – and
with that it has become necessary that designers ensure the RTL is testable. If the RTL has
testability issues, test coverage goals can’t be met and the RTL needs to be modified, which

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means several iterations of synthesis, verification, and Automatic Test Pattern Generation
(ATPG).

Here we will discuss the basic design practices to ensure proper testability.

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2. Clock Control

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Figure 1: SHIFT_MODE = 1 during shift

2.2 Internally generated clocks

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For all internally generated clocks a bypass should be provided. In case there is a requirement of
this clock, say we need PLL clock for at-speed testing, then a clock control logic should be added
on them.

Figure 2: Bypassing all internally generated clock

An example for this would be clock generated by sequential logic:

Here the clock is generated by the output of a flop, since this generated clock is not directly
controllable by the ATPG tool, we need to add clock control logic.

Figure 3: Bypass for clock generate from a flop

2.3 Test clock selection

It must be ensured that test clock frequency is always greater than or equal to the functional clock
frequency, so that we never end up under-testing a logic.

2.4 Using clock as data

When clock is used as data in a design, then it must always be ensured that we use test mode
signal to gate this data path (i.e., clock to the data cone). Otherwise a race condition may result
that produces an inaccurate simulation results.

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Figure 4: Eliminating race condition

3. Un-clocked latches

Static Timing Analysis (STA) team closes timing only on those sequential elements which are
clocked. If the enable/clock of the latch comes from the output of a flop, STA team doesn’t check
it for timing, which may lead to erroneous latching of the data. It will be caught either in simulation
or on silicon. This can be prevented if the enable of the latch is a valid clock (gated or ungated).

Figure 5: Un-clocked latch

Zero Delay (ATPG/Idle):

ATPG tools while generating patterns works on a zero delay type simulation model. Data is
sampled just before the clock edge, so from tool’s perspective, the output is always high during
pattern generation in this case.

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Figure 6(a): Zero Delay

Data Skewed with respect to clock (Simulation):

In simulation, due to skew in design between the data and clock we can have two scenarios, data
coming either early or late and in both such cases we will start getting fails.

Figure 6(b): Data Early

Figure 6(c): Data Delayed

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4. Reset Control

As discussed previously, clock and reset of a flop must be fully controllable. To achieve this, a
multiplexer is placed in the reset path as shown below. The first input of the multiplexer is the
functional reset as before. The second input is the DFT (test) controlled RESET and the select
line (test mode) is used by DFT to switch to the controlled reset in test mode.

Figure 7: Reset control using mux

4.1 Cascading of switching logic in the reset path

The select signal (Reset Override) is not timed by the timing team, so any random skew in this
signal must not affect the state of any of the flops. If two or more such switching logics are
cascaded as shown, this may result in a glitch to the RESET pin of the flop which will corrupt its
state.

Figure 8(a): Cascaded reset control logic

Zero Delay (ATPG):

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Due to zero delay in ATPG, the select line M1 & M2 will toggle at the same time so the reset RST
is always high.

Figure 8(b): Zero Delay ATPG

Delay between M1 & M2 (simulation)

Due to interconnect delay, M2 makes a late transition than M1 resulting in a glitch at reset
resetting the flop.

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Figure 8(c): Real simulation Scenario

In order to solve the problem, only a single multiplexer should be used in the reset path.

4.2 Synthesis of switching logic for controlling reset

As mentioned above, a multiplexer is added before the reset of a flop. During synthesis, this
multiplexer may be converted to complex gates (AOI – AND OR INVERT) as shown in figure 9(a).

Figure 9(a): Synthesized mux

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This scenario may result in a glitch at the reset of the flop leading to the false output.

Figure 9(b): A failing scenario

To prevent the glitch, this multiplexer should be preserved using pragma in RTL so that the logic
is synthesized as a glitch-free multiplexer instead of any random AOI combination working as a
multiplexer.

5. Common source of inputs of combinational logic

A combinational logic (for example 2-input AND gate or a 2-input OR gate) having both its inputs
driven from same source with one being inverted will maintain the same constant output value
regardless of the state of the driving node, but the output will probably contain a glitch when the
driving node changes state.

Figure 10: Two input AND gate with common input sources

6. Combinational Loops

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When the output of a combination logic is fed back to one of its input, a combination loop is
formed. ATPG tool simulates the design assuming zero delay in combinational elements which
may result in undetermined output for one or more input combinations.

Figure 11: Combinational Loops

As shown above, the input combination (A, B, C) = (1, 0, 0) will create oscillations in the circuit.
To prevent this, the tool breaks the loop and models it as a TIEX block in the feedback path which
results in coverage loss. Therefore such loops should be avoided.

7. Analog Blocks

Special handling is required for all analog blocks during testing when working with ATPG tools.
Many analog blocks can have embedded digital logic and we should ensure that all this logic is
testable. The digital inputs/outputs of the analog block interface needs to fully controllable and
observable. At the same time analog inputs/outputs should be wrapped or safe-stated. There can
be requirements based on test cases to keep analog portion of the block in a low power state
(power down or sleep), along with its analog outputs either in high impedance state or driving a
constant value, so special care needs to be taken care in such cases via safe stating of the block.

8. Voltage and Temperature Triggers Masking

SOC has voltage and temperature detection circuits built in them, to generate interrupts in case
either goes beyond the defined specification. During testing these signals need to be disabled or
masked, since there are multiple tests like Very Low Voltage (VLV) Test, High Voltage Stress Test,
etc., which will start showing fails if these interrupt signals are not masked.

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Figure 12: Analog Wrapper

9. Conclusion

It is very important to make our designs DFT-friendly. The simple practices above can save much
design time, effort, and frustration. Hence, it is recommended that designers ensure that all of the
above design practices are followed.

Also see :

– Design planning for large SoC implementation at 40nm: Guaranteeing

predictable schedule and first-pass silicon success <
http://www.edn.com/design/integrated-circuit-design/4413580/design-planning-
for-large-soc-implementation-at-40nm--guaranteeing-predictable-schedule-
and-first-pass-silicon-success>
– Product How To: DFT strategy for ARM processor-based designs <
http://www.edn.com/design/test-and-measurement/4405452/product-how-to--
dft-strategy-for-arm-processor-based-designs>
– SOC DFT verification with static analysis and formal methods <
http://www.edn.com/design/test-and-measurement/4388547/soc-dft-
verification-with-static-analysis-and-formal-methods>

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