1.

An architecture used in any

microcontroller is called
a)Harvard architecture
b) Von-Neumann architecture
c) Princeton architecture
d) both (a) and (c)
.2 . M o r e a d d r e s s p i n s , t h e m o r e m e m o r y
l o c a t i o n s a r e i n s i d e t h e c h i p . a) TRUE

b) FALSEc) Insufficient data d) None of these.3 . I f t h e r e i s

no data transfer in serial communication and
the line is high, it is
c a l l e d a) MARK b ) S TOP BITc) SP ACE d) STAR T
B IT. 4 . T h e t r a n s d u c e r m u s t b e c o n n e c t e d t o
signal conditioning circuit before it is sent to
the
ADC.
a) TRUE b) FALSEc) Insufficient data d) N
o n e o f t h e s e 5.Which of these are real-time
a p p l i c a t i o n s s c e n a r i o s ? I d e n t i f y . a) An on-line bus
ticketing system b) Printing of annual report of a companyc)
Reconciling a day's transaction in an account book of a small
companyd) An aircraft's yaw control system.6 . I d e n t i f y t h e
category of the following real-time systems as
“ h a r d , s o f t o r f i r m ” . a) An on-line celebrity cricket bat
auction b) A patient monitoring system in an ICUc) A library
book reservation systemd) A bank's credit card defaulters notice
generation program.7 . W h i c h o f t h e f o l l o w i n g
d e s c r i b e t h e R O T S d e s i g n p h i l o s o p h y b e s t ? a)
Maximize the throughput of the system b) Maximize the
processor utilizationc) Maximizing the response timed)
Response within certain stipulated time period.8 . W h i c h o f
the following are commercially claimed
RTOSs ?a ) L i n u x b ) W i n d o w s
C E c ) W i n d o w s N T d ) V x
w o r k s e ) S u n S o l a r i s .
Embeded System Solved MCQs
Question Answers
Embedded System Solved MCQs Question Answers
1. Which one of the following are header files?
A. proc()
B. truct()
C. files
D. #include
Answer - Click Here:
D
2. The standard C compiler used for the UNIX systems…
A. cc
B. sc
C. simulator
D. compiler
Answer - Click Here:
A
3. Which type of non-privileged processor mode is entered
due to the raising of the high priority of an interrupt?
A. Supervisor Mode (SVC)
B. Interrupt Mode (IRQ)
C. Fast Interrupt Mode (FIQ)

D. User mode
Answer - Click Here:
C
4. Where the Abort mode generally enters when _______?
A. undefined instructions are to be handled
B. ARM processor is on rest
C. low priority interrupt is raised
D. an attempt access memory fails
Answer - Click Here:
D
5. Which one of the following is also called a loader?
A. linker
B. locater
C. compiler
D. assembler
Answer - Click Here:
A
6. Mention that which one of the following gives the final
control to the programmer..?
A. linker
B. compiler
C. locater
D. simulator
Answer - Click Here:
A
7. Which assembler option is used to turn off long or short
address optimization?
A. -m
B. -o
C. -n
D. -V
Answer - Click Here:
B
8. Which of the following allows the reuse of the software and
the hardware components…?
A. peripheral design
B. input design
C. platform-based design
D. memory design
Answer - Click Here:
C
9. Embedded systems applications typically involve
processing information as ________
A. Distance
B. Signals
C. Block level
D. Logical volumes
Answer - Click Here:
A
10. The following is the design in which both the hardware
and software are considered during the design.
A. software/hardware codesign
B. peripheral design
C. platform-based design
D. memory based design
Answer - Click Here:
A
11. API stands for __________?
A. accessing peripheral through an interface
B. address programming interface
C. address programming interface
D. application programming interface
Answer - Click Here:
C
12. The loops are interchangeable, in which design activity…?
A. hardware/software partitioning
B. high-level transformation
C. scheduling
D. compilation
Answer - Click Here:
B

An architecture used in any microcontroller is calleda)Harvard architecture b) Von-.١

Neumann architecturec) Princeton architecture d) both (a) and (c).2.More address
pins, the more memory locations are inside the chip.a) TRUE b) FALSEc)
Insufficient data d) None of these.3. If there is no data transfer in serial
communication and the line is high, it is calleda) MARK b) STOP BITc) SPACE d)
START BIT.4.The transducer must be connected to signal conditioning circuit before
it is sent to the ADC.a) TRUE b) FALSEc) Insufficient data d) None of these5.Which
of these are real-time applications scenarios? Identify.a) An on-line bus ticketing
system b) Printing of annual report of a companyc) Reconciling a day's transaction in
an account book of a small companyd) An aircraft's yaw control system.6.Identify the
category of the following real-time systems as “hard, soft or firm”.a) An on-line
celebrity cricket bat auction b) A patient monitoring system in an ICUc) A library
book reservation systemd) A bank's credit card defaulters notice generation
program.7. Which of the following describe the ROTS design philosophy best ?a)
Maximize the throughput of the system b) Maximize the processor utilizationc)
Maximizing the response timed) Response within certain stipulated time period.8.
Which of the following are commercially claimed RTOSs ?a) Linuxb) Windows CEc)
Windows NTd) Vx works e) Sun Solaris.9.The device ‘Touch screen’ can be used
asa) input device b) output devicec) both input and output device d) none of these.10.
Which one of the following scheduling algorithm checks the rate of occurrence of the
task ?a) RAM b) EDFc) Co-operative d) All of these.11. Which of the following has
the highest “storage performance” ?a) DRAM b) SRAMc) OTP ROM d) Masked
.ROM
12.Cyclic scheduling is best for which of the following
task
?a) Aperiodic b) Sporadicc) Periodic d) None of these.1 3
. P O S I X i s a n e x a m p l e o f a) Application Software b) Tra
ditional Operation Systemc) Real Time Operating System d) None of these.1 4 . W h i
ch software architecture is the most Complex
?a ) R o u n d r o b i n b )
R o u n d r o b i n w i t h i n
t e r r u p t c) Functional queue scheduling d) RTOS.1 5 . T h e
m a i n f u n c t i o n o f R T O S i s a) real time task scheduling and
interrupt latency control b) process managementc) device managementd) memory
management.1 6 . W h i c h o f t h e f o l l o w i n g d e v i c e i s
not an embedded system ?a ) C e l l -
p h o n e b ) M a i n f r a m e c ) M o d e m d ) A u t o m
o b i l e . 17. Automobile engine control system is the
example of a ) s o f t r e a l t i m e b ) h a r d r e a l t i m e c ) f i r m r
eal time d) none of these.18.Which of the following
is volatile memory
?a ) E E P R O M b ) S R A M c ) N V -
R A M d ) F l a s h m e m o r y E P R O
M . 19.A microcontroller unit must
havea) oscillator and reset circuitsb) oscillator,
reset, watchdog
and linear circuitsc ) o s c i l l a t o r c i r c u i t
s d ) e x t e r n a l m e m o r y i n t e r f a c i n g
c i r c u i t s . 20. A program that combines object code files
into an executable program is called
a/ana ) c o m p i l e r b ) l i n k e r c ) l o a d e r d ) a s s e m b l
er.2 1 . I
2
C bus stands
for a ) i n t r a I C c o n n e c t b u s b ) i n t e r f a c e I C c o n
nect busc ) i n t e r I C c o n n e c t b u s d ) n o n e
o f t h e s e . 22.The number of bit of microcontroller in sophist
icated
em bedded s ys t em is a ) 8 o r 1 6 b ) 1 6 o r 3 2 c ) 3 2 o r 6 4 d ) n
one of these.23. MAC unit is present in which type
of processor
? a) ARM processor b) DSP processorc) ASIP processor d)
None of these.24. In distributed embedded controller
w h i c h t y p e o f b u s i s used
?a ) C A N b u s b ) I 2 C b u s c ) U S B b u s d ) N o n e o f t h e s e .

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25.Architecture used in DSP processor isa) Von Neu

mann b) Harvard architecturec) SIMD d) All of t
hese.2 6 . L e t
h
be the hit rate,
M
be the miss penalty,
C
be the time to access information in the cache.The average access time
experienced by the processor isa)
t avg
=(1–
h
)
C
+(1–
h
)
M
b)
t avg
=
hC
+(1–
h
)
M
c)
t avg
=(1–
h
)
C
+
hM
d)
t avg
=
hC
+
h M.27.
Which of the following has highest storage performance
?a ) D R A M b ) S R A M c ) O T P R O M d ) M a s k e d R O
M . 28.Which one of the following scheduling algorithms checks
the rate of occurrence of the task
?a ) D M A b ) E D F c ) C o -
o p e r a t i v e d ) A l l o f t h e s e . 29.8051 is a
............... bit
microcontroller.a ) 1 6 b ) 8 c ) 3 2 d
) N o n e o f t h e s e . 30.Which of the
following is commercially claimed RTOSS
?a ) L i n u x b ) W i n d o w s c ) W
i n d o w N T d ) V X W o r k s . 31.A
s m a l l s c a l e e m b e d d e d s ys t e m i s d e s i g n e d w i t h . . . . . . . . . . . b i t
microcontroller.a ) 8 b ) 1 6 c ) 3 2
d ) 8 o r 1 6 . 32.Which is
t h e h e a r t o f a n e m b e d d e d s y s t e m ? a) Interrupt controller b) Proce
ssor c) I/O devices d) power supply.3 3 . I n s u c c e s s i v e a p p r o x i m a t i o n
method conversion time is equal to .................... for 8-bit
s y s t e m running with 1 MHz
clock.a ) 8 μ s e c b ) 4 μ s e c c ) 1 μ s e c d ) n o n e o f t
h e s e . 34.A model in which there are finite states, which had
g i v e n a s e t o f i n p u t s o r s t a t e c h a n g e s according to the state transition
function,
isa ) F S M b ) A D F G c ) D F G d )
S t a t e t r a n s i t i o n f u n c t i
o n . 35. A program that conmbines object code files
into anexecutable program is called
aa ) C o m p i l e r b ) L i n k e r c ) L o a d e r d ) A s s e m b l e r . 3 6
.Which of the following is volatile memory
?a) EEPROM b) SRAMc) NV RAM d) Flash memor
y E P R O M . 37. Automobile engine control system is the
example of a ) s o f t r e a l s i m e b ) h a r d r e a l s i
m e c ) b o t h o f t h e s e d ) n o n e o f t h e s e .
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38.Which of the following devices is not an

embedded system ?a ) C e l l p h o n e b ) M a i n f r a m e c
) M o d e m d ) A u t o m o b i l e . 39.Which software
architecture is the most complex
?a ) R o u n d r o b i n b ) R
o u n d r o b i n w i t h i n t
e r r u p t c ) F u n c t i o n a l q u e u e
s c h e d u l i n g d )
R T O S . 4 0 . R e a l t i m e m e a n s a) actual time b) time
from start of task c) time measured using the system clock of RTOSd) time that has a
fixed unalterable zero reference in which a clock advances at constantinterval and
which cannot be reloaded.4 1 . A d e v i c e d r i v e r w o u l d o r d i n a r i l y
b e w r i t t e n i n a) machine language b) assembly languagec) a platform-
independent language such as JAVAd) an application-oriented language.4 2 . W h i c h
c h i p h a s a l a r g e n u m b e r o f a r r a ys w i t h e a c h e l e m e n t h a v i n g
fusible links ?a ) G P P b ) A S S P c ) F P G A d ) R e g
i s t e r . 43.An architecture used in any
microcontroller
isa ) H a r v a r d b ) V o n n e u m a n c ) P r i n c e t o n d ) b o
t h ( a ) a n d ( c ) . 44. Cyclic scheduling is best for which
of the following tasks
?a) Aperiodic b) Sporadicc) Periodic d) None of these.4 5
. R T O S i s o n e w h i c h a) allows flexible scheduling of the
system resource to several task b) controls task synchronizationc) is an operating
system for microcontroller d) is an operating system for pre-emptive
scheduling.4 6 . M o r e a d d r e s s p i n s , t h e m o r e m e m o r y l o c a t i o n s
areinside the chip. It
isa ) T r u e b ) F a l s e c ) I n s u f f i c i e n t d a t a d ) N o n
e o f t h e s e . 47.If there is no data transfer in serial
communication and the line is high, it is
calleda ) M A R K b ) S T O P B I T c ) S P A C E
d ) S T A R T B I T . 48.The transducer must be
connected to signalconditioning circuit before it is sent
to the
ADC
.a ) T r u e b ) F a l s e c ) I n s u f f i c i e n t d a t a d ) N o n e
o f t h e s e . 49. A powerful modeling language which
i s e x t e n s i v e l y u s e d i n t h e s o f t w a r e d e v e l o p m e n t p r o c e s s , specially
designed for

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a ) U M L b ) C c ) S M I d ) J A V A . 50.Address
lines requires for 32 k-
byte memory chip isa ) 1 3 b ) 1 4 c
) 1 5 d ) 1 6 . 5 1 . E E P R O M
i s a) flash also b) for erase at a time of one byte and flash for a sector of bytec)
different from flashd) works identically for erase as well as write.5 2 . T h e
t e r m h a n d - s h a k i n g i s u s e d i n a) interrupt data transfer scheme b)
DMA data transfer schemec) synchronous data transfer schemed) asynchronous data
transfer scheme.5 3 . W h i c h c h i p h a s a l a r g e n u m b e r o f a r r a ys
with each element having
fusible links ?a ) G P P b ) A S S
P c ) F P G A d ) R e g i s
t e r . 5 4 . T h e m a i n f u n c t i o n o f R T O S i s a)
Real time task scheduling and interrupt latency control b) Device managementc)
Process managementd) Memory management.5 5 . W h i c h o n e o f t h e f o l l o w i n g
is used as an additional processing unit for running the
a p p l i c a t i o n specific tasks in place of processing using embedded software
?a ) M i c r o -
c o n t r o l l e r b ) D S P c )
F P G A d )
A S S P . 56.Which of
the following has the highest "storage performance"
?a ) D R A M b ) S R A M c ) O T P R O M d ) M a s k e d R
O M . 57.Which of the following are commercially claimed
RTOSs ?a ) L i n u s b ) W i n d o w s C E c ) W i n d o w s N T d )
S u n S o l a r i s . 58.Which of the following scheduling
algorithms checks the rate of occurrence of the
task ?a ) D M A b ) E D F c ) C o -
o p e r a t i v e d ) A l l o f t h e s e .
59.Which is
the heart of an embedded system ?a ) I n t e r
r u p t c o n t r o l l e r b ) P r o c
e s s o r c) I/O devices d) Power supply.6 0 . A m o d e l i n w h i c h
there are finite states, which have given assets of inputs, or state
c h a n g e s according to the state transition function is

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a ) F S M b ) A D F G c )
D F G d ) U M L 61.A small scale
em bedded s ys t em is desi gned wit h ........... bit mi cro-
controller.a ) 8 b ) 8 o r 1
6 c ) 3 2 d ) 6 4 . 62.DMA
modules can communicate with CPU
t h r o u g h a) interrupt b) cycle stealingc) branch instruction d) none of these.6 3
. O b j e c t c o d e i s a ) i n p u t o f a s s e m
b l e r b ) o u t p u t o f a s s e m b l e r c ) i n t e r
m e d i a t e c o d e d ) n o n e o f t h e s e . 64.
A CPU has 16 bit program counter. This
means CPU can have ............ address
m e m o r y locations.a ) 1 6 K b ) 3 2
K c ) 6 4 K d ) 2 5 6 K . 6
5.How many layers are there in an embedded system
design?a ) 0 2 b
) 0 3 c ) 0
4 d ) 0 5 66.Architectu
re used in 8051 microontroller is?A ) S I M D b
) H a r v a r d c ) v o n -
N e u m a n n d ) M I S D 67.In embedded
system design, actuator acts
as a/ana ) i n p u t d e v i c e b ) o u t p u t d
e v i c e c ) m e m o r y d e v i c e d ) b o t h
a ) a n d b ) 68.which one is a serial synchronous
communication
protocol?a ) R S 2 3 2 b )
U S B c ) P C I d )
I
2
C6 9 . w h i c h o n e o f t h e f o l l o w i n g i s a n
RTOS?a ) w i n d o w s N T b ) U n
i x c ) U b u n t u d ) W i n d o s
C E 7 0 . G - s e n s o r i s u s e d t o
s e n s e a ) P o s i t i o n b ) p r e s s u r e c ) A c c e l
e r a t i o n d ) G r a v i t a t i o n a l F o r c e 71.A
program that combine object code files into
an executable program is called
aa ) C o m p i l e r b ) l i n k e r c ) b o t h
 a ) a n d b ) d ) n o n e o f t h e s e 7 2
. a r o b o t i c a r m i s a a ) H a r d r e a l t i
m e s y s t e m b ) s o f t r e a l t i m e s y s
t e m c ) d i s c r e e t s y s t e
m d ) f e e d b a c k s y s t e m
7 3 . A t h r e a d i s a a ) H e a v y w e i g
h t p r o c e s s b ) l i g h t w e i g h t p r o c
e s s

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1. Which memory storage is widely used in PCs and Embedded Systems?

a) EEPROM
b) Flash memory
c) SRAM
d) DRAM
View Answer
Answer: d
Explanation: DRAM is used in PCs and Embedded systems because of its low
cost. SRAM, flash memory and EEPROM are more costly than DRAM.
2. How is the protection and security for an embedded system made?
a) Security chips
b) Memory disk security
c) IPR
d) OTP
View Answer
Answer: c
Explanation: Intellectual property right provides security and protection to
embedded systems.
3. Which of the following task swapping method is a better choice in the
embedded systems design?
a) time slice
b) RMS
c) cooperative multitasking
d) pre-emptive
View Answer
Answer: d
Explanation: The pre-emptive method of task swapping is the first choice for
embedded system design because of its better system response.
4. Which type of memory is suitable for low volume production of embedded
systems?
a) Non-volatile
b) RAM
c) Volatile
d) ROM
View Answer
Answer: a
Explanation: The devices which use non-volatile memory allow the software to be
download and returned in the device. UV erasable EPROM is favorable but
EEPROM is also gaining favor. Therefore, this type of memory is used in low
volume production.
5. Which activity is concerned with identifying the task at the final embedded
systems?
a) scheduling
b) task-level concurrency management
c) high-level transformation
d) compilation
View Answer
Answer: b
Explanation: There are many design activities associated with the platforms in the
embedded system and one such is the task-level concurrency management
which helps in identifying the task that needed to be present in the final
embedded systems.
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6. Which level simulates the algorithms that are used within the embedded
systems?
a) algorithmic level
b) switch level
c) gate level
d) circuit level
View Answer
Answer: a
Explanation: The algorithmic level simulates the algorithm which is used within in
the embedded system.
7. How an embedded system communicate with the outside world?
a) Memory
b) Output
c) Peripherals
d) Input
View Answer
Answer: c
Explanation: The system communicates with the outside world through
peripherals.
8. Which of the following helps in reducing the energy consumption of the
embedded system?
a) emulator
b) debugger
c) simulator
d) compilers
View Answer
Answer: d
Explanation: The compilers can reduce the energy consumption of the embedded
system and the compilers performing the energy optimizations are available.
9. What is the purpose of memory refresh register of Z80?
a) To control on-chip SRAM
b) To control on-chip DRAM
c) To clear cache
d) To control ROM
View Answer
Answer: b
Explanation: In addition to the general purpose registers, a stack pointer,
program counter, and two index registers are included in Z80. It was also used in
many embedded designs because of its high-quality performance and for its in-
built refresh circuitry for DRAMs.
10. What does MESI stand for?
a) modified exclusive system input
b) modifies embedded shared invalid
c) modified exclusive shared invalid
d) modified exclusive stale invalid
View Answer
Answer: c
Explanation: The MESI protocol supports a shared state which is a formal
mechanism for controlling the cache coherency by using the bus snooping
techniques. MESI refers to the states that cached data can access. In MESI
protocol, multiple processors can cache shared data.
11. Which of the following is the pin efficient method of communicating between
other devices?
a) memory port
b) peripheral port
c) parallel port
d) serial port
View Answer
Answer: d
Explanation: The serial ports are considered to be the pin efficient method of
communication between other devices within an embedded system.
12. Which of the following is a traditional method for emulating the processor?
a) CPU simulator
b) SDS
c) ICE
d) Low-level language simulator
View Answer
Answer: c
Explanation: The SDS is one of the simulation tool used in the embedded
systems. CPU simulator and the low-level simulator are the other kinds of the
simulator used in the embedded system design.
13. Which of the following unit protects the memory?
a) memory management unit
b) peripheral unit
c) execution unit
d) bus interface unit
View Answer
Answer: a
Explanation: The resources have to be protected in an embedded system and the
most important resource to be protected is the memory which is protected by the
memory management unit through different programming.
14. Identify the standard software components that can be reused in an
embedded system design?
a) memory
b) application software
c) application manager
d) operating system
View Answer
Answer: d
Explanation: There are certain software components that can be reused in an
embedded system design. These are the operating systems, real-time databases
and some other forms of middleware.
15. What does ICE stand for?
a) in-circuit EPOM
b) in-code emulation
c) in-circuit emulation
d) in-code EPROM
View Answer
Answer: c
Explanation: The ICE or in-circuit emulation is one the traditional method used to
emulate the processor in the embedded system so that the software can be
downloaded and can be debugged in situ in the end application.
16. Who proposed the first power model?
a) Tiwari
b) Russell and Jacome
c) Russell
d) Jacome
View Answer
Answer: a
Explanation: Tiwari proposed the first power model in the year 1974. The model
includes the so-called bases and the inter-instruction instructions. Base costs of
the instruction correspond to the energy consumed per instruction execution
when an infinite sequence of that instruction is executed. Inter instruction costs
model the additional energy consumed by the processor if instructions change.
17. Which of the following offers external chips for memory and peripheral
interface circuits?
a) Embedded system
b) Peripheral system
c) Microcontroller
d) Microprocessor
View Answer
Answer: d
Explanation: Microcontrollers are the CPUs which have integrated memory and
peripherals whereas microprocessor offers external chips for memory.
18. What kind of socket does an external EPROM to plugged in for prototyping?
a) Piggyback reset socket
b) Multi-socket
c) Piggyback
d) Single socket
View Answer
Answer: c
Explanation: Some controllers use a special package called piggyback socket on
the top of the package to allow the EPROM for prototyping.
19. Which is the single device capable of providing prototyping support for a
range of microcontroller?
a) Umbrella device
b) OTP
c) RAM
d) ROM
View Answer
Answer: a
Explanation: Umbrella device is capable of providing prototyping support for a
range of microcontrollers.
20. By which instruction does the switching of registers take place?
a) Register instruction
b) EXX instruction
c) Instruction opcodes
d) AXX instruction
View Answer
Answer: c
Explanation: Only one set of registers can be used at one time and the switching
of registers and data transfer is performed by the EXX instruction.
21. Which of the architecture is more complex?
a) MC68040
b) MC68030
c) SPARC
d) 8086
View Answer
Answer: c
Explanation: SPARC have RISC architecture which has a simple instruction set
but MC68020, MC68030, 8086 have CISC architecture which is more complex
than CISC.
22. Which of the following statements are true for von Neumann architecture?
a) separate bus between the program memory and data memory
b) external bus for program memory and data memory
c) external bus for data memory only
d) shared bus between the program memory and data memory
View Answer
Answer: d
Explanation: von Neumann architecture shares bus between program memory
and data memory whereas Harvard architecture have a separate bus for program
memory and data memory.
23. What is approximate data access time of SRAM?
a) 2ns
b) 10ns
c) 60ns
d) 4ns
View Answer
Answer: d
Explanation: SRAM access data in approximately 4ns because of its flip-flop
arrangement of transistors whereas the data access time in DRAM is
approximately 60ns since it has a single capacitor for one-bit storage.
24. Which of the following is a plastic package used primarily for DRAM?
a) Zig-zag
b) DIMM
c) SIMM
d) Dual-in-line
View Answer
Answer: a
Explanation: Zig-zag package of memory is a plastic package used for DRAM.
The leads of this package are arranged in a zigzag manner.
25. Which of the following is the biggest challenge in the cache memory design?
a) coherency
b) memory access
c) size
d) delay
View Answer
Answer: a
Explanation: The coherency is a major challenge in designing the cache memory.
The cache has to be designed by solving the problem of data coherency while
remaining hardware and software compatible.
26. Which ports are used in the multi-master system to avoid errors?
a) bidirectional port
b) tridirectional port
c) multi directional port
d) unidirectional port
View Answer
Answer: a
Explanation: By using the bidirectional ports, each master can monitor the line
and confirm its expected state and if it is not matched, a mismatch or collision
had occurred which will discontinue the transmission by the master.
27. Which provides an input clock for the receiver part of the UART 8250?
a) DDIS
b) MR
c) RD
d) RCLK
View Answer
Answer: d
Explanation: RCLK provides an input clock for the receiver part of the UART. RD
is the read signal. MR is the master reset pin and DDIS is used to control bus
arbitration logic.
28. What does PCM stand for?
a) peculiar code modulation
b) pulse codec machine
c) pulse code modulation
d) peripheral code machine
View Answer
Answer: c
Explanation: The linear codec is also known as pulse code modulation which is
commonly used in the telecommunications industry.
29. Which of the following is the common method for connecting the peripheral to
the processor?
a) software
b) exception
c) external interrupts
d) internal interrupts
View Answer
Answer: c
Explanation: The common method for connecting the peripheral to the processor
is the external interrupts. The external interrupts are provided through the
external pins which are connected to the peripherals.
30. What allows the data protection in the software interrupt mechanism?
a) TRAP
b) SWI
c) Same mode
d) Different mode
View Answer
Answer: d
Explanation: The switching between user mode and supervisor mode provides
protection for the processor, that is, the different modes in the software interrupt
allows the memory and the associated code and data to be protected from each
other.
31. In which of the exceptions does the external event causes the exception?
a) precise
b) imprecise
c) asynchronous exception
d) synchronous exception
View Answer
Answer: c
Explanation: The asynchronous exception is the one in which an external event
causes an exception and is independent of the instruction flow. On the other
hand, the synchronous exceptions are synchronised, that is, it is caused by the
instruction flow.
32. Which interrupts generate fast interrupt exception?
a) software interrupt
b) hardware interrupt
c) internal interrupt
d) external interrupt
View Answer
Answer: d
Explanation: The external interrupts generates the fast interrupt routine exception
in which the external interrupt is synchronised with the processor clock.
33. Which task swap method works in a regular periodic point?
a) cooperative multitasking
b) schedule algorithm
c) pre-emption
d) time slice
View Answer
Answer: d
Explanation: The time slicing works by switching task in regular periodic points in
time, that is, any task that needs to run next will have to wait until the current time
slice is completed.
34. Which of the following is a part of RTOS kernel?
a) register
b) ISR
c) memory
d) input
View Answer
Answer: b
Explanation: The ISR can send the message for the tasks and it is a part of
RTOS kernel.
35. Which provides the TCP/IP communication over the ethernet and FDDI?
a) pNA+ network manager
b) pSOS+
c) pSOS+ kernel
d) pSOS+m
View Answer
Answer: a
Explanation: A pNA+ network manager is a networking option which can provide
the TCP/IP communication over a large variety of media such as the FDDI and
the ethernet.
36. What limits the amount of virtual memory in Windows 3.1?
a) static file
b) dynamic file
c) nature of swap file
d) size of the swap file
View Answer
Answer: d
Explanation: The swap file of Windows 3.1 have a size of 25 Mbytes and thus
limits the amount of virtual memory that it can support.
37. Which one of the following offers CPUs as integrated memory or peripheral
interfaces?
a) Memory system
b) Embedded system
c) Microcontroller
d) Microprocessor
View Answer
Answer: c
Explanation: Microcontrollers are the CPUs which have integrated memory and
peripherals but microprocessor possesses external chips for memory.
38. Which algorithm is based on Jackson’s rule?
a) EDF
b) LST
c) LL
d) EDD
View Answer
Answer: d
Explanation: The EDD or earliest due date is based on Jackson’s rule. The
Jackson’s rule states that for a given a set of n independent tasks, any algorithm
that executes the tasks in the order of nondecreasing deadlines is optimal with
respect to reducing the maximum lateness. EDF is the earliest deadline first, LL
is the least laxity and the LST is the least slack time first.
39. Which of the following does not have the ability to get hundred individual
signal cables into the probe in the emulation technique?
a) JTAG
b) ICE
c) BDM
d) OnCE
View Answer
Answer: b
Explanation: The in-circuit emulation does not have the ability to get a hundred
individual signal cables into the probe. This problem comes under the physical
limitation of the probe, that is as the density of the processor increases the
available sockets which provide good electrical contacts is becoming harder
which causes a restriction to the probe.
40. Which technique can solve the errors in the linear buffer?
a) low and high water mark
b) pointer
c) high water mark
d) low water mark
View Answer
Answer: a
Explanation: The errors in the linear buffering include the loss of data especially
during the regular sampling which can be avoided by the pointers that are
checked against certain values and this result is used for fetching more data.
These points are known as the low water mark and the high water mark.
41. Which buffering mechanism is common to the SPOX operating system?
a) directional buffer
b) linear buffer
c) single buffer
d) buffer exchange
View Answer
Answer: d
Explanation: The buffer exchange can support the SPOX operating system which
is used for the digital signal processors and it is easy to implement.

Embedded Systems Multiple Choice

Question
Using this Embedded Systems MCQ/Answers, you can crack your college viva/
entrance test and interview with the help of these selected questions.

1) Which design allows the reuse of the software and the hardware components?

a. Memory Design
b. Input design
c. Platform-based design
d. Peripheral design

Hide Answer Workspace

Answer: C [ Platform-based design ]

Description: The software and the hardware can be reused using the platform
design to cope with the increasing complexity in creating embedded systems.

2) Which design considers both the hardware and software during the embedded
design?

a. Memory Design
b. Software/ hardware codesign
c. Platform-based design
d. Peripheral design

Hide Answer Workspace

Answer: B [ Software/ hardware codesign ]

Description: It will consider both the hardware and software design concerns.
It helps in the right combination of the hardware and the software for the
efficient product.

3) What does API stand for?

a. Application Programming Interface

b. Address Programming Interface
c. Accessing peripheral through the interface
d. None of them

Hide Answer Workspace

Answer: A [ Application Programming Interface ]

Description: The API stands for Application Programming Interface. It helps in

extending the platform towards software applications.

4) Which design activity can be used for the mapping operation to hardware?

a. High-level transformation
b. Scheduling
c. Compilation
d. Hardware / Software partitioning

Hide Answer Workspace

Answer: D [ Hardware / Software partitioning ]

Description: The activity is in charge of mapping operations to the software or

the hardware.

5) Which process can be used in analyzing the set of possible designs?

a. Scheduling
b. Design space exploration
 c. Hardware / Software partitioning
d. Compilation

Hide Answer Workspace

Answer: B [ Design Space Exploration ]

Description: It is the process of analyzing the set of designs, and the method
which meets the specification is selected.

6) What does FRIDGE stand for?

a. the floating-point programming design environment

b. the fixed-point programming design environment
c. floating-point programming decoding
d. fixed-point programming decoding

Hide Answer Workspace

Answer: B [ Fixed-Point Programming Design Environment ]

Description: FRIDGE stands for Fixed-Point programming Design Environment,

which can be developed for the optimization programs.

7) Which of the following tool can replace floating-point arithmetic with fixed-point
arithmetic?

a. FAT
b. SDS
c. FRIDGE
d. VFAT

Hide Answer Workspace

Answer: C [ FRIDGE ]

Description: There are specific tools available for the optimization programs.
One such tool is the FRIDGE or fixed-point programming design environment,
commercially made available by Synopsys System Studio. This tool can be used
in the transformation program, converting floating-point arithmetic to fixed-
point arithmetic. This is widely used in signal processing.

8) Which of the following can reduce the loop overhead and thus increase the
speed?

a. loop tiling
b. Loop unrolling
c. loop fusion
d. loop permutation

Hide Answer Workspace

Answer: B [ Loop unrolling ]

Description: The loop unrolling can reduce the loop overhead, that is, the fewer
branches per execution of the loop body, which in turn increases the speed but
is only restricted to loops with an endless number of iteration. The unrolling can
improve the code size.

9) Which part of the COOL input comprises information about the available
hardware platform components?

a. design constraints
b. target technology
c. behavior
d. both behavior and design constraints

Hide Answer Workspace

Answer: B [ Target Technology ]

Description: The codesign tool consists of three input ports described as target
technology, design constraints, and behavior. Each input does different
functions. The target technology comprises information about the various
hardware platform components available within the system.
10) What does Index set L denotes?

a. task graph node

b. processor
c. hardware components
d. task graph node type

Hide Answer Workspace

Answer: D [ Task Graph Node Type ]

Description: The index set is used in the IP or the integer programming model.
The Index set KP denotes the processor, I represent the task graph nodes, and
L means the task graph node type.

11) Which design can be used to reduce the energy consumption of the embedded
system?

a. Simulator
b. Compiler
c. Emulator
d. Debugger

Hide Answer Workspace

Answer: B [ Compiler ]

Description: The compiler can be used to reduce the energy consumption of

the embedded system. It performs the available energy optimizations.

12) What is the main ingredient for power optimization?

a. Power Model
b. Energy Model
c. Power Compiler
d. Watt Model

Hide Answer Workspace

Answer: A [ Power Model ]

Description: You can save energy at any stage of the embedded system
development. High-level optimization techniques can reduce power
consumption. Similarly, compiler optimization can also reduce power
consumption, and the essential thing in power optimization is the power model.

13) Who proposed the first power model?

a. Russell
b. Jacome
c. Russel and Jacome
d. Tiwari

Hide Answer Workspace

Answer: D [Tiwari]

Description: Tiwari proposed the first power model in the year 1974. The model
includes the so-called bases and the inter-instruction instructions. The
education's base costs correspond to the energy consumed per instruction
execution when an infinite sequence of that instruction is executed. Inter
instruction costs model the additional power consumed by the processor if
instructions change.

14) Which model is based on precise measurements using real hardware?

a. First power model

b. Encc energy-aware compiler
c. Second Power Model
d. Third power model

Hide Answer Workspace

Answer: encc energy-aware compiler

Description: The enccenergy-aware compiler uses the energy model by Steinke

et al. it is based on the actual hardware's precise measurements. The power
consumption of the memory, as well as the processor, is included in this model.
15) How can one compute the power consumption of the cache?

a. First power model

b. Lee power model
c. CACTI
d. Third power model

Hide Answer Workspace

Answer: C [ CACTI ]

Description: The CACTI can compute the cache's power consumption, which
Wilton and Jouppi proposed in 1996.

16) Which of the following function can interpret data in the C language?

a. Scanf
b. Printf
c. File
d. Proc

Hide Answer Workspace

Answer: A [ Scanf ]

Description: The scanf and printf are the C language functions used to interpret
data and print data.

17) Which statement replaces all occurrences of the identifier with string?

a. # include
b. # define identifier string
c. # ifdef
d. # define MACRO()
Hide Answer Workspace

Answer: B [ #define identifier string ]

Description: # define statement can replace all occurrences of the identifier

with string. Similarly, it can determine the constants, which also makes the code
easier to understand.

18) Which of the following is also known as loader?

a. Linker
b. Locator
c. Assembler
d. Compiler

Hide Answer Workspace

Answer: A [ Linker ]

Description: The linker is also known as a loader. It can take the object file and
searches the library files to find the routine it calls.

19) Which command takes the object file and searches library files to find the
routine calls?

a. Emulator
b. Simulator
c. Linker
d. Debugger

Hide Answer Workspace

Answer: C [ Linker ]

Description: The linker is also known as a loader. It can take the object file and
searches the library files to find the routine it calls. The linker can give the
programmer the final control concerning how unresolved references are
reconciled, where the sections are located in the memory, which routines are
used, etc.
20) Which of the following language can describe the hardware?

a. C++
b. C
c. VHDL
d. JAVA

Hide Answer Workspace

Answer: C [ VHDL ]

Description: The VHDL is the hardware description language that describes the
hardware, whereas C, C++, and JAVA are software languages.

21) Which simulator/ debugger is capable of displaying output signal waveform

resulting from stimuli applied to the inputs?

a. VHDL emulator
b. VHDL simulator
c. VHDL locator
d. VHDL debugger

Hide Answer Workspace

Answer: B [ VHDL Simulator ]

Description: The VHDL simulator can display the output signal waveforms that
result from the stimuli or trigger applied to the input.

22) What describes the connections between the entity port and the local
component?

a. One-to-one map
b. Many-to-one map
c. One-to-many maps
d. Port map
Hide Answer Workspace

Answer: D [ Port map ]

Description: The port map describes the connection between the entity port
and the local component. The component is declared by component
declaration, and the entity ports are mapped with the port mapping.

23) Which of the following is an abstraction of the signal impedance?

a. Strength
b. Nature
c. Size
d. Level

Hide Answer Workspace

Answer: D [ Size ]

Description: Most of the systems contain electrical signals of different

strengths and levels. The signal's level is the abstraction of the signal voltage,
and the power is the abstraction of the signal impedance.

24) How many types of wait statements are available in the VHDL design?

a. 4
b. 3
c. 6
d. 5

Hide Answer Workspace

Answer: A [ 4 ]

Description: There are four kinds of wait statements. These are waiting on, wait
for, wait until and wait.
25) Which of the following is a C++ class library?

a. C
b. JAVA
c. SystemC
d. C++

Hide Answer Workspace

Answer: C [ SystemC ]

Description: System C is a C++ class library that helps solve behavioral,

resolution, simulation time problems.

26) Which C++ class is similar to the hardware description language like VHDL?

a. Verilog
b. C
c. JAVA
d. SystemC

Hide Answer Workspace

Answer: D [ SystemC ]

Description: SystemC is a C++ class similar to the hardware description

languages like VHDL and Verilog. The execution and simulation time in the
SystemC is almost identical to the VHDL.

27) Which of the following is standardized as IEEE 1364?

a. C++
b. C
c. Verilog
d. FORTRAN

Hide Answer Workspace

Answer: C [ Verilog ]

Description: It is a hardware description language. Verilog was developed for

modeling hardware and electronic devices. It is then standardized by the IEEE
standard 1364.

28) Which of the following is an analog extension of the VHDL?

a. System VHDL
b. VHDL-AMS
c. System Verilog
d. Verilog

Hide Answer Workspace

Answer: B [ VHDL-AMS ]

Description: The extension of the VHDL includes the analog and mixed
behavior of the signals.

29) Which level simulates the algorithms that are used within the embedded
systems?

a. Circuit Level
b. Gate Level
c. Algorithmic Level
d. Switch Level

Hide Answer Workspace

Answer: Algorithmic Level

Description: It simulates the algorithm which is used within the embedded

system.

30) Which of the following models the components like resistors, capacitors, etc.?

a. Layout model
 b. Register-transfer level
c. Switch-level model
d. Circuit level model

Hide Answer Workspace

Answer: D [ Circuit level model ]

Description: This simulation can be used for the circuit theory and its
components such as the resistors, inductors, capacitors, voltage sources, current
sources. This simulation also involves partial differential equations.

31) Which models communicate between the components?

a. fine-grained modeling
b. transaction level modeling
c. circuit-level model
d. coarse-grained modeling

Hide Answer Workspace

Answer: B [ Transaction level modeling ]

Description: The transaction-level modeling is a type of instruction set level

model. This modeling helps in the modeling of components which is used for
the communication purpose. It also models the transaction, such as read and
writes cycles.

32) Which model is used to denote the Boolean functions?

a. gate-level model
b. switch level
c. layout model
d. circuit level

Hide Answer Workspace

Answer: A [ Gate Level model ]

Description: The gate-level model is used to denote the boolean functions, and
the simulation only considers the gate's behavior.

33) n which model, the effect of instruction is simulated, and their timing is not
considered?

a. circuit model
b. gate-level model
c. layout model
d. coarse-grained model

Hide Answer Workspace

Answer: D [ coarse-grained model ]

Description: The coarse-grained model is a kind of instruction set level

modeling in which only the effect of instruction is simulated, and the timing is
not considered. The information which is provided in the manual is sufficient
for this type of modeling.

34) Which of the following is a set of specially selected input patterns?

a. debugger pattern
b. test pattern
c. byte pattern
d. bit pattern

Hide Answer Workspace

Answer: B [ Test pattern ]

Description: While testing any devices or embedded systems, we apply some

selected inputs known as the test pattern and observe the output. This output
is compared with the expected outcome. The test patterns usually are used in
the already manufactured systems.

35) Which of the following have flip-flops which are connected to form shift
registers?
a. test pattern
b. scan design
c. CRC
d. bit pattern

Hide Answer Workspace

Answer: B [ Scan Design ]

Description: All the flip-flop storing states are connected to form a shift
register in the scan design. It is a kind of test path.

36) Which gate is used in the geometrical representation if a single event causes
hazards?

a. NOT
b. OR
c. AND
d. NAND

Hide Answer Workspace

Answer: B [ OR ]

Description: The fault tree analysis is done graphically using gates, mainly AND
gates and OR gates. The OR gate is used to represent a single event that is
hazardous. Similarly, AND gates are used in the graphical representation if
several events cause hazards.

37) Which of the following can compute the exact number of clock cycles required
to run an application?

a. coarse-grained model
b. layout model
c. register-transaction model
d. fine-grained model

Hide Answer Workspace

Answer: D [ fine-grained model ]

Description: The fine-grained model has the cycle-true instruction set

simulation. In this modeling, it is possible to compute the exact number of clock
cycles required to run an application.

38) Which of the following is possible to locate errors in the specification of the
future bus protocol?

a. HOL
b. EMC
c. FOL
d. BDD

Hide Answer Workspace

Answer: D [ BDD ]

Description: The model checking was developed using the binary decision
diagram and the BDD, and it was possible to locate errors in the specification
of the future bus protocol.

39) What is CTL?

a. code tree logic

b. CPU tree logic
c. computer tree logic
d. computational tree logic

Hide Answer Workspace

Answer: D [Computational tree logic ]

Description: The EMC-system is a popular system for model checking

developed by Clark that describes the CTL formulas, also known as
computational tree logic. The CTL consist of two parts, a path quantifier and a
state quantifier.
40) Which is a top-down method of analyzing risks?

a. FMEA
b. FTA
c. Damages
d. Hazards

Hide Answer Workspace

Answer: B [ FTA ]

Description: The FTA is Fault tree analysis which is a top-down method of

analyzing risks. It starts with damage and comes up with the reasons for the
damage. The research is done graphically by using gates.

41) Which of the following microprocessor is designed by Zilog?

a. Zigbee
b. Z80
c. 8087
d. 80386

Hide Answer Workspace

Answer: B [ Z80 ]

Description: Designed by Zilog in 1976. 80386 and 8087 are the processors
designed by Intel, and Zigbee is IEEE based, which is used for high-level
communication protocol.

42) How an alternate set of the register can be identified in Z80?

a. 'Prefix
b. 'Suffix
c. , prefix
d. , suffix

Hide Answer Workspace

Answer: B [ 'Suffix ]

Description: To identify the main register and alternate register ' is used in the
suffix.

43) What is the purpose of the memory refresh register of Z80?

a. To control on-chip SRAM

b. To control on-chip DRAM
c. To clear cache
d. To control ROM

Hide Answer Workspace

Answer: B [ To control on-chip SRAM ]

Description: In addition to the general-purpose registers, a stack pointer,

program counter, and two index registers are included in Z80. It was also used
in many embedded designs because of its high-quality performance and its in-
built refresh circuitry for DRAMs.

44) Which signal is used to differentiates the access from a standard memory cycle?

a. RESET
b. HALT
c. IORQ
d. MREQ

Hide Answer Workspace

Answer: C [ IORQ ]

Description: The IORQ signal is used to differentiate the access from a standard
memory cycle. These input/output accesses are similar from a hardware
perspective to a memory cycle but only occur when an input/output port
instruction is executed.
45) What supports multitasking in 80386?

a. External paging memory management unit

b. Read mode
c. On-chip paging memory management unit
d. Paging and segmentation

Hide Answer Workspace

Answer: C [ On-chip paging memory management unit ]

Description: Because of the efficient paging mechanism of 80386 in the

memory management unit, it supports multitasking. That is, different tasks can
be done at a time, a kind of parallel port.

46) Which one of the following is the successor of the 8086 and 8088 processor?

a. 80387
b. 80286
c. 8087
d. 8051

Hide Answer Workspace

Answer: B [ 80286 ]

Description: 80286 is the successor of 8086 and 8088 because it possesses a

CPU based on 8086 and 8088. 8051 is a microcontroller designed by Intel which
is commonly known as Intel MCS-51. 8087 is the first floating-point coprocessor
of 8086.

47) Which are the two modes of 80286?

a. Mode1 and mode2

b. Mode A and mode B
c. Real mode and protected mode
d. Alternate and main
Hide Answer Workspace

Answer: C [ Real mode and protected mode ]

Description: It possesses two modes which are called fundamental and

protected methods. In natural ways, it adds some additional register to access
a size greater than 16MB but still preserves its compatibility with 8086 and 8088.

48) When is the register set gets expanded in 80286?

a. In expanded mode
b. Interrupt mode
c. In real mode
d. In protected mode

Hide Answer Workspace

Answer: D [ In protected mode ]

Description: In protected mode, two additional register instances are called

index register and base pointer register, which helps expand the register.

49) Which of the following processors can perform exponential, logarithmic, and
trigonometric functions?

a. 8087
b. 8088
c. 8086
d. 8080

Hide Answer Workspace

Answer: A [ 8087 ]

Description: 8087 is a coprocessor that can perform all the mathematical

functions, including addition, subtraction, multiplication, division, exponential,
logarithmic, trigonometric, etc. 8086, 8080, and 8088 are microprocessors that
require the help of a coprocessor for floating-point arithmetic.
50) How are negative numbers stored in a coprocessor?

a. Decimal
b. Gray
c. 1's complement
d. 2's complement

Hide Answer Workspace

Answer: D [ 2's complement ]

Description: In a coprocessor, negative numbers are stored in 2's complement

with its leftmost sign bit of 1, whereas positive numbers are stored in the form
of actual value with its leftmost sign bit of 0.