ECE 2144- ANALOG CIRCUIT LAB

LAB MANUAL
 INSTRUCTION TO THE STUDENTS

Pre-lab Preparation

 All the students are requested to respect the lab timing.

 Each lab experiment requires the preparation that may involve a significant amount of work.
 The pre-lab work must be completed before arrival at the lab. The pre-lab work will be part
of your lab grade and will be evaluated every week.
 The student must revise concepts related to Logic design, Verilog Programming and VLSI
Design before coming to VLSI Lab.
Lab Journal
The students have to maintain Lab Journals and need to submit the same to the faculty at the start
of each lab. Each experiment must be written neatly and include the following details as
applicable
 Experiment Number and Date
 Experiment Title and Objective
 Verilog constructs used (Up to Experiment No. 4)
 Truth table, Logic equation and circuit diagram for combinational circuits (exercise problems
only)
 State diagram/ state table and circuit diagram for sequential circuits ( exercise problems only)
 Verilog code for each exercise problem.
 Simulation results and analysis
 Conclusion(s)
 Solution to additional assignment problems if any given by faculty
 Example of journal is given in the figure below
 Daily Evaluation

 Maintain neat lab journal: 03 Marks

 Conduction (solved examples) and complete involvement in the lab: 03 Marks
 Conduction of all the exercise problems & able to explain: 04 Marks

Regarding missing labs

1. The student is not allowed to miss more than two labs. For two labs, absence with the
valid reason they will be evaluated out of 10 otherwise 6 Marks. For rest absence (if the
students miss more than two lab sessions) 0 marks will be awarded. In either of the case,
the students must repeat the experiments which they have missed. If the students have
not repeated or completed all the experiments, they will be detained and will not be
eligible for the lab end exam.
2. To repeat the lab student should get prior permission by writing the letter and getting
approved through lab coordinators with supporting documents (Faculty, please update
the absentee marks on the same day).
3. Repetition of experiments is subject to availability of free systems in the lab.
 Experiment No. 1:
MOSFET and OPAMP characteristics

Objective:
To study the drain and transfer characteristics and effect of body bias in transistor using LTspice.

Components & Equipment:

Computer, LTspice software

Theory:

Study of nMOS and pMOS

An nMOS transistor is a 4 terminal device containing source, drain, gate and a substrate. Two n
layers are diffused into a P substrate. And the space between is overlapped by poly silicon. The
source is connected to ground and so is the substrate. We increase the gate voltage until Vth after
which a channel is formed below the gate. The channel becomes stronger as we increase V gs
from here and is determined by the overdrive voltage given by V ov=Vgs-Vth. At a constant Vds, the
transconductance characteristics is shown below.

Fig. 1.1 (i) nMOS (ii) Output characteristics of nMOS

Here, the MOSFET operates in linear region and acts as a resistor. If we increase V ds, at
Vds=Vgs-Vth, the voltage near drain becomes zero and there is no channel formation. If we
increase the voltage then pinch-off occurs at the drain and the current remains constant for any
further increase in the Vds voltage.
The output current Ids is given by the equation–
Ids = 0 ; Vgs=0
Ids = β {(Vgs-Vth)Vds - Vds2}; Vds<Vgs-Vth
Ids=(β/2)(Vgs-Vth)2; Vds>Vgs-Vth

Introduction to LTSpice tool:

SPICE (Simulation Program with Integrated Circuit Emphasis) is a general-purpose, open source
analog electronic circuit simulator. It is a program used in integrated circuit and board-level
design to check the integrity of circuit designs and to predict circuit behavior.

LTspice is a high-performance SPICE simulator, schematic capture and waveform viewer with
enhancements and models for easing the simulation of switching regulators. The enhancements
to SPICE have made simulating switching regulators extremely fast compared to normal SPICE
simulators, allowing the user to view waveforms for most switching regulators in just a few
minutes. Included in this download are LTspice, Macro Models for majority of Linear
Technology's switching regulators, over 200 op amp models, as well as resistors, transistors and
MOSFET models.

LTspice can run simulations on either schematic files or coded netlist files. Both methods are
quite similar, and only simulations with schematic files are introduced in detail here.

Example 1.1 Draw the Id versus Vgs characteristic curve of nmos transistor using LTSpice
Step 1: Install LTspice and open the software (Click No if requested update).
Current version: LTspice XVII.

Fig. 1.2 Schematic of editor

Step 2:

2.1 Create a new schematic.

2.2 Open an existing schematic file.

Fig. 1.3 Schematic editor

Step 3: Add/Modify/Delete electrical components into the schematic.

Path – Edit > component or press ‘F2’

Shortcut keys and buttons; zoom in/out or rotate components if needed. Also available to view in
“Control Panel”.

Fig. 1.4 Schematic editor with edit

 Fig. 1.5 Schematic editor with multiple icons

Most commonly used shortcuts are as follows:

<F5>delete
<F6> copy
<F7> move component without wires attached
<F8>move components with wires attached
<F9> undo
shift<F9> redo
<CTRL R> rotates component (once it has been selected using <F7>)
<CTRL E> mirrors component (once it has been selected using <F7>)

Fig. 1.6 Schematic editor with multiple tool bar

Step 4: Add components from the library and place them at proper positions. Components will
be placed where you left click the mouse, until you press “ESC” to stop placing that component.

Fig. 1.7 Editor window

Step 5: Add wires (click and release) to connect all components to create the complete
circuit/schematic.

Fig. 1.8 Circuit diagram

 Step 6: Right click on the components and change their values, as given in circuit diagram
above. Write command “.include cmosedu_models.txt” and paste in the editor window near to
the circuit diagram.

Step 7: “Run” the simulation

a. In the Edit Simulation Command window, select DC Sweep and fill in the details.
Simulation command will be generated automatically.

Fig. 1.9 Edit Simulation Command window

b. Click “OK” to run the simulation and view the output.

Id(M1)
660µA

600µA

540µA

480µA

420µA

360µA

300µA

240µA

180µA

120µA

60µA

0µA
0.0V 0.1V 0.2V 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1.0V
 Fig. 1.10 Simulation result

c. Color of trace panel can be adjusted in “Tools”, “Color Preference”, “Waveform” tab,
“background” in pulldown menu.

Fig. 1.11 palette editor.

Step 8: To view the output of transient analysis

a. In the Edit Simulation Command window, select Transient Analysis and fill in the
details. Simulation command will be generated automatically.
b. Left click to activate (bring front) the schematic panel. Place the cursor on the node/wire
(voltage) or the element (current), and left click to probe and display the measured values

c. Right click on the trace panel, select “Add Traces”, and left click on the signals you want
to see. Click “OK” to display.
 Fig. 1.12 Trace panel.

Example 1.2 Plot the characteristic curve for Id – Vds, keeping Vgs constant, to observe the
different characteristic regions of nMOS transistor.
Solution:

a. Draw the same circuit diagram as in Example 1.1.

b. Change the DC sweep to voltage source V1 .
c. Run the simulation and observe the output waveform

Fig. 1.13 Circuit diagram

Id(M1)
660µA

600µA

540µA

480µA

420µA

360µA

300µA

240µA

180µA

120µA

60µA

0µA

-60µA
0.0V 0.1V 0.2V 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1.0V
 Fig. 1.14 Simulation output

Example 1.3 Plot the Id – Vgs characteristic of nMOS transistor, on varying the value of
Vds.
Solution:

a. Draw the same circuit diagram as in Example 1.1.

b. Change the DC sweep to voltage source V2 and sweep the voltage from 0 to 1 in steps of
0.001.
c. Now, we have to perform parametric analysis on voltage source V1. So declare Vds as a
variable, by right click on the voltage source V1 and change the value as {V1}, inside
flower brackets.
d. Use the .step parameter to vary the voltage source V1 from 0 to 1 in steps of 0.2, as
shown in the figure below.
e. Run the simulation. Select ‘Add trace’ and then select ‘Id(M1)’. The graph will be
plotted.
f. Observe the value where Id starts to raise. This happens at the threshold voltage. Note
down the value where it happens.

Fig. 1.15: Step statement editor

 Fig. 1.16: Circuit diagram

Fig. 1.17: Simulation output waveform

Example 1.4 Plot the Id – Vds characteristic of nMOS transistor, on varying the value of
Vgs.
Solution:

a. Draw the circuit diagram.

b. Change the DC sweep to V1 and sweep the voltage from 0 to 1 in steps of 0.001.
c. Use the .step parameter to vary the voltage source V2 from 0 to 1 in steps of 0.2.
d. Run the simulation and observe the output waveform.

Fig. 1.18: Circuit diagram

Fig. 1.19: Simulation output

Example 1.5 Plot the Id – Vgs characteristic of nMOS transistor, to study the effect of body
bias.
Solution:

a. Draw the circuit diagram, as shown below.

b. Change the DC sweep to V2 and sweep the voltage from 0 to 1 in steps of 0.001.
c. Use the .step parameter to vary the voltage source V3 from -0.2 to 0.2 in steps of 0.2.
d. Run the simulation and observe the output waveform.
 Fig. 1.20: Circuit diagram

Fig. 1.21: Simulation output

Example 1.6 Find the transconductance gain of the nMOS in saturation.

Solution:
 Once we plot Id v/s Vgs graph, we can calculate transconductance gain [gm] of the nMOS from
that graph since gm is the differentiation of Id with respect to Vgs.
 Any Mathematical operation can be done on the graph by right clicking on the trace
mentioned at the top of the graph.
 Since we need to differentiate Id graph, click on Id(M1) and in then enter d(Id(M1)) in its place.

This essentially gives you the differentiated graph from which we can note down the
transconductance value in saturation region for the given nMOS.

Simulation Results:
Fig 1.22 Plot of gm against Vgs
Op-amp characteristics:

An operational amplifier is a three-terminal device consisting of two high impedance input

terminals, one is called the inverting input denoted by a negative sign and the other is the non-
inverting input denoted with a positive sign. The third terminal is the output of the Op-Amp.

Inverting Operational Amplifier:

In the inverting operational amplifier circuit, the signal is applied at the inverting input
and the non-inverting input is connected to the ground. In this type of amplifier, the output is
180⁰ out of phase to the input, i.e. when positive signal is applied to circuit, the output of the
circuit will be negative. By assuming the Op-Amp is ideal, then the concept of virtual short can
be applied at the input terminals of the Op-Amp. So that voltage at the inverting terminal is equal
to the voltage at non-inverting terminal.

Non-Inverting Operational Amplifier:

When the signal is applied at the non-inverting input, the resulting circuit is known as
Non-Inverting Op-Amp. In this amplifier the output is exactly in phase with the input i.e. when a
positive voltage is applied to the circuit, the output will also be positive. By assuming the Op-
Amp is ideal, then concept of virtual short can be applied i.e. the voltage at the inverting and
non-inverting terminal is equal.
Example 1.7 Plot the transient characteristics of an inverting op-amp using LTSpice.

Solution:
a. Draw the circuit diagram of an inverting opamp as shown in the figure below. Save the
schematic as op_amp.asc.

Fig 1.23 Schematic of inverting opamp

b. Go to Heirarchy Create a new symbol. Draw the symbol as shown in figure below.
Name it as op_amp.asy.
 Fig 1.24 Symbol of inverting opamp

c. Open a new schematic window and select the symbol created, by changing the top
directory.

Fig 1.25 Selecting the symbol

d. Draw the circuit diagram using the symbol of the inverting opamp.

Fig 1.26 Circuit diagram

 e. Run the simulation and observe the output. The output will be an inverted form of the
input waveform.

Fig 1.27 Input and output waveforms of an inverting opamp

Exercise problems:

1) Draw the following characteristics for pMOS device using LTSpice and observe the
waveforms. [Hint: The voltages will be negative for a pMOS]
a. Id vs Vgs curve, by keeping Vds constant
b. Id vs Vds curve, by keeping Vgs constant
c. Id vs Vgs curve, by varying the values of Vds
d. Id vs Vds curve, by varying the values of Vgs
e. Id vs Vds curve to observe the body effect
2) Create a circuit symbol for a non-inverting op-amp using LTSpice and plot its transient
characteristics.
 Experiment No. 2:
MOSFET Amplifiers

Objective:
To design Common Source, Common Drain and Common Gate MOSFET amplifiers and
analyze the performance using LTspice.

Components & Equipment:

Computer, LTspice software

Theory:

Common Source (CS) amplifier:

It uses the gate as its input terminal and the drain as its output. The source terminal is
common to both the input and output in terms of the AC signal, hence the name common-source.
It is designed for providing very high input impedance.
An ideal CS amplifier has infinite input impedance (draws no current at DC), and a
moderately high output resistance (easier to match for maximum power transfer), and a high
voltage gain (a desirable feature of an amplifier).

Common Drain (CD) amplifier:

The input is applied between the gate and drain terminals, while the output is measured
between the source and drain terminal. Since the drain terminal is common between the input
and output side, it is known as Common Drain Amplifier. Since the output at the source terminal
is following the input signal, it is also known as Source Follower.
It is a unit-gain amplifier with a very large input impedance but a smaller output
impedance. Therefore, it is good for matching a high-impedance circuit to a low-impedance
circuit or to a circuit that needs a larger supply of current.

Common Gate (CG) amplifier:

Here, input is applied between source and gate and output is taken between drain and
gate.
Gate potential is at constant potential. So, increase in input voltage in positive direction cause
increase in the negative gate source voltage. The reduction in drain current results in an increase
in output voltage.
As the input impedance is low, it is good for matching sources with a low input
impedance due to the maximum power theorem, but it draws more current, implying high power
consumption from the signal source.
Example 2.1 In the following circuit, determine the voltage gain mathematically and verify
it using LTspice. Given specifications Vth = 0.5 V, μn C ox=100 μA /V 2, W/L = 5/0.18, λ=0.

Solution:
Circuit diagram:
 Fig 2.1 Circuit diagram of CS amplifier

Design:
Output:

Fig 2.2 Input and output waveforms of CS amplifier

Example 2.2 In the following circuit, determine the voltage gain mathematically and verify
it using LTspice. Given specifications Vth = 0.5 V, μn C ox=100 × 10−6 μA/V 2, W/L = 80, λ=0.

Solution:
Circuit diagram:

Fig 2.3 Circuit diagram of CD amplifier

Design:
Output:

Fig 2.4 Input and output waveforms of CD amplifier

Example 2.3 In the following circuit, determine the voltage gain mathematically and verify
it using LTspice. Given specifications Vth = 0.5 V, μn C ox=100 μA /V 2, W/L = 244, λ=0.
Solution:

Circuit diagram:

Fig 2.5 Circuit diagram of CG amplifier

Design:
Output:

Fig 2.6 Input and output waveforms of CG amplifier

Exercise problems:

1) Determine the gain of the circuit diagram in Fig 2.1, if C 1is removed.
2) Determine the gain of the circuit diagram in Fig 2.1, if C 1=100 µF and λ=0.1V-1.
 Experiment No. 3:
MOSFET Current Mirror

Objective:
To design basic current mirror (with resistive load, nmos load and pmos load) and analyze the
performance using LTspice.

Components & Equipment:

Computer, LTspice software

Theory:

Current mirror is an analog circuit that senses the reference current and generates the
copy or number of copies of the reference current, with the same characteristics. The replicated
current is as stable as the reference current source. The replicated current could be the same as
the reference current, or it could be either multiple or fraction of the reference current.

Current Mirrors are particularly useful in the integrated circuits, for biasing the
amplifiers. The advantage of biasing the amplifiers with the current source is that it provides a
high voltage gain and good biasing stability.

Example 3.1 In the following circuit, determine I D2/ID1 when (i) λ=0 and (ii) λ=0.05 V −1 ,
and verify it using LTspice.
Given specifications, μn C ox=100 μA /V 2,( )
W
=
5
L 1 0.18
, V T =0.5
W
( )
=
10
L 2 0.18
Solution:
Circuit diagram:

Fig 3.1 Circuit diagram of current mirror

Design:
Output:

Fig 3.2 Input and output waveforms of current mirror

Fig 3.3 Transient analysis of current mirror

Exercise problems:
2
1) Repeat the circuit in Fig 3.1 when (i) λ=0 and (ii) λ=0.01 V −1, and μn C ox=100 μA /V ,

( WL ) = 0.18
1
10
, V =0.5 ( ) =
T
W
L 2
50
0.18
.
 Experiment No. 4:
MOSFET Differential Amplifier

Objective:
To design a MOSFET differential amplifier with resistive load and analyze the performance
using LTspice.

Components & Equipment:

Computer, LTspice software

Theory:

Differential amplifiers provide a high input impedance for the input terminals. A properly
designed differential amplifier with its current-mirror biasing stages is made from matched-pair
devices to minimize imbalances from one side of the differential amplifier to the other. Two
active devices are connected to a positive voltage supply via passive series elements. The
transistors must be a matched pair (i.e., two matched MOSFETs). The "pull up" loads are
similarly matched to each other. The lower terminals of the active devices are connected
together, and a dc current source pulls current down toward the negative voltage bus to effect the
bias. The controlling input ports of the devices are connected to input signals

Differential amplifiers apply gain not to one input signal but to the difference between
two input signals. This means that a differential amplifier naturally eliminates noise or
interference that is present in both input signals.

Differential amplification also suppresses common-mode signals, i.e. a DC offset that is

present in both input signals will be removed, and the gain will be applied only to the signal of
interest, eliminating the need for bulky DC-blocking capacitors. The subtraction that occurs in a
differential pair makes it easy to incorporate the circuit into a negative-feedback amplifier.

Example 4.1 In the following circuit, determine the voltage gain mathematically and verify
it using LTspice. Given specifications, Vth = 0.5 V, μn C ox=100 μA /V 2, W/L = 869, λ=0.
Solution:

Circuit diagram:

Fig 4.1 Circuit diagram of differential amplifier

Design:
Output:

Fig 4.2 Input and output waveforms of differential amplifier

Fig 4.3 Output waveform of differential amplifier

Exercise problems:

1) Repeat the circuit in Fig 4.1 with Vth = 0.5 V, μn C ox=100 μA /V 2, W/L = 869, and
−1
λ=0.01 V .
 Experiment No. 5:
MOSFET Feedback Amplifier

Objective:
To design MOSFET feedback amplifier and analyze the performance using LTspice.

Components & Equipment:

Computer, LTspice software

Theory:

The concept of feeding the output signal back to its input circuit is known as feedback
and hence the name feedback amplifier. It is dependent between the output and input with
effective control. Figure 6.1 shows voltage series feedback amplifier, where feedback circuit is
connected in shunt with the output in such a way that it decreases the output impedance and
increases the input impedance. In this circuit, it is placed in a shunt with the output but in series
with respect to the input signal.

Fig 5.1 Block diagram of voltage series feedback amplifier

Feedback amplifiers are divided into two types: positive feedback and negative feedback.
In the positive feedback amplifier, the input voltage or the current is in phase with the input
signal. Both the input signal and feedback introduce a phase shift of 180° and makes a 360°
resultant phase shift to be in phase with the input signal. It increases the gain of the amplifier but
also increases distortion and instability. Normally, positive feedback is not used for amplifiers.
For example, positive feedback is used to provide hysteresis for oscillators and comparators.

When any increase in the output signal results into the input in such a way as to cause the
decrease in the output signal, the amplifier is said to have negative feedback. The advantages of
providing negative feedback are that the transfer gain of the amplifier with feedback can be
stabilized against variations in the hybrid parameters of the transistor or the parameters of the
other active devices used in the circuit. The most advantage of the negative feedback is that there
is significant improvement in the frequency response and in the linearity of the operation of the
amplifier. In Voltage-Series feedback, the input impedance of the amplifier is increased and the
output impedance is decreased. Noise and distortions are reduced considerably.
Example 5.1 Design a voltage series negative feedback amplifier and analyze its transient
response and frequency response using LTspice.

Solution:
Transient response:

Fig 5.2 Circuit diagram of voltage series feedback amplifier

Output:

Fig 5.3 Output waveform of transient analysis

Frequency response:
To observe the frequency response, use the Spice command
.ac dec 10 10 100Meg

Output:

Fig 5.4 Frequency response

Exercise problems:

1) Design a voltage series positive feedback amplifier and analyze its transient response and
frequency response using LTspice.
 Experiment No. 6:
MOSFET Oscillators

Objective:
To design MOSFET oscillators and analyze the performance using LTspice.

Components & Equipment:

Computer, LTspice software

Theory:

An oscillator is used to generate a signal which has a specific frequency, and these are
useful for synchronizing the computation process in digital systems. It is an electronic circuit that
produces continuous waveforms without any input signal. The oscillator converts a dc signal into
an alternating signal form at the desired frequency. There are various types of oscillators
depending on the components which are using in the electronic circuits.

LC oscillator:

The LC oscillator is a type of tuned oscillator that uses a combination of L (Inductor) and
C (Capacitor) to provide the required positive feedback, which is essential to produce sustained
oscillations in the circuit. The sustained oscillations ensure periodic oscillations at a specific
frequency. LC oscillators reverse the voltage polarity using an inductor (L) and a capacitor (C) to
create the oscillating effect.

RC oscillator:

A linear oscillator circuit which uses an RC network, a combination of resistors and

capacitors, for its frequency selective part is called an RC oscillator. In RC oscillator circuits
which use a single inverting amplifying device, the amplifier provides 180° of the phase shift, so
the RC network must provide the other 180°. Since each capacitor can provide a maximum of
90° of phase shift, RC oscillators require at least two frequency-determining capacitors in the
circuit (two poles), and most have three or more, with a comparable number of resistors. RC
oscillators are used to produce lower frequencies, mostly audio frequencies, in such applications
as audio signal generators and electronic musical instruments.

Schmitt trigger:

Schmitt triggers are bistable networks that are widely used to enhance the immunity of
circuits to noise and disturbances. The main difference between Schmitt triggers and
comparators lies in the DC transfer characteristics. The comparator shows only one switching
threshold, while Schmitt trigger shows different switching thresholds for positive-going and
negative-going input signals. This characteristic is called hysteresis. If the noise magnitude of the
input signal is less than the switching threshold difference, Schmitt trigger will not respond, thus
making Schmitt trigger immune to the undesired noise. The Schmitt trigger is a circuit that
converts a varying voltage into a stable logical signal (one or zero). The DC transfer
characteristic needs hysteresis to reduce the sensitivity to noise and disturbances. The hysteresis
in a Schmitt trigger offers better noise margin and noise stable operation.

Ring oscillator:

Ring oscillator is described as an odd number of inverters are connected in a series form
with positive feedback & output oscillates between two voltage levels either 1 or zero to measure
the speed of the process. These oscillators have an ‘n’ odd number of inverters. The number of
inverter stages in this oscillator mainly depends on the frequency that we want to generate from
this oscillator.

Fig 6.1 Three-stage ring oscillator

Example 6.1 Design and simulate a 5 GHz LC VCO oscillator using TSMC 180 nm in
LTspice.

Solution:
Circuit diagram:

Fig 6.2 Circuit diagram of LC oscillator

Design:
Use NMOS with W =20 μm and L=0.18 μm.

Output:

Fig 6.3 Output waveform of LC oscillator

Example 6.2 Design and simulate a RC phase shift oscillator using LTspice.

Solution:
Circuit diagram:

Fig 6.4 Circuit diagram of RC oscillator

Output:

Fig 6.5 Output waveform of RC oscillator

Example 6.3 Design and simulate a Schmitt trigger using LTspice.

Solution:

Circuit diagram:

Fig 6.6 Circuit diagram of Schmitt trigger

Design:

Use M1 transistor = NMOS with W =500 nm and L=50 nm .

Use M2 transistor = NMOS with W =500 nm and L=50 nm .
Use M3 transistor = NMOS with W =1.125 μm and L=50 nm .
Use M4 transistor = PMOS with W =1 μm and L=50 nm .
Use M5 transistor = PMOS with W =1.3 μm and L=50 nm .
Use M6 transistor = PMOS with W =1 μm and L=50 nm .

Output:

Fig 6.7 Output waveform of Schmitt trigger

Exercise problems:

1) Design and simulate a ring oscillator circuit using LTspice (Odd number of CMOS
inverter in a loop).
 Experiment No. 7:
Linear application of OP AMP

Objective:
To design and test inverting amplifier, summing amplifier and integrator using OPAMP.

Components & Equipment:

Dual source DC power supply, CRO, OPAMP μA741 and discrete components.

Theory:

(a) Inverting Amplifier

Fig. 7.1 (a): Inverting amplifier circuit (b): Inverting amplifier I/O waveforms

Design:

− Rf
Voltage gain, AV = = 10 ; Choose R =1 kΩ, then Rf =10 kΩ
R
 Fig. 7.2 : Frequency Response

Procedure:
Frequency response
1. Rig up the circuit as shown in the Fig.7.1(a) with VCC = ±12V.
2. Apply 2Vp-p sinusoidal input signal of 1 kHz from AFO.
3. Observe the output waveform on the CRO and measure the Voltage gain.
4. Vary the input frequency from 100Hz to 1MHz and note down the corresponding
output voltage. Also measure the 3 dB frequency.
5. Increase the frequency in multiples of 10 and measure the roll-off rate in dB per
decade (or multiple of 2 to measure the roll-off rate in dB per octave).
6. Plot the frequency response on the semi-log graph sheet.
7. Check what happens if the input voltage is increased to 5V p-p.
Slew Rate Measurement
8. Apply square wave signal of frequency 10 kHz and peak to peak amplitude 0.5V
(such that it operates in mid-band and linear region) to the inverting amplifier shown
in Fig. 7.1(a)
9. Observe the input and output waveforms and the transitions between two levels of
square wave. The slope measured at the transitions gives slew rate of OPAMP.
10. Change the frequency of the signal and plot the input and output waveform
properly labelled.
Observations:
Vin = _________________ V.
Frequency Output Gain Gain in dB
 Voltage(V
(Hz) (Vo/Vin) 20 log(Vo/Vin)
o)

Slew rate measurement

Vin = _________________ V.

Frequency Slope (V/μsec)

5 kHz
10 kHz
15 kHz
20 kHz

(b) Summing Amplifier

Circuit diagram:
 Fig. 7.3: Summing amplifier circuit

Design:

Design the circuit to obtain Vout = -(V1+V2)

V1 V2
For summing amplifier; Vout = -Rf ( +
R1 R2

Let Rf = 1KΩ; R1 = Rf =1KΩ; R2 = Rf =1KΩ

Procedure:

1. Rig up the circuit as shown in Fig. 7.3. Give V 1 and V2 from two different input
sources (in lab use two dc power supplies) and measure the output.
2. Repeat for three to four sets of -/+ values and measure the output.

Observations:

Input Voltage (Vi) Output

V1 V2 Voltage (Vout)

Exercise problems:

1. Design a summing amplifier using single IC μA 741 OPAMP to realize

a. Vout = 2 Vin1 − 4 Vin2 − 2 Vin3

b. Vout = 8 Vin1 − 3 Vin2 − 0.5 Vin3

2. Design a non-inverting amplifier given in Fig. 7 . 4 for gain of 5. Obtain
the frequency response and transfer characteristics.
Fig. 7.4: Non-inverting amplifier circuit
 Experiment No. 8:
Active filters using OP-AMP

Objective:
To design and implement low pass and high pass active filters and to observe the frequency
responses.

Components & Equipment:

Dual source DC power supply, CRO, function generator, OPAMP μA741 & discrete
components.

Theory:

LOW PASS FILTER (LPF)

Circuit Diagram:

Fig. 8.1(a) Second order LPF (b) Frequency response

Design:

fc = 1 kHz, with pass band gain = 2. Assume 𝐶1 = 𝐶2 = 0.1µF.

Rf
Let R1 = 10 kΩ. Therefore, Av = 1 + = 2, then R2 = 10kΩ.
R1

1 1
f c= if R2=R3=R & C1 = C2 = C, then R = = 1.59kΩ
2 √ R2 R 3 C 1 C 2 2f cC
Procedure:

1. Rig up the circuit as shown in the Fig. 8.1(a).

2. Using AFO, apply 1 kHz sinusoidal input with a peak-to-peak amplitude of 1 V
(positive peak = 0.5 V). Observe the input and output using CRO.
3. Keeping input voltage constant, vary the input frequency from 10 Hz to 10 kHz and
note down the amplitude change in output voltage waveform. Tabulate these results
in dB and plot the frequency response.

HIGH PASS FILTER (HPF)

Design: (Check)

fc = 100 Hz, with pass band gain = 2. Assume 𝐶1 = 𝐶2 = 0.1µF.

Rf
Let R1 = 10 kΩ. Therefore, Av = 1 + = 2, then R2 = 10kΩ.
R1

1 1
f c= if R2=R3=R & C1 = C2 = C, then R = = 1.59kΩ
2 √ R2 R 3 C 1 C 2 2f cC

Circuit Diagram:

Fig. 8.2(a) Second order HPF (b) Frequency response

Exercise problems:

1. Implement the circuit in Fig. 8.3 with fR = 1 kHz, Q = 4, A = 8, Let 𝐶1 = 𝐶2 =

0.0047µF and plot the graph.

Fig. 8.3(a) Notch Band Pass Filter (b) Frequency response

2. Implement the circuit in Fig. 8.4 Rf = R1=10kΩ and plot the graph.

Fig. 8.4 (a) All pass filter (b) Phase response

 Experiment No. 9:
Schmitt Trigger using OP AMP

Objective:
To design and test Schmitt trigger using OPAMP.

Components & Equipment:

Dual-mode DC power supply, CRO, µA 741, discrete components.

Procedure:

1. Rig up the circuit as shown in Fig. 9 . 1(a).

2. Apply 1 kHz sinusoidal signal of 1V peak-to-peak.

3. Observe and note the input and output waveforms using CRO.

Design:

VUTP = 7.5V, VLTP = -7.5V and VOUT = ±15V

R1 − R1
V UTP = V Sat ; V LTP = V
R 1+ R 2 R1 + R2 Sat

R1 1
Hence = ; Choose R1 = 1KΩ then R2 = 1KΩ
R 1+ R 2 2

Circuit Diagram:

Fig. 9.1 (a): Inverting Schmitt Trigger circuit (b) Inverting Schmitt Trigger I/O waveform (c)
Hysteresis curve

Results:

VUTP(Theoretical) = VLTP(Theoretical) =

VUTP(Practical) = VLTP(Practical) =

Exercise problems:
1. Design an (a) inverting (b) Non inverting Schmitt trigger for the following
specifications:
a. VUTP = 5V, VLTP = −5V
b. VUTP = 7.5V, VLTP = −5V
c. VUTP = 3V, VLTP = 1V
 Experiment No. 10:
555 Timer Applications

Objective:
To design Astable and Monostable multivibrators using IC 555.

Components & Equipment:

IC 555, DC Power Supply, CRO, 1N4001, and discrete components.

Procedure:

1. Connect the circuit as shown in Figures.

2. Connect VCC of 5V

3. Observe the waveforms at pin no. 2, 6 and 3 of IC 555 on the CRO.

ASTABLE MULTIVIBRATOR

Circuit Diagram:

Fig. 10.1(a): Asymmetric Astable multivibrator, (b) Waveforms at Pin no. 3 and 2

Design:

To obtain a square wave of 0.5 kHz frequency with 66% duty cycle

1 T ON
T = =2mSec ∧ Duty Cycle= =66 %
f T
Hence TON= 1.38 mSec and TOFF = 0.69 mSec

TOFF = RBC ln2 = 0.69 mSec; Assuming, RB=10kΩ calculate C (C= 0.952 µF)

TON= C(RA+RB) ln 2, Hence Find RA=10kΩ.

Observations:

VPP of Square wave: TON :

VPP of Capacitor voltage: TOFF :

Duty Cycle:

Result:

Output Theoretical Practical

Frequency
Amplitude

MONOSTABLE MULTIVIBRATOR

Circuit Diagram:

Design:

Monostable multivibrator with 1.1ms pulse width T= RC ln3=1.1

Assuming C= 0.1µF , Compute R ( R=10 kΩ) For Trigger circuit R1= 10 kΩ

Fig. 10.2 (a) Monostable multivibrator b) Trigger and output waveforms

Observations:
VPP of pulse wave: TON:

Duty Cycle:

VPP of capacitor voltage: TOFF:

Result:

Pulse width:

Theoretical: 1.1ms Practical:

Exercise problems:

1. Design a circuit using IC 555 to generate a 3 kHz, 75% duty cycle square wave.
2. Design symmetric astable mutivibrator given in fig below.