UNIT 4

LPC2148
System control block
Pin Description of System Control
Block
Cont…
System Control Registers
Cont..
System control block function PLL
 Phase Locked Loop
• PLL is a closed loop system to generate high frequency
by multiplying with given factor to the input frequency.
• There are two PLL modules in the LPC2148
microcontroller.
• The PLL0 is used to generate the CCLK clock (system
clock) .
• The PLL1 has to supply the clock for the USB at the
fixed rate of 48 MHz.
• PLL interrupts are only available for PLL0 and not for
PLL1.
• Input clock to both the PLLs must be between 10Mhz
to 25Mhz strictly.
 Cont….
• The input frequency is multiplied: 10 MHz to
60 MHz for the CCLK and 48 MHz for the USB
clock using CCO.
• The multiplier can be an integer value from 1 to
32.
• The CCO (current control oscillator) range- 156
MHz to 320 MHz, so there is an additional divider
in the loop to keep the CCO within its frequency
range while the PLL is providing the desired
output frequency.
 Symbols
FOSC Frequency of the crystal oscillator

CCO Frequency of Current Controlled Oscillator (CCO)

CCLK CPU Clock frequency (PLL Output frequency)

PLL Multiplier value (set using MSEL bits in PLLCFG

M
register)

P PLL Divider value (set using PSEL bits in PLLCFG register)

PCLK Peripheral clock from CCLK

 Cont…
• ARM7 LPC2148 needs two clocks; one is for its
peripherals and other for its CPU.
• CPU works faster with higher frequencies
whereas peripheral needs lower frequency to
work with.
• The Peripheral Clock i.e. PCLK is derived from CPU
Clock i.e. CCLK.
• The input to APB Divider is CCLK and output is
PCLK. By Default PCLK runs at 1/4th the speed of
CCLK.
The frequency of CPU clock or the output of the PLL
is
CCLK = M x FOSC or CCLK = CCO / (2 x P)

The frequency of CCO is

CCO = CCLK x 2 x P or CCO = FOSC x M x 2 x P

Standard Values (when PLL is used)

• The range of FOSC is 10 MHz to 25 MHz
• The range of CCLK is 10 MHz to FMAX (60 MHz
for LPC214x MCUs)
• The range of CCO is 156 MHz to 320 MHz.
 Setting up PLL
• PLL activation is controlled via the PLLCON register. The
PLL multiplier and divider values are controlled by the
PLLCFG register.
• Since all chip operations, are dependent on the PLL0,
accidental changes in the PLL setup could result in unexpected
behavior, so these two registers are protected

• The same concern is present with the PLL1 and the USB.

• Both PLLs are turned off and bypassed following a chip Reset
and when by entering Power-down mode.
• The program must configure and activate the PLL, wait for the
PLL to Lock, then connect to the PLL as a clock source.
PLLCON
PLLCFG
PLLSTAT
PLL Feed Register
PLLCON
PLL Interrupt
// This pgm for 60Mhz clk & 60Mhz pclk

void set_pll(void)
{
PLL0CON=0x01;
// PPLE=1 & PPLC=0 so it will be enabled but not connected after FEED
sequence
PLL0CFG=0x24;
// set the multipler to 5 (i.e actually 4) i.e 12x5 = 60 Mhz (M - 1 = 4), Set P=2 since
we want FCCO in range So , Assign PSEL =01 in PLL0CFG as per the table.
PLL0FEED=0XAA; //feed
PLL0FEED=0X55;
while((PLL0STAT&(1<<10))==0);
// check whether PLL has locked on to the desired freq by reading the lock bit in
the PPL0STAT register
PLL0CON=0x03;
//enable & connect pll
PLL0FEED=0XAA;
PLL0FEED=0X55;
VPBDIV = 0x01;
// PCLK is same as CCLK i.e 60Mhz
}
 Timer
Features:
 A 32-bit Timer/Counter with a programmable 32-bit
Prescaler.
 Counter or Timer operation Timer/Counter0 and
Timer/Counter1 are functionally identical except for
the peripheral base address.
 Four 32-bit capture channels/ timer
– Take a snapshot of the timer value when an input signal
transitions. Optionally generate an interrupt.
 Four 32-bit match registers- allow:
o Continuous operation with optional interrupt
generation on match.
o Stop / Reset timer on match with optional interrupt
generation.
 PCLK and VPDIV Register
• All of the timers are driven by PCLK which is
the Peripheral Clock. The system is generally
driven by the CCLK or Crystal Clock.
• PCLK is derived from CCLK which is the
processor clock.
• If CCLK = 60MHz, VPBDIV register determines
the rate of PCLK. VPBDIV is not the same as
the prescaler register although its action is
similar.
• VPBDIV is an 8-bit register and only the lower
two bits of it are used.
 Cont..
Note:
PCLK goes into a prescaler which further scales
the clock going to the timer. The output of the
prescaler actually drives the timer register.
 Timer
No of Timers : 2 (Timer 0 & Timer 1)
• The Timer/Counter is designed to count cycles
of the peripheral clock (PCLK) or externally-
supplied clock, and
• Can optionally generate interrupts or perform
other actions at specified timer values
Two timer/counters named Timer0 and Timer1.
Each timer has the following features:
• A 32-bit Timer/Counter with a programmable
32bit Prescaler.
• The prescaler allows the user to divide the
clock.
• Counter or Timer operation.
• Four 32-bit capture channels per timer that
take a snapshot of the timer value when an
input signal transitions.
• A capture event may also optionally generate
an interrupt.
 Timer Register
1. PR : Prescale Register (32 bit) – Stores the maximum
value of Prescale counter after which it is reset.
2. PC : Prescale Counter Register (32 bit) – This register
increments on every PCLK(Peripheral clock).
a. This register controls the resolution of the timer.
b. When PC reaches the value in PR , PC is reset back to
0 and Timer Counter is incremented by 1.
c. If PR=9 then Timer Counter Increments on every 10th
cycle of PCLK. Hence by selecting an prescale value
we can control the resolution of the timer.
3. TC : Timer Counter Register (32 bit) – This is the main
counting register. Timer Counter increments when PC
reaches its maximum value as specified by PR.
 Cont..

4. TCR : Timer Control Register(8 bit) – This register is

used to enable , disable and reset TC.
a. When bit0 =1, timer is enabled and when 0 it is
disabled.
b. When bit1 is set to 1 TC and PC are set to zero
together in sync on the next positive edge of PCLK.
Rest of the bits of TCR are reserved.
5. CTCR : Count Control register(8 bit) – Used to select
Timer/Counter Mode. Bits 1:0 are used
a. For our purpose we are always going to use this in
Timer Mode. When the value of the CTCR is set to 0×0
Timer Mode is selected.
7:2
6) MCR : Match Control register (16 bit) – This register is used
to control which all operations can be done when the value in
MR matches the value in TC.
Bits 0,1,2 are for MR0 , Bits 3,4,5 for MR1 and so on. Here's a
quick table which shows the usage:

• For MR0:
– Bit 0 : Interrupt on MR0 i.e trigger an interrupt when MR0
matches TC. Interrupts are enabled when set to 1 and
disabled when set to 0.
– Bit 1 : Reset on MR0. When set to 1 , TC will be reset when it
matched MR0. Disabled when set to 0.
– Bit 2 : Stop on MR0. When set to 1 , TC & PC will stop when
MR0 matches TC. – Similarly bits 3-5 , 6-8 , 9-11 are for MR1 ,
MR2 , MR3 respectively.
15:12
 Timer Features
 Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on

match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation

 Four external outputs corresponding to match registers,

with the following capabilities:
– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match.
 Match Registers
• A Match Register is a Register which contains a specific value set by
the user.

• When the Timer starts – every time after TC is incremented the value
in TC is compared with match register.

• If it matches then it can Reset the Timer or can generate an interrupt

as defined by the user.

• Match Registers can be used to:

– Stop Timer on Match and trigger an optional interrupt.
– Reset Timer on Match and trigger an optional interrupt.
– To count continuously and trigger an interrupt on match.
 Pin description
• MAT0.3..0 & MAT1.3..0 (Output)
• External Match Output 0/1- When a match
register 0/1 (MR3:0) equals the timer counter
(TC), this output can either toggle, go low, go
high, or do nothing.
• The External Match Register (EMR) controls
the functionality of this output.
 Capture Registers
• As the name suggests it is used to Capture Input
signal. When a transition event occurs on a
Capture pin , it can be used to copy the value of
TC into any of the 4 Capture Register or to
generate an Interrupt.
• CAP0.3..0 & CAP1.3..0 (Input) Capture Signals-
A transition on this (capture) pin is found, it loads
one of the Capture Registers with the value in the
Timer Counter and optionally generate an interrupt.
List of all CAPTURE signals, together with pins on
where they can be selected: Capture 0:
• CAP0.0 (3 pins) : P0.2, P0.22 and P0.30
• CAP0.1 (1 pin) : P0.4
• CAP0.2 (3 pin) : P0.6, P0.16 and P0.28
• CAP0.3 (1 pin) : P0.29 Capture 1:
• CAP1.0 (1 pin) : P0.10
• CAP1.1 (1 pin) : P0.11
• CAP1.2 (2 pins) : P0.17 and P0.19
• CAP1.3 (2 pins) : P0.18 and P0.21
7) IR : Interrupt Register – It contains the interrupt
flags for 4 match and 4 capture interrupts.
a. Bit0 to bit3 are for MR0 to MR3 interrupts
respectively.
b. And similarly the next 4 for CR0-3 interrupts.
c. when an interrupt is raised the corresponding
bit in IR will be set to 1 and 0 otherwise.
d. Writing a 1 to the corresponding bit location
will reset the interrupt – which is used to
acknowledge the completion of the
corresponding ISR execution.
 Setting up & configuring Timers
1. To use timers we need to first configure
them.
2. We need to set appropriate values in TxCTCR,
TxIR, TxPR and reset TxPC, TxTC.
3. Finally we assign TxTCR = 0×01 which enables
the timer.
 Timer Calculation

Time Delay=(PR+1)(MR)/PCLK
PCLK=60MHz
• PR= Presale Register
• MR=Match Register
• PCLK= Peripheral Clock
 Delay Generation Using Timers
Note:

Timer Blocks use peripheral clock as their input

and hence peripheral clock must be initialized
before Timer is initialized.
// Initialize PLL
// Consider 60Mhz clk & 60Mhz pclk
void set_pll(void)
{
PLL0CON=0x01;
// PPLE=1 & PPLC=0 so it will be enabled but not connected after FEED
sequence
PLL0CFG=0x24;
// set the multipler to 5 (i.e actually 4) i.e 12x5 = 60 Mhz (M - 1 = 4), Set P=2 since
we want FCCO in range So , Assign PSEL =01 in PLL0CFG as per the table.
PLL0FEED=0XAA; //feed
PLL0FEED=0X55;
while((PLL0STAT&(1<<10))==0);
// check whether PLL has locked on to the desired freq by reading the lock bit in
the PPL0STAT register
PLL0CON=0x03;
//enable & connect pll
PLL0FEED=0XAA;
PLL0FEED=0X55;
VPBDIV = 0x01;
// PCLK is same as CCLK i.e 60Mhz
}
In order to initialize the Timer 0 block, the following
steps must be followed.
T0CTCR = 0x0; // Timer Mode is selected.
T0PR = 59; // PR is set to this value for 1mS delay in
incrementing of TC
T0MR0=1000000;
T0TCR = 0x02; // Reset the Timer
Now we will see some commands to get a delay as
per the user requirements in milliseconds. For this,
we need to use the
Timer Control Register (TCR) and
Timer Counter register (TC).
In order to get a delay as per the user’s input in
milliseconds, we need to use the following steps.
T0TCR = 0x02; // Reset the Timer
T0TCR = 0x01; // Enable the Timer
while (T0TC !=T0MR0); //Wait till the TC reaches the
desired delay
T0TCR = 0x00; // Disable the Timer
// LED Blink Program without using timers for delay generation
#include <LPC21xx.h>
unsigned int delay;
int main ()
{
PINSEL0 = 0x00000000 ; // Configure P0.0 to P0.15 as GPIO
PINSEL1 = 0x00000000 ; // Configure P0.16 to P0.31 as GPIO
IO0DIR =gd
while(1)
{
IO0CLR = 0x00FF0000; // IO0CLR |= (0xFF<<16)
// CLEAR P0.16 to P0.23, LEDs ON
for(delay=0; delay<500000; delay++); // delay
IO0SET = 0x00FF0000; // IO0SET |= (0xFF<<16)
// SET (1) P0.16 to P0.23, LEDs , LEDs OFF
for(delay=0; delay<500000; delay++); // delay
}

}
//Blinking LED program using Timers for an efficient delay operation

#include<lpc214x.h>
/* Initialize the PLL0 and configure it to produce 60 MHz System Clock (CCLK) and Peripheral
Clock (PCLK) */
Void PLL(){
PLL0CON = 0x01;
PLL0CFG = 0x24;
PLL0FEED = 0xaa;
PLL0FEED = 0x55;
while (!(PLL0STAT & 0x00000400)); //while((PLL0STAT&(1<<10))==0);
PLL0CON = 0x03;
PLL0FEED = 0xaa;
PLL0FEED = 0x55;
VPBDIV = 0x01;
}
/* Function definition of delay function */
void timer()
{
T0CTCR=0X0000; //Timer Mode
T0PR=59; //Prescaler Value
T0MR0=1000000; //Match Register Value
T0MCR=0x04;
//TC and PC will be stopped and TCR[0] will be set to 0 if MR0
matches the TC.
T0TCR=0X02; //Reset Timer
T0TCR=0X01; //Timer ON
while(T0TC!=T0MR0);
T0TCR=0x0;
T0TC=0; //Timer OFF
}
int main()
{
PINSEL1=0x00;
/* Configure all pins of PORT 0 as outputs */
IO0DIR=0xFFFFFFFF;
PLL();

while (1)
0X00FF0000;
{ IO0SET=0xFFFFFFFF; // IO0SET |= (0xFF<<16)
timer();
0X00FF0000;
IO0CLR=0xFFFFFFFF; // IO0CLR |= (0xFF<<16)
timer();
}
}
 PWM
Pulse Width Modulation (PWM) is a technique
by which width of a pulse is varied while keeping
the frequency constant.
LPC2148 supports two types of controlled PWM
outputs as,

• Single Edge Controlled PWM Output

Only falling edge position can be controlled.

• Double Edge Controlled PWM Output

Both Rising and Falling edge positions can be
controlled.
• Single Edge Controlled PWM : All the rising
(positive going) edges of the output waveform
are positioned/fixed at the beginning of the
PWM period. Only falling (negative going)
edge position can be controlled to vary the
pulse width of PWM.
• Double Edge Controlled PWM : All the rising
(positive going) and falling (negative going)
edge positions can be controlled to vary the
pulse width of PWM. Both the rising as well as
the falling edges can be positioned anywhere
in the PWM period.
 LPC2148 PWM
• It is based on standard 32-bit Timer Counter, i.e.
PWMTC (PWM Timer Counter). This Timer Counter
counts the cycles of peripheral clock (PCLK).
• We can scale this timer clock counts using 32-bit
PWM Prescale Register (PWMPR).
• LPC2148 has 7 PWM match registers (PWMMR0 –
PWMMR06).
• One match register (PWMMR0) is used to set PWM
frequency.
 Cont..
• Remaining 6 match registers are used to set PWM
width for 6 different PWM signals in Single Edge
Controlled PWM or 3 different PWM signals in
Double Edge Controlled PWM.
• Whenever PWM Timer Counter (PWMTC)
matches with these Match Registers then, PWM
Timer Counter resets, or stops, or generates
match interrupt, depending upon settings in
PWM Match Control Register(PWMMCR).
 Associated Registers
1. PINSEL0 & PINSEL1
2. PWMIR(PWM INTERRUPT REGISTER)
3. PWMPR(PRESCALE REGISTER)
4. PWMPC(PRESCALE COUNTER)
5. PWMTC(TIMER COUNTER)
6. PWMTCR(TIMER CONTROL REGISTER)
7. PWMPCR(PWM CONTROL REGISTER)
8. PWMMCR(MATCH CONTROL REGISTER)
PWM CHANNEL
CHANNEL NUMBER PORT PIN PWM MATCH REGISTER

PWM1 P0.0 PWMMR1

PWM2 P0.7 PWMMR2

PWM3 P0.1 PWMMR3

PWM4 P0.8 PWMMR4

PWM5 P0.21 PWMMR5

PWM6 P0.9 PWMMR6

PWM INTERRUPT REGISTER
 PWM Prescale register
• 32 bit prescale register specifies the maximum
value for the prescale counter(PC)
 PWMPC(PRESCALE COUNTER)
• It is a 32-bit register.
• It controls the division of PCLK by some
constant value before it is applied to the PWM
Timer Counter.
• It is incremented on every PCLK.
• When it reaches the value in PWM Prescale
Register, the PWM Timer Counter is
incremented and PWM Prescale Counter is
reset on next PCLK.
PWMTC(TIMER COUNTER)
 PWM Match register(PWMMR0 to
PWMMR6)
• The 32 bit PWM Match register values are
continuously compared to the PWM timer
counter value.
• When the two values are equal, actions can
be triggered automatically. The action
possibilities are to generate an interrupt, reset
the PWM timer counter, or stop the timer.
• Actions are controlled by the settings in the
PWMMCR register
PWMMCR REGISTER
 PWMPCR
• PWM Control Register– Enables PWM outputs
and selects PWM channel types as either
single edge or double edge controlled.(16 Bit
Register)
PWMLER
 PWMLER

7
 Example 1
// Single Edge Control
// PWM channel 1 and PWM channel 2
• Let us set PWMMR0 as 150000(T=150000
PCLOCKS)
• PWMMR1=Ton=75000 PCLK// 50% Duty Cycle
• PWMMR2=Ton=100000 PCLK//66.66% Duty
cycle
 Steps to program PWM
1. Select the PINSEL register according to which
PWM output pin is selected(PWM channel).
To select P0.0 PWM1, PINSEL[1:0]=10
P0.7 PWM2, PINSEL[15:14]=10
2. Configure TCR to enable the Counter for incrementing the TC,
TC and Prescale to reset, and Enable the PWM block.

//To reset TC and Prescalar PWMTCR[1]=1

• PWMTCR[0]=1 , TC & prescalar are enabled i.e
CE bit
• PWMTCR[3]=1, PWM is enabled.
• So the value in PWMTCR=00001001, i.e 09H
 3. Set the required pre-scalar value in PR. Consider PR=0

• PWMPR=0
4. Configure MCR to reset the TC whenever it matches MR0.

PWMMCR[1]=1, to reset PWMTC after match MR0

So the value is PWMMCR=0x00000002H
5. Update the Cycle time in MR0
PWMMR0=150000
6. Load the Duty cycles for required PWMx channels in respective
match registers MRx(x: 1-6)
In our example
PWMMR1=75000
PWMMR2=100000
7. Enable the bits in LER register to load and latch the new match
values.
We will load PWMMR1 and PWMMR2 values once the timer ie reset
so the value in PWMLER=00000110 i.e PWMELER=0x06H

8. Enable the required PWM channels in PCR register.

15

so the value in PWMPCR=0000011000000000

PWMPCR=0x0600H
Void PWM_init()
{
PINSEL0=0X00008002;
PWMTCR=0X09;
PWMPCR=0X600;
PWMPR=0;
PWMMCR=0X02;
PWMMR0=150000;
}
int main()
{
PWM_init();
While(1)
{
PWMMR1=75000;
PWMMR2=100000;
PWMLER=0X06;
}
 Example 2
Let us consider
PWMMR0=200000
PWM Channels selected are PWM3 and PWM5
Let
PWMMR3=150000
PWMMR5= 50000
Calculate the Ton time for both and the total
time period
 Calculations(PWM Resolution)
• PWM block derives its clock from the Peripheral Clock (PCLK) which
is clocked at 60 MHz. So, to get a time required for PCLK to run for
‘X’ clock cycles at 60 MHz is

X / (60 * 10^6).
• If the Prescale is considered, then X = PR + 1. So, when we consider
the Prescale value to be 59, then we get a delay of

Delay = (59 + 1) / (60 * 10^6) = 1 microsecond (1 µS).

Similarly, if we set the PR to 59999, then we get a delay of

Delay = (59999 + 1) / (60 * 10^6) = 1 millisecond (1 mS).

 Program
Develop a logic and write an embedded C
program to control the brightness of LED
connected at Pin P0.21 of LPC2148. We will be
using period of 10ms. We also have to connect
two Switches at Pin P1.16 & P1.17 which
controls the pulse width and so when we press
any switch among these. We will get equivalent
brightness.
#include <lpc21xx.h>

void initPWM(void); // Initialize PWM

void initClocks(void); // Setup PLL and Clock Frequency

int main()
{
PINSEL1=(0x04<<8); // pin P0.21 the channel 5 of PWM connect LED to this pin

initClocks(); //Initialize CPU and Peripheral Clocks @ 60Mhz

initPWM(); //Initialize PWM

while(1)
{
if( !((IO1PIN) & (1<<16)) ) // Check P1.16
{
PWMMR5 = 2500; //T-ON=25% , Hence 25% Bright
PWMLER = (1<<5) ; //Update Latch Enable bit for PWMMR5
}
else if( !((IO1PIN) & (1<<17)) ) // Check P1.17
{
PWMMR5 = 5000; //50% Bright
PWMLER = (1<<4);
} 5
}
}
void initPWM(void)
{
PINSEL0 = (PINSEL0 & ~(1 << 16)) | (1 << 17); // Select PWM4 output for Pin0.8
PWMPCR = 0x0; //Select Single Edge PWM - by default its single Edged so this line can be removed
PWMPR = 60-1; // 1 micro-second resolution
PWMMR0 = 10000; // 10ms period duration
PWMMR5 = 500; // 0.5ms - pulse duration i.e width (Brigtness level)
PWMMCR = (1<<1); // Reset PWMTC on PWMMR0 match
PWMLER = (1<<0)|(1<<5); // update MR0 and MR5
PWMPCR = (1<<13); // enable PWM output
PWMTCR = (1<<1) ; //Reset PWM TC & PR
PWMTCR = (1<<0) | (1<<3); // enable counters and PWM Mode
//PWM Generation goes active now - LED must be 25% Bright after boot!!Now you can get the PWM output at Pin P0.21!
}
void initClocks(void)
{
PLL0CON = 0x01; //Enable PLL
PLL0CFG = 0x24; //Multiplier and divider setup
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
while(!(PLL0STAT & 0x00000400)); //is locked?
PLL0CON = 0x03; //Connect PLL after PLL is locked
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
VPBDIV = 0x01; // PCLK is same as CCLK i.e.60 MHz
}
 Program
Write a Program to generate a double edge
controlled PWM on PWM3 (P0.1)
 Watchdog Timer
Introduction
• Watchdog Timer (WDT) can be helpful to automatically reset the system
whenever a timeout occurs.
• System reset is required for preventing failure of the system in a situation
of a hardware fault or program error.
• There are countless applications where the system cannot afford to get
stuck at a point (not even for a small duration of time). For example, in a
radar system, if the system hangs for 5 minutes, it can result in serious
repercussions (an enemy plane or missile may go undetected resulting in
huge losses).
• The system should be robust enough to automatically detect the failures
quickly and reset itself in order to recover from the failures and function
normally without errors.
• One can manually reset the system to recover from errors. But it is not
always feasible to manually reset the system, especially once it has been
deployed.
• To overcome such problems, a watchdog timer is necessary to
automatically reset the system without human intervention.
 Watchdog Timer
• A WDT is a hardware that contains a timing
device and clock source. A timing device is a
free-running timer, which is set to a certain
value that gets decremented continuously.
When the value reaches zero, a short pulse is
generated by WDT circuitry that resets and
restarts the system.
 LPC2148 Watchdog Timer
LPC2148 has an inbuilt watchdog timer. The watchdog when
enabled generates a system reset if the user program fails to
feed (or reload) the watchdog within a predetermined amount
of time.

• The watchdog consists of a fixed divide by 4 prescalar and a 32-bit counter. The
clock is fed to the timer through the prescalar.
• The counter can be loaded with any value between 0xFF and 0xFFFFFFFF. If the
counter is loaded with any value less than 0xFF, the counter is initialized with a
value 0xFF.
• The watchdog needs to be fed with a pre-determined sequence of 0xAA followed
by 0x55 before watchdog timer underflows to prevent reset/interrupt.
 Associated Registers
• WDMOD(watchdog mode register)
• WDTC(Timer Constant)
• WDFEED(Feed Register)
• WDTV(Timer value register)
Steps to program WDT
WDMOD Register
 Cont..

• Bit 0 – WDEN (Watchdog Interrupt Enable)

• Bit 1 – WDRESET (Watchdog Reset Enable)

• Bit 2 – WDTOF (Watchdog Time-Out Flag)

This bit is set when the watchdog times out.It is cleared by software.
• Bit 3 – WDINT (Watchdog Interrupt Flag)

This bit is set when the watchdog times out. This bit is cleared when any reset
occurs. It is a read only bit
WDTC
WDFEED
WDTV
Block Diagram of WDT
 Program
• Write an embedded C program to show the
operation of Watchdog timer by creating the
hanging of the system in the program.
 Program
Steps given below:
• Set the watchdog timer constant reload value in the
WDTC register.
• Select the mode using the WDMOD register
• Start the watchdog by feeding it with 0xAA followed by
0x55 in the WDFEED register
• Make sure to feed the watchdog again before the timer
counter underflows in order to prevent reset/interrupt
• The Watchdog Time-Out Flag (WDTOF) can be
monitored to determine if the watchdog has caused
reset condition. The WDTOF flag must be cleared using
software.
 Program
• Write an embedded C program to show the
operation of Watchdog timer by creating the
hanging of the system in the program.
Consider the watchdog time interval be
139ms. Indicate the reset of the system by
turning ON the LED connected to P0.16.
#include<lpc214x.h>
void delay(int x)
{
while(x--);
}

int main()
{
IO0DIR=(1<<16)|(0xF<<0);
if(WDMOD & 0x04)
{
IO0CLR=(1<<16);
IO0SET=(1<<16);
delay(500);
IO0CLR=(1<<16);
delay(500);
}
WDTC=0X000000ff;
WDMOD=0X00000003;
WDFEED=0X000000AA;
WDFEED=0X00000055;
while(1)
{
}

}
Vectored Interrupt Controller(VIC)
VIC LPC2148
Register in VIC
VICIntSelect (R/W)
VICIntEnable (R/W)
VICIntEnClr (R/W)
VICIRQStatus (Read)
VICFIQStatus (Read)
VICSoftInt
VICSoftIntClear
VICVectCntI0 to VICVectCntI15
Important Note
VICVectAddr0 to VICVectAddr15
VICVectAddr
 program
• Write an embedded C program to blink LED’s
using timer0 interrupt.
#include <lpc214x.h>
void initClocks(void);
void initTimer0(void);
__irq void timer0ISR(void);
int main(void){
initClocks(); // Initialize PLL to setup clocks
initTimer0(); // Initialize Timer0
IO0DIR = (1<<10); // Configure pin P0.10 as Output
IO0PIN = (1<<10);
T0TCR = (1<<0); // Enable timer
while(1); // Infinite Idle Loop
}
void initTimer0(void)
{
T0CTCR = 0x0; //Set Timer Mode
T0PR = 60000-1; //Increment T0TC at every 60000 clock cycles //60000 clock cycles @60Mhz = 1 mS
T0MR0 = 500-1; //Zero Indexed Count-hence subtracting 1
T0MCR = (1<<0) | (1<<1);//Set bit0 & bit1 to Interrupt & Reset TC on MR0
VICVectAddr4 = (unsigned )timer0ISR; //Pointer Interrupt Function (ISR)
VICVectCntl4 = (1<<5) | 4; //(bit 5 = 1)->to enable Vectored IRQ slot //bit[4:0]) -> this the source number
VICIntEnable = (1<<4); // Enable timer0 interrupt
T0TCR = (1<<1); // Reset Timer
}
__irq void timer0ISR(void)
{
long int readVal;
readVal = T0IR; // Read current IR value
IO0PIN ^= (1<<10); // Toggle LED at Pin P0.10
T0IR = readVal; // Write back to IR to clear Interrupt Flag
VICVectAddr = 0x0; // End of interrupt execution
}
void initClocks(void){
PLL0CON = 0x01; //Enable PLL
PLL0CFG = 0x24; //Multiplier and divider setup
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
while(!(PLL0STAT & 0x00000400)); //is locked
PLL0CON = 0x03; //Connect PLL after PLL is locked
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
VPBDIV = 0x01; } //PCLK is same as CCLK i.e.60 MHz
 External Interrupts
Associated Registers
1. EXTMODE
2. EXTPLOLAR
3. EXTINT
 Program
• Write an embedded C program to toggle LED’s
using external interrupt
#include<LPC2xx.h>
void Ext_Int()__irq
{
IO0SET|=(1<<17);
delay();
IO0CLR|=(1<<17);
delay();
EXTINT=0x01 //clear interrupt
VICVectAddr=0x00 // ISR execution completed
}
int main()
{
PINSEL1=0X01; // P0.16 EXTERNAL INTERRUPT 0
IO0DIR|=(1<<17);
EXTMODE=0X0; // LEVEL SENSITIVE
EXTPOLAR=0X01; // HIGH LEVEL SENSITIVE
VICVectCntI0=0x20 | 14 // 5th bit for enable interrupt
VICIntSelect=0x0; // IRQ interrupt
VICIntEnable=0x00004000 // Enable 14th pin for EXTINT0
while(1);
}