CD74AC540, CD74ACT540, CD54ACT540, CD74AC541, CD54AC541, CD74ACT541, CD54ACT541

SCHS285B – DECEMBER 1998 – REVISED MAY 2024

CD74AC540, CDx4ACT54x, CDx4AC541 Octal Buffer/Line Drivers, 3-State

1 Features CMOS technology. The CD54/74AC/ACT540 are
inverting 3-state buffers having two active-LOW
• SCR-latchup-resistant CMOS process and circuit
output enables. The CD54/74AC/ACT541 are non-
design
inverting 3-state buffers having two active-LOW
• Speed of bipolar FAST®/AS/S with significantly
output enables.
reduced power consumption
• Balanced propagation delays Device Information
• AC types feature 1.5V to 5.5V operation and PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)

balanced noise immunity at 30% of the supply. CD74AC540,

DW (SOIC, 20) 12.8mm x 10.3mm 12.8mm x 7.5mm

• ±24mA output drive current CDx4ACT54x, DB (SSOP, 20) 7.2mm x 7.8mm 7.2mm x 5.3mm
CDx4AC541
– Fanout to 15 FAST®ICs N (PDIP, 20) 24.33mm x 9.4mm 24.33mm x 6.35mm

– Drives 50Ohm transmission lines (1) For all available packages, see Section 10.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
2 Description (3) The body size (length × width) is a nominal value and does
not include pins.
The CD54/74AC540, -541, and CD54/74ACT540,
-541 octal buffer/line drivers use the RCA ADVANCED

Functional Block Diagram

®FAST is a Registered Trademark of Fairchild Semiconductor Corp.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD74AC540, CD74ACT540, CD54ACT540, CD74AC541, CD54AC541, CD74ACT541, CD54ACT541
SCHS285B – DECEMBER 1998 – REVISED MAY 2024 www.ti.com

Table of Contents
1 Features............................................................................1 6.2 Functional Block Diagram......................................... 11
2 Description.......................................................................1 6.3 Device Functional Modes..........................................11
3 Pin Configuration and Functions ..................................3 7 Application and Implementation.................................. 12
4 Specifications.................................................................. 4 7.1 Power Supply Recommendations.............................12
4.1 Absolute Maximum Ratings........................................ 4 7.2 Layout....................................................................... 12
4.2 ESD Ratings............................................................... 4 8 Device and Documentation Support............................13
4.3 Recommended Operating Conditions.........................4 8.1 Documentation Support (Analog)..............................13
4.4 Thermal Information....................................................4 8.2 Receiving Notification of Documentation Updates....13
4.5 Electrical Characteristics, AC Series.......................... 5 8.3 Support Resources................................................... 13
4.6 Electrical Characteristics, ACT Series........................ 6 8.4 Trademarks............................................................... 13
4.7 Switching Characteristics, AC Series..........................7 8.5 Electrostatic Discharge Caution................................13
4.8 Switching Characteristics, ACT Series....................... 8 8.6 Glossary....................................................................13
5 Parameter Measurement Information............................ 9 9 Revision History............................................................ 13
6 Detailed Description...................................................... 11 10 Mechanical, Packaging, and Orderable
6.1 Overview................................................................... 11 Information.................................................................... 14

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3 Pin Configuration and Functions

Figure 3-1. CDx4AC540, CDx4ACT540 Figure 3-2. CDx4AC541, CDx4ACT541

Table 3-1. Pin Functions

PIN
NO. NAME I/O1 DESCRIPTION
!MR 1 I Master reset, active low
Q0 2 O Output Q0
D0 3 I Input D0
D1 4 I Input D1
Q1 5 O Output Q1
Q2 6 O Output Q2
D2 7 I Input D2
D3 8 I Input D3
Q3 9 O Output Q3
GND 10 - Ground
CP 11 I Clock, rising edge triggered
Q4 12 O Output Q4
D4 13 I Input D4
D5 14 I Input D5
Q5 15 O Output Q5
Q6 16 O Output Q6
D6 17 I Input D6
D7 18 I Input D7
Q7 19 O Output Q7
VCC 20 - Supply

1. I = input, O = output, P = power, FB = feedback, GND = ground, N/A = not applicable

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4 Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage −0.5 6 V
IIK Input diode current (VI < −0.5 or VI > VCC + 0.5 V) ±20 mA
IOK Output diode current (VO < −0.5 or VO > VCC + 0.5 V) ±50 mA
IO Output source or sink current per output PIN (VO > −0.5 or VO < VCC + 0.5 V) ±50 mA
Vcc or ground current, ICC or IGND (1) ±100 mA
Tstg Storage temperature −65 +150 °C

(1) For up to 4 outputs per device: add ±25 mA for each additional output.

4.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/
V(ESD) Electrostatic discharge ±2000 V
JEDEC JS-0011

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage
(For TA = full package-temperature range)
AC types 1.5 5.5 V
ACT types 4.5 5.5 V
VI, VO Input or output voltage 0 VCC V
TA Operating temperature -55 +125 °C
dt/dv Input rise and fall slew rate
at 1.5V to 3V (AC types) 0 50 ns/V
at 3.6V to 5.5V (AC types) 0 20 ns/V
at 4.5V to 5.5V (ACT types) 0 10 ns/V

(1) Unless otherwise specified, all voltages are referenced to ground.

4.4 Thermal Information

CD74AC540, CDx4ACT54x, CDx4AC541
THERMAL METRIC(1) N (PDIP) DW (SOIC) UNIT
20 PINS 20 PINS
RθJA Thermal Resistance 69 101.2 °C/W

(1) The package thermal impedance is calculated in accordance with JESD 51.

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4.5 Electrical Characteristics, AC Series

PARAMETER (TA) - °C
TEST CONDITIONS
VCC (V) +25 -40 to +85 -55 to +125 UNIT
VI (V) IO (mA) MIN MAX MIN MAX MIN MAX
1.5 1.2 — 1.2 — 1.2 —
High-level input
VIH 3 2.1 — 2.1 — 2.1 — V
voltage
5.5 3.85 — 3.85 — 3.85 —
1.5 — 0.3 — 0.3 — 0.3
Low-level input
VIL 3 — 0.9 — 0.9 — 0.9 V
voltage
5.5 — 1.65 — 1.65 — 1.65
-0.05 1.5 1.4 — 1.4 — 1.4 —
-0.05 3 2.9 — 2.9 — 2.9 —
-0.05 4.5 4.4 — 4.4 — 4.4 —
High-level output VIH or VIL
VOH (1), (2) -4 3 2.58 — 2.48 — 2.4 — V
voltage
-24 4.5 3.94 — 3.8 — 3.7 —
-75 5.5 — — 3.85 — — —
-50 5.5 — — — — 3.85 —
0.05 1.5 — 0.1 — 0.1 — 0.1
0.05 3 — 0.1 — 0.1 — 0.1
0.05 4.5 — 0.1 — 0.1 — 0.1
Low-level output VIH or VIL
VOL (1), (2) 12 3 — 0.36 — 0.44 — 0.5 V
voltage
24 4.5 — 0.36 — 0.44 — 0.5
75 5.5 — — — 1.65 — —
50 5.5 — — — — — 1.65
VCC or
II Input leakage current 5.5 — ±0.1 — ±1 — ±1 μA
GND
VIH or VIL
3-state leakage
IOZ VO = VCC 5.5 — ±0.5 — ±5 — ±10 µA
current
or GND
Quiescent supply VCC or
ICC 0 5.5 — 8 — 80 — 160 µA
current, MSI GND

(1) Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to
minimize power dissipation.
(2) Test verifies a minimum 50-ohm transmission-line-drive capability at +85°C, 75 ohms at +125°C.

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4.6 Electrical Characteristics, ACT Series

PARAMETER (TA) - °C
TEST CONDITIONS
VCC (V) +25 -40 to +85 -55 to +125 UNIT
VI (V) IO (mA) MIN MAX MIN MAX MIN MAX
High-level input
VIH 4.5 to 5.5 2 — 2 — 2 — V
voltage
Low-level input
VIL 4.5 to 5.5 — 0.8 — 0.8 — 0.8 V
voltage
-0.05 4.5 4.4 — 4.4 — 4.4 —

High-level output VIH or VIL -24 4.5 3.94 — 3.8 — 3.7 —

VOH (1), (2) V
voltage -75 5.5 — — 3.85 — — —
-50 5.5 — — — — 3.85 —
0.05 4.5 — 0.1 — 0.1 — 0.1

Low-level output VIH or VIL 24 4.5 — 0.36 — 0.44 — 0.5

VOL (1), (2) V
voltage 75 5.5 — — — 1.65 — —
50 5.5 — — — — — 1.65
VCC or
II Input leakage current 5.5 — ±0.1 — ±1 — ±1 μA
GND
VIH or VIL
3-state leakage
IOZ VO = VCC 5.5 — ±0.5 — ±5 — ±10 μA
current
or GND
Quiescent supply VCC or
ICC 0 5.5 — 8 — 80 — 160 μA
current, MSI GND
Additional quiescent
supply current per
input pin
VCC-2.1 4.5 to 5.5 — 2.4 — 28 — 3 mA
TTL inputs high
ΔICC
1 unit load

(1) Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to
minimize power dissipation.
(2) Test verifies a minimum 50-ohm transmission-line-drive capability at +85°C, 75 ohms at +125°C.

Table 4-1. Act Input Loading Table

UNIT LOAD(2)
INPUT
540 541
DATA 1.42 0.5
OE1, OE2 1.3 1.3

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4.7 Switching Characteristics, AC Series

tr, tl = 3ns, CL = 50pF (See Section 5)
(TA) - °C
PARAMETER VCC (V) -40 to +85 -55 to +125 UNIT
MIN MAX MIN MAX
Propagation Delays:
Data to Output
AC540
tPLH 1.5 – 77 — 85
tPHL 3.3* 2.4 8.6 2.4 9.5 ns
5† 1.8 6.2 1.7 6.8
AC541
tPLH
1.5 — 89 — 98
tPHL
3.3 2.8 9.9 2.7 10.9 ns
5 2.1 7.1 2 7.8
Enable, to Output to Output 1.5 — 136 — 150
tPZL
3.3 4.6 16.4 4.5 18 ns
tPZH
5 3.1 10.9 3 12
Disable to Output to Output 1.5 — 136 — 150
tPLZ
3.3 3.9 13.6 3.8 15 ns
tPHZ
5 3.1 10.9 3 12
Power Dissipation Capacitance AC540 — 60 Typ. 60 Typ.
CPD ‡ pF
AC541 — 60 Typ. 60 Typ.
VOHV Min. (Valley) VOH During
Switching of
Other Outputs
5 4 Typ. @ 25°C V
(Output Under
Test Not
Switching)
VOLP Max. (Peak) VOL During
Switching of
Other Outputs
5 1 Typ. @ 25°C V
(Output Under
Test Not
Switching)
CI Input Capacitance — — 10 — 10 pF
CO 3-State Output Capacitance — — 15 — 15 pF

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4.8 Switching Characteristics, ACT Series

tr, tl = 3ns, CL = 50pF (See Section 5)
(TA) - °C
PARAMETER VCC (V) -40 to +85 -55 to =125 UNIT
MIN MAX MIN MAX
Propagation Delays:
tPLH Data to Output: ACT540 5(1) 1.9 6.5 1.8 7.2 ns
tPHL ACT541 5(1) 2.1 7.5 2.1 8.2 ns
tPZL Enable to Output
5 5 3.5 12.2 3.4 ns
tPZH
tPLZ Disable to Output
5 3.5 12.2 3.4 13.4 ns
tPHZ
Power Dissipation Capacitance
CPD CPD ACT540/
is used to ACT541
determine
the
dynamic — 60 Typ. 60 Typ. pF
power
consumpti
on, per
channel.

VOHV Min. (Valley) VOH

During Switching of Other Outputs (Output Under Test Not
5 4 Typ. @ 25°C V
Switching)
Max. (Peak) VOL
VOLP During Switching of Other Outputs (Output Under Test Not V
5 1 Typ. @ 25°C
Switching)
CI Input Capacitance — — 10 — 10 pF
CO 3-State Output Capacitance — — 15 — 15 pF

(1) 5V: min. is @5.5 V

(2) CPD is used to determine the dynamic power consumption, per channel.

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5 Parameter Measurement Information

A. VOHV AND VOLP ARE MEASURED WITH RESPECT TO A GROUND REFERENCE NEAR THE OUTPUT UNDER TEST,
B. INPUT PULSES HAVE THE FOLLOWING CHARACTERISTICS: PRR ≤ 1 MHz, tr = 3 ns, t( = 3 ns, SKEW 1 ns.
C. R.F. FIXTURE WITH 700-MHz DESIGN RULES REQUIRED. IC SHOULD BE SOLDERED INTO TEST BOARD AND BYPASSED
WITH 0.1 µF CAPACITOR. SCOPE AND PROBES REQUIRE 700-MHz BANDWIDTH.
D. 92CS-42406

Figure 5-1. Simultaneous Switching Transient Waveforms.

Figure 5-2. Three-state Propagation Delay Waveforms and Test Circuit.

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Figure 5-3. Propagation Delay Times and Test Circuit.

CD54/74AC CD54/74ACT
Input Level VCC 3V
input Switching Voltage, VS 0.5 VCC 1.5 V
Output Switching Voltage, VS 0.5 VCC 0.5 VCC

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6 Detailed Description
6.1 Overview
The CD74AC540, -541, and CD74ACT540, -541 are supplied in 20-lead dual-in-line plastic packages (E suffix)
and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the
following temperature ranges: Industrial (−40 to +85°C) and Extended Industrial/Military (−55 to +125°C).
The CD54AC540, -541, and CD54ACT540, -541, available in chip form (H suffix), are operable over the −55 to
+125°C temperature range.
6.2 Functional Block Diagram

6.3 Device Functional Modes

Table 6-1. Truth Table
CD54/74AC/ACT540

INPUTS OUTPUTS

OE1,OE1 A Y

L L H

L H L

H X Z

Table 6-2. Truth Table

CD54/74AC/ACT541

INPUTS OUTPUTS

OE1,OE2 A Y

L L L

L H H

H X Z

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the min and max supply voltage rating located in Section 4.3.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends 0.1 µF and if there are multiple VCC terminals, then TI recommends .01 µF or .022 µF
for each power terminal. It is okay to parallel multiple bypass capacitors to reject different frequencies of noise. A
0.1 µF and 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power
terminal as possible for best results.
7.2 Layout
7.2.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. Specified below are the rules that
must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high
or low bias to prevent them from floating. The logic level that should be applied to any particular unused input
depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense
or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver. If the transceiver
has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the
input section of the I.O’s so they also cannot float when disabled.

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8 Device and Documentation Support

8.1 Documentation Support (Analog)
8.1.1 Related Documentation
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
CD74AC540 Click here Click here Click here Click here Click here
CD54AC541 Click here Click here Click here Click here Click here
CD74AC541 Click here Click here Click here Click here Click here
CD54ACT540 Click here Click here Click here Click here Click here
CD74ACT540 Click here Click here Click here Click here Click here
CD54ACT541 Click here Click here Click here Click here Click here
CD74ACT541 Click here Click here Click here Click here Click here

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 1998) to Revision B (May 2024) Page
• Added Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Device
Functional Modes, Application and Implementation section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ............................................................................. 1
• Updated θJA value: DW = 58 to 101.2, all values in °C/W ................................................................................4

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10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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