MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 Approaches of realizing digital circuits by (MOS) technology
1. switch logic 2. gate logic
switch logic : Realization of digital circuits uses “pass transistors” or
“transmission gates”.
Like relay contacts, to steer logic signals through the device.
gate logic: Realization of digital circuits using inverters and other
conventional gates, as it is typically done in transistor–transistor logic
(TTL) circuits.
Pass-Transistor Logic:
 Assume that the pass transistors are nMOS devices.
 A high-level signal gets degraded as it is steered through an nMOS
pass transistor.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 This effect becomes more prominent when a pass-transistor output is
allowed to drive the gate of another pass-transistor stage.
 Inverter has to be designed with a high inverter ratio (8:1) such that
the gate drive (3.5 V assuming the threshold voltage equal to 1.5 V)
is sufficient enough to drive the inverter output to an acceptable low
level.

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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 For input combination-100 function is “1,” the output will rise to
high level by charging the output load capacitance.
 After that if we apply -010, for which the function is “0,” .
But the output remains at logic level “1” because the output
capacitance does not get a discharge path when input combination of
010 is applied.
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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
Therefore, in synthesizing pass-transistor logic, it is essential to
provide both charging and discharging path for the load
capacitance.
In other words, charging path has to be provided for all input
combinations requiring a high output level and discharge path has
to be provided for all input combinations requiring a low output
level.

Sneak paths which cause current, energy, or logical sequence to flow

along an unexpected path or in an unintended direction. OR
Sneak timing in which events occur in an unexpected or conflicting
sequence.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
1. Realize the Function f = a + b′c using pass-transistor logic.
expansion around the variable “a,” we get f = a.1 + a′.b′c.
Now, Expanding around the variable “b,” we get f = a 1+ a′ (b 0 + b′ c)

Circuit realization based on the above approach is not only area efficient
but also satisfies all the requirements of pass-transistor logic
realization mentioned earlier.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

 Realizing Pass-Transistor Logic
2-to-1 and 4-to-1 multiplexers can be realized by using pass transistor
logic

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5.4a ---Circuit realization may not be optimal in terms of
the number of pass transistors.
Optimal network may be obtained by expanding a function iteratively
using Shannon’s expansion theorem.The variable around which
expansion is done has to be suitably chosen and each reduced function is
further expanded until it is a constant or a single variable.
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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 Pesimistic

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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 Pass-Transistor Logic Families

1. The conventional nMOS pass-transistor logic or complementary

pass-transistor logic (CPL),
2. The dual pass-transistor logic (DPL), and
3. The swing-restored pass-transistor logic (SRPL)

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 COMPLEMENTARY PASS-TRANSISTOR LOGIC (CPL)

Basic structure :Comprises two nMOS pass-transistor logic network

(one for each rail), two small pull-up pMOS transistors for swing
restoration, and two output inverters for the complementary output
signals.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 This is the basic and minimal gate
structure with ten transistors. All two-
input functions can be implemented by
this basic gate structure.

2-to-1 multiplexer realization using CPL logic

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All two-input functions can be implemented by this
basic gate structure.
Realizations of 2-input NAND, NOR, and EX-OR
functions are shown in Fig. 5.8a–c, respectively.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
SWING-RESTORED PASS-TRANSISTOR LOGIC(SRPL)
 Extension of CPL
 Suitable for low-power low-voltage applications.
 Output inverters are cross-coupled with a latch structure, which
performs both swing restoration and output buffering.
 pull-up pMOS transistors are not required anymore and that the
output nodes of the nMOS networks are the gate outputs.

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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
DOUBLE PASS-TRANSISTOR LOGIC
 The DPL is a modified version of CPL
 Both nMOS and pMOS logic networks are used together
 To alleviate the problem of the CPL associated with reduced high
logic level.

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 Transmission gate: consists of two complementary metal-oxide-
semiconductor (CMOS) transistors - one NMOS (n-channel MOS)
and one PMOS (p-channel MOS) transistor.
 These transistors are typically arranged in parallel to form a
transmission gate.
 As the input signal varies from Vdd to 0V, the resistance of the
NMOS and PMOS transistors will also vary.

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 "SHOOT-THROUGH"
The overall resistance of the transmission gate is determined by the
combination of the NMOS and PMOS transistors. During the
transition from 0V to Vdd, there is a period where both transistors
are conducting to some extent. This is known as the "shoot-
through" region. In this region, the resistance of the transmission
gate is relatively low, and both the NMOS and PMOS transistors
contribute to the current flow.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

NAND and NOR gates along with the inverters can be used to
realize any complex Boolean function.
Fan-in is the number of signal inputs that the gate processes to
generate some output.
fan-out is the number of logic inputs driven by a gate.

a. 2-input NAND gate and a four-input NOR

gate with fan-in of 2 and 4, respectively.
b. a four-input NOR gate is shown
with fan-out of 3.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

depletion- type nMOS transistor as a pull-up device and n enhancement-type
nMOS transistors as pull-down devices.
In this kind of realization, the length/width (L/W) ratio of the pull-up and pull-
down transistors should be carefully chosen such that the desired logic levels are
maintained.
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Critical factor here is the low-level output voltage, which should be
sufficiently low such that it turns off the transistors of the following
stages.

To satisfy this, the output voltage should be less than the threshold
voltage, i.e., Vout ≤ Vt = 0.2 Vdd.

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The ratio of Zpu to the sum of all the pull-down Zpds must be at
least 4:1.
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Not only one pull-down transistor is required per input of the NAND
gate stage but also the size of the pull-up transistor has to be adjusted
to maintain the required overall ratio. This requires a considerably
larger area than those of the corresponding nMOS inverter.

Delay increases in direct proportion to the number of inputs. If

each pull-down transistor is kept of minimum size, then each will
represent one gate capacitance at its input and resistance of all the pull-
down transistors will be in series. Therefore, for an n-input NAND
gates, we have a delay of n-times that of an inverter, i.e.,

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An n-input NOR gate -output is low when any one of the pull-down
transistors is on, as it happens in the case of an inverter. As a
consequence, the aspect ratio of the pull-up to any pulldown
transistor will be the same as that of an inverter, irrespective of the
number of inputs of the NOR gate.

The area occupied by the nMOS NOR gate is reasonable, because the
pull-up transistor geometry is not affected by the number of inputs.
The worst-case delay of
an NOR gate is also comparable to the corresponding inverter. As a
consequence, the use of NOR gate in circuit realization is preferred
compared to that of NAND gate, when there is a choice.
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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 CMOS NAND Gates
Fan-in of n having n number of nMOS transistor in series in the pull-
down path and n number of pMOS transistors in parallel in the pull-
up network.
With all the transistors same size, having a width W = Wn = Wp and
length L = Ln = Lp.
If all inputs are tied together, it behaves like an inverter. However,
static and dynamic characteristics are different from that of the
standard inverter.
To determine the inversion point, pMOS transistors in parallel may be
equated to a single transistor with the width n times that of a single
transistor. And nMOS transistors in series may be considered to be
equivalent to have a length equal to n times that of a single transistor.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
This makes the transconductance ratio

As the fan-in number n increases, ratio

(transconductance ratio) decreases leading to
increase in Vinv. i.e with the increase in fan-in,
the switching point (inversion point) moves
towards the right. By ignored the body effect.
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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 Transconductance ratio

**With the increase in fan-in the

a n-input complementary MOS (CMOS) NOR inversion point moves towards
gate and b the equivalent circuit
left for NOR gates, whereas it
moves towards right in case of
NAND gates.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 Switching Characteristics
 Let us consider the series and parallel transistors separately.
 n pull-up pMOS transistors with their gates tied together along with
a load capacitance CL. Intrinsic time constant of this network is given by

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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
In static circuits, the output voltage levels remain unchanged as long as
inputs are kept the same and the power supply is maintained.
nMOS static circuits have two disadvantages:
They draw static current as long as power remains ON, and they require
larger chip area because of “ratioed” logic.

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Charge sharing is a phenomenon that occurs in digital circuits, and
it becomes particularly relevant in the context of dynamic CMOS
(Complementary Metal-Oxide-Semiconductor) circuits. Dynamic
CMOS is a style of digital circuit design that uses dynamic node
charging and discharging to perform logic functions. It is
commonly used in low-power applications due to its reduced
transistor count compared to static CMOS.

In dynamic CMOS circuits, charge sharing can occur during the

evaluation phase of the circuit operation. Let's break down the
process and understand how charge sharing happens:
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1.Precharge Phase:
1.Initially, all nodes in the dynamic circuit are precharged to either
Vdd or GND.
2.This precharging is necessary to ensure that the nodes are at valid
logic levels before the evaluation phase begins.
2.Evaluation Phase:
1.During this phase, the inputs change, and the dynamic nodes are
allowed to discharge or remain charged based on the logic function
being performed.
2.Nodes that need to discharge are connected to the output node
through NMOS transistors.

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3. Charge Sharing:
1.Charge sharing occurs when a node that is in a precharged state is
connected to another node that is not at the same potential.
2.If a precharged node is connected to a discharged node, or vice
versa, there will be a flow of charge between them until they reach a
common voltage level.
3.This flow of charge can cause a temporary drop in voltage at the
precharged node and a corresponding rise in voltage at the
discharged node.

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4. Impact on Operation:
1.Charge sharing can lead to incorrect logic levels on the nodes,
potentially causing glitches and introducing errors in the circuit's
operation.
2.The extent of charge sharing depends on factors such as the
capacitance of the nodes involved, the resistance of the
connecting transistors, and the duration of the evaluation phase.

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5. Mitigation Techniques:
1.To mitigate charge sharing effects, designers employ various
techniques, such as adding additional transistors to the circuit,
adjusting transistor sizes, or using precharge and evaluation
schemes that minimize the likelihood of charge sharing.

Understanding and managing charge sharing is crucial in dynamic

CMOS design to ensure the reliability and correctness of the circuit.
Designers need to carefully analyze the circuit and implement
appropriate techniques to minimize the impact of charge sharing on
circuit performance.

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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 A two-phase nonoverlapping
clock clock has three states and
four edges and satisfies the
property φ1.φ′2 = 0. There is a
dead time, Δ, between
transitions of the clock signals,
And is decided by the delay
through the NAND gates and
the two inverters.

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As the clock (clk) signal goes low, φ1 also goes low after four gate
delays. φ2 can go high after seven gate delays. In a similar manner, as
clk goes high, φ2 goes low after five gate delays and φ1 goes high after
eight gate delays. So φ2 ( φ1) goes high after three gate delays and φ1 (
φ2) goes low. Here the dead time is three gate delays.
A longer dead time can be obtained by inserting more number of
inverters in the feedback path.

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Two-phase clocking gives a great deal of freedom in
designing circuits. When the clock Φ2 is high, the
intrinsic capacitor charges to Vdd through Q1. And clock
Φ1, which comes after Φ2 performs the evaluation.

Vin -high, Q2 is turned ON and since Q3 is ON, the capacitor

discharges to the GND level and the output V0 attains low logic level.
Vin -low, the Q2 is OFF and there is no path for the capacitor to
discharge. Therefore, the output V0 remains at high logic level.
It may be noted that the pull-up and pull-down transistors are never
simultaneously ON.

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 The circuit has no DC current path regardless of the state of the
clocks or the information stored on the parasitic capacitors.
 Moreover, the output is not ratioed, i.e., the low-level output is
independent of the relative value of the aspect ratio of the
transistors.
 That’s why the circuits based on two-phase clocking are often termed
as ratioless and powerless.
 Moreover, in dynamic circuits, there can be at the most one transition
 per clock cycles, and therefore there cannot be multiple spurious
transitions called glitches, which can take place in static CMOS
circuits. Like inverter, NAND, NOR, and other complex functions can
be realized by replacing Q2 with a network of two or more nMOS
transistors.
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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 Advantages of Dynamic MOS Circuits
 The number of transistors required for a circuit with fan-in N is ( N
+2) , in contract to 2 N in case of state CMOS circuit.
 Load capacitance is substantially lower than that for static CMOS
circuits.
 This is about 50 % less than static CMOS and is closer to that of
nMOS (or pseudo nMOS) circuits.
 But, here full pull-down (or pull-up) current is available for
discharging (or charging) the output capacitance.
 dynamic circuits provide superior (area-speed product) performance
compared to its static counterpart.
 Dynamic NOR gate is about five times faster than the static CMOS
NOR gate. The speed advantage is due to smaller output capacitance
and reduced overlap current.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 Charge Leakage Problem
The source–drain diffusions form parasitic diodes with the substrate. If
the source (or drain) is connected to a capacitor CL with some charge on
it, the charge will be slowly dissipated through the reversebiased
parasitic diode. Current doubles for every
10 °C increase in temperature.
Subthreshold leakage current: Even
when the transistor is OFF and the current
can still flow from the drain to source.
This component of current increases when the gate voltage is above
zero and as it approaches the threshold voltage, this effect becomes more
pronounced. A sufficiently high threshold voltage Vt is recommended to
alleviate this problem.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 Charge Sharing Problem
C1 and C2 are connected to node A through two switches representing
the MOS transistors. Before the switches are closed, the charge on CL is
given by QA = VddCL and charges at node B and C are QB = 0 and QC =
0, respectively.
After the switches are closed, there will be a redistribution of charges
based on the charge conservation principle, and the voltage VA at
node A is given by
If C1 = C2 = 0.5 CL, then VA = 0.5
Vdd. This may not only lead to incorrect
interpretation of the output but also
results in the high-static-power
dissipation of the succeeding stage.
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A weak pMOS (low W/L) is added as a pull-up transistor.The transistor
always remains ON and behaves like a pseudo-nMOS circuit during the
evaluation phase. Although there is static power dissipation due to this
during evaluation phase, it helps to maintain the voltage by replenishing
the charge loss due to the leakage current or charge sharing.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

 Clock Skew Problem
It is not uncommon to use several stages of dynamic circuits to
realize a Boolean function. Same clock is applied to all these stages, it
suffers delay due to resistance and parasitic capacitances associated with
the wire that carry the clock pulse and this delay is approximately
proportional to the square of the length of the wire.

Different amounts of delays are experienced at different points in the

circuit and the signal-state changes that are supposed to occur
simultaneously may never actually occur at the same time. This is
known as clock skew problem and it results in hazard and race
conditions.
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Domino logic and low levels, respectively

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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
SYNCHRONOUS SYSTEM: all components are supposed to be
triggered by the same clock signal to maintain proper timing and
synchronization.
Due to Differences in trace lengths, Manufacturing variations, and
Temperature gradients, the clock signal may reach different
components at slightly different times.
CLOCK SKEW :Variation in arrival times of a clock signal at different
elements of a synchronous digital circuit.
lead to 1. performance and reliability issues in digital circuits.
2. Setup and hold time violations, impacting the stability of the flip-
flops and potentially leading to incorrect operation of the circuit.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

 NORA (NOR-2-AND) logic is a technique used to mitigate the effects
of clock skew.
 NORA logic:Traditional flip-flops are replaced with a combination of
NOR gates and AND gates.
 Basic idea is to use a NOR gate to form a latch, and then use an AND
gate to control the latch operation.
 approach among various techniques used to enhance the robustness
of synchronous circuits in the presence of clock skew.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.